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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [tcReset.v] - Blame information for rev 3

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`include "timescale.v"
`include "defines.v"
 
 
module tcReset (tcResetEn, resetIn, tcAddr, resetOut);
 
        input tcResetEn, resetIn;
        input [`tcAddrLen-1:0] tcAddr;
 
        output [`tcNumbers-1:0] resetOut;
 
        reg [`tcNumbers-1:0] resets;
 
 
        always @ *
        begin
                if (tcResetEn)
                begin
                        resets[tcAddr] = resetIn;
                end
        end
 
        assign resetOut = resets;
 
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv
2			`include "timescale.v"
3			`include "defines.v"
4
5
6			`module tcReset (tcResetEn, resetIn, tcAddr, resetOut);`
7
8			`input tcResetEn, resetIn;`
9			input [`tcAddrLen-1:0] tcAddr;
10
11			output [`tcNumbers-1:0] resetOut;
12
13			reg [`tcNumbers-1:0] resets;
14
15
16			`always @ *`
17			`begin`
18			`if (tcResetEn)`
19			`begin`
20			`resets[tcAddr] = resetIn;`
21			`end`
22			`end`
23
24			`assign resetOut = resets;`
25
26
27			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [tcReset.v] - Blame information for rev 3