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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [timer_all.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module timer (clk, en, reset, type, preset, DN, TT, ACC);
 
        input clk, en, reset;
        input [`tcTypeLen-1:0] type;
        input [`tcPresetLen-1:0] preset;
 
        output DN, TT;
        output [`tcAccLen-1:0] ACC;
 
        reg DN = 0, TT = 0;
        reg [`tcAccLen-1:0] ACC = 0;
 
        reg [`tcTypeLen-1:0]     TimerType;
        reg [`tcTypeLen-1:0]     typeNext;
 
 
 
        parameter       OnDelayTimer                    = `tcTypeLen'b0;
        parameter       OffDelayTimer                   = `tcTypeLen'b1;
        parameter       RetOnDelayTimer         = `tcTypeLen'b10;
        parameter       defaultType                             = `tcTypeLen'b11;
 
        always @ (type)
        begin
                case (type)
 
                `timerType1             :       begin
                                                                typeNext = OnDelayTimer;
                                                                end
 
                `timerType2             :       begin
                                                                typeNext = OffDelayTimer;
                                                                end
 
                `timerType3             :       begin
                                                                typeNext = RetOnDelayTimer;
                                                                end
 
                default                 :       begin
 
                                                                $display("\nTimer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");
                                                                end
 
                endcase
        end
 
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset)
                begin
                        $write ("\ntimer module is reset        ");
                        TimerType = defaultType;
                end
                else
                begin
                        TimerType = typeNext;
                end
        end
 
 
        always @ (posedge clk)
        begin
 
 
                case (TimerType)
 
                OnDelayTimer    :       begin
                                                                                if (reset)
                                                                                begin
                                                                                        ACC = `tcAccLen'b0;
                                                                                        DN = 1'b0;
                                                                                        TT = 1'b0;
                                                                                end
                                                                                else
                                                                                begin
                                                                                        if (en)
                                                                                        begin
                                                                                                if (ACC < preset)
                                                                                                begin
                                                                                                        ACC = ACC + 1'b1;
                                                                                                        DN = 1'b0;
                                                                                                        TT = 1'b1;
                                                                                                end
                                                                                                else if (ACC >= preset)
                                                                                                begin
                                                                                                        ACC = ACC;
 
                                                                                                        DN = 1'b1;
                                                                                                        TT = 1'b0;
                                                                                                end
                                                                                        end
                                                                                        else
                                                                                        begin
                                                                                                ACC = `tcAccLen'b0;     // if not enabled
                                                                                                DN = 1'b0;
                                                                                                TT = 1'b0;
                                                                                        end
                                                                                end
                                                                        end     // end this case
 
                OffDelayTimer   :       begin                                                   // not correct implementation!
                                                                                if (reset)
                                                                                begin
                                                                                        ACC = `tcAccLen'b0;
                                                                                        DN = 1'b0;
                                                                                        TT = 1'b0;
                                                                                end
                                                                                else
                                                                                begin
                                                                                        if (!en)
                                                                                        begin
                                                                                                if (ACC < preset)
                                                                                                begin
                                                                                                        ACC = ACC + 1'b1;
                                                                                                        DN = 1'b0;
                                                                                                        TT = 1'b1;
                                                                                                end
                                                                                                else if (ACC >= preset)
                                                                                                begin
                                                                                                        ACC = ACC;
                                                                                                        DN = 1'b1;
                                                                                                        TT = 1'b0;
                                                                                                end
                                                                                        end
                                                                                        else
                                                                                        begin
                                                                                                ACC = `tcAccLen'b0;     // if not enabled
                                                                                                DN = 1'b0;
                                                                                                TT = 1'b0;
                                                                                        end
                                                                                end
                                                                        end     // end this case
 
                RetOnDelayTimer :       begin
 
                                                                                if (reset)
                                                                                begin
                                                                                        ACC = `tcAccLen'b0;
                                                                                        DN = 1'b0;
                                                                                        TT = 1'b0;
                                                                                end
                                                                                else
                                                                                begin
                                                                                        if (en)
                                                                                        begin
                                                                                                if (ACC < preset)
                                                                                                begin
                                                                                                        ACC = ACC + 1'b1;
                                                                                                        DN = 1'b0;
                                                                                                        TT = 1'b1;
                                                                                                end
                                                                                                else if (ACC >= preset)
                                                                                                begin
                                                                                                        ACC = ACC;
                                                                                                        DN = 1'b1;
 
 
 
 
                                                                                                        TT = 1'b0;
                                                                                                end
                                                                                        end
                                                                                        else
                                                                                        begin
                                                                                                ACC = ACC;      // retain ACC
                                                                                                DN = 1'b0;
                                                                                                TT = 1'b0;
                                                                                        end
                                                                                end
                                                                        end     // end this case
 
 
                                default         :       begin
                                                                        if (!reset)
                                                                        $display("\nError in timer type ");
                                                                        end
 
                                endcase
 
        end
 
 
endmodule

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [timer_all.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45	7	maheshpalv	`module timer (clk, en, reset, type, preset, DN, TT, ACC);`
46
47			`input clk, en, reset;`
48			input [`tcTypeLen-1:0] type;
49			input [`tcPresetLen-1:0] preset;
50
51			`output DN, TT;`
52			output [`tcAccLen-1:0] ACC;
53
54			`reg DN = 0, TT = 0;`
55			reg [`tcAccLen-1:0] ACC = 0;
56
57			reg [`tcTypeLen-1:0] TimerType;
58			reg [`tcTypeLen-1:0] typeNext;
59
60
61
62			parameter OnDelayTimer = `tcTypeLen'b0;
63			parameter OffDelayTimer = `tcTypeLen'b1;
64			parameter RetOnDelayTimer = `tcTypeLen'b10;
65			parameter defaultType = `tcTypeLen'b11;
66
67			`always @ (type)`
68			`begin`
69			`case (type)`
70
71			`timerType1 : begin
72			`typeNext = OnDelayTimer;`
73			`end`
74
75			`timerType2 : begin
76			`typeNext = OffDelayTimer;`
77			`end`
78
79			`timerType3 : begin
80			`typeNext = RetOnDelayTimer;`
81			`end`
82
83			`default : begin`
84
85	8	maheshpalv	`$display("\nTimer is defined for unknown type.\n Valid types: On-delay, Off-delay, retentive-on-delay");`
86	7	maheshpalv	`end`
87
88			`endcase`
89			`end`
90
91
92			`always @ (posedge clk or posedge reset)`
93			`begin`
94			`if (reset)`
95			`begin`
96	8	maheshpalv	`$write ("\ntimer module is reset ");`
97	7	maheshpalv	`TimerType = defaultType;`
98			`end`
99			`else`
100			`begin`
101			`TimerType = typeNext;`
102			`end`
103			`end`
104
105
106			`always @ (posedge clk)`
107			`begin`
108
109
110			`case (TimerType)`
111
112			`OnDelayTimer : begin`
113			`if (reset)`
114			`begin`
115			ACC = `tcAccLen'b0;
116			`DN = 1'b0;`
117			`TT = 1'b0;`
118			`end`
119			`else`
120			`begin`
121			`if (en)`
122			`begin`
123			`if (ACC < preset)`
124			`begin`
125			`ACC = ACC + 1'b1;`
126			`DN = 1'b0;`
127			`TT = 1'b1;`
128			`end`
129			`else if (ACC >= preset)`
130			`begin`
131			`ACC = ACC;`
132
133			`DN = 1'b1;`
134			`TT = 1'b0;`
135			`end`
136			`end`
137			`else`
138			`begin`
139			ACC = `tcAccLen'b0; // if not enabled
140			`DN = 1'b0;`
141			`TT = 1'b0;`
142			`end`
143			`end`
144			`end // end this case`
145
146			`OffDelayTimer : begin // not correct implementation!`
147			`if (reset)`
148			`begin`
149			ACC = `tcAccLen'b0;
150			`DN = 1'b0;`
151			`TT = 1'b0;`
152			`end`
153			`else`
154			`begin`
155			`if (!en)`
156			`begin`
157			`if (ACC < preset)`
158			`begin`
159			`ACC = ACC + 1'b1;`
160			`DN = 1'b0;`
161			`TT = 1'b1;`
162			`end`
163			`else if (ACC >= preset)`
164			`begin`
165			`ACC = ACC;`
166			`DN = 1'b1;`
167			`TT = 1'b0;`
168			`end`
169			`end`
170			`else`
171			`begin`
172			ACC = `tcAccLen'b0; // if not enabled
173			`DN = 1'b0;`
174			`TT = 1'b0;`
175			`end`
176			`end`
177			`end // end this case`
178
179			`RetOnDelayTimer : begin`
180
181			`if (reset)`
182			`begin`
183			ACC = `tcAccLen'b0;
184			`DN = 1'b0;`
185			`TT = 1'b0;`
186			`end`
187			`else`
188			`begin`
189			`if (en)`
190			`begin`
191			`if (ACC < preset)`
192			`begin`
193			`ACC = ACC + 1'b1;`
194			`DN = 1'b0;`
195			`TT = 1'b1;`
196			`end`
197			`else if (ACC >= preset)`
198			`begin`
199			`ACC = ACC;`
200			`DN = 1'b1;`
201
202
203
204
205			`TT = 1'b0;`
206			`end`
207			`end`
208			`else`
209			`begin`
210			`ACC = ACC; // retain ACC`
211			`DN = 1'b0;`
212			`TT = 1'b0;`
213			`end`
214			`end`
215			`end // end this case`
216
217
218			`default : begin`
219			`if (!reset)`
220	8	maheshpalv	`$display("\nError in timer type ");`
221	7	maheshpalv	`end`
222
223			`endcase`
224
225			`end`
226
227
228			`endmodule`