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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                );
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
 
// wires (interconnects) of execution unit
 
        wire    [`instAddrLen-1:0]                       pcOut;
        wire    [`instOpCodeLen+`instFieldLen-1:0] romOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOutData, outputReadOut;
 
        wire branchOutc;
        wire [`accMuxSelLen-1:0] accMuxSelOutc;
        wire accEnOutc;
        wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
        wire aluEnc;
        wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
        wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
        wire outputRwOutc;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc;
        `endif
        `ifdef UART_peripheral
        wire uartReadOutc, uartWriteOutc;
        wire [7:0] uartDataOut;
        wire rxEmpty, txFull;
        `endif
 
        wire branchOut;
        wire [`accMuxSelLen-1:0] accMuxSelOut;
        wire accEnOut;
        wire [`op2MuxSelLen-1:0] op2MuxSelOut;
        wire aluEn;
        wire [`aluOpcodeLen-1:0] aluOpcodeOut;
        wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        wire outputRwOut;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;
        `endif
        `ifdef UART_peripheral
        wire uartReadOut, uartWriteOut;
        `endif
 
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
        wire    [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
        wire    [7:0] tcAccOut;
        wire    [7:0] tcLoadOut;
        wire [`tcNumbers-1:0] enWires;
        wire [`tcNumbers-1:0] resetWires;
        wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
        wire [(`tcNumbers*2)-1:0] typeWires;
        wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
 
        wire clk_d, clk_t;
        reg [10:0] cnt = 0;
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset)
                begin
                        cnt =0;
                end
                else
                begin
                        cnt = cnt + 1'b1;
                end
        end
 
        assign clk_d = cnt[0];
        assign clk_t = cnt[10];
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        wire branch = (~romOut[14] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[10]) | ((romOut[10] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[14]) & accOut[0]);                                // END = 00000; JMP = 00001
 
        pgmCounter              ProgramCounter (clk_d, reset, branch, romOut[9:0], pcOut);
 
 
// instruction ROM is declared using xilinx primitive
//      RAMB16_S18 rom ( .DI(),
//                               .DIP(),
//                               .ADDR(pcOut),
//                               .EN(1'b1),
//                               .WE(),   
//                               .SSR(1'b0),
//                               .CLK(clk_d),
//                               .DO(romOut),
//                               .DOP());
 
        rom     CodeMem (clk_d, pcOut, romOut);
 
// pipeline register
 
        wire    [`instOpCodeLen-1:0] instOpCode1;
        wire    [`instFieldLen-1:0] instField1;
        wire    [`instFieldLen-1:0] instField2;
 
        ppReg1  PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
 
        controlUnit             CONTROL_UNIT (clk, reset, instOpCode1, instField2[8:7],
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
 
                                                                                        );
 
 
 
// pipeline register
 
 
 
        ppReg2  PipeLine_Reg2 (clk,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                , instField1
 
                                                                        ,accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
                                                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                                                        outputRwOut
 
                                                                        `ifdef timerAndCounter_peripheral
                                                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut
                                                                        `endif
 
                                                                        `ifdef UART_peripheral
                                                                                , uartReadOut, uartWriteOut
                                                                        `endif
 
                                                                        , instField2
                                                                );
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 (accMuxSelOut, instField2[7:0], aluOut
                                                                                `ifdef timerAndCounter_peripheral
                                                                                , tcLoadOut, tcAccOut
                                                                                `endif
                                                                                `ifdef UART_peripheral
                                                                                , uartDataOut, {rxEmpty, txFull}
                                                                                `endif
                                                                                , accMuxOut
                                                                                );
 
 
        accumulator                     acc             (accMuxOut, accEnOut, accOut);
 
        op2Mux                          op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        wire [7:0] op2Out;
 
        byteNegator                     byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
 
        alu                                     arithLogicUnit  (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
 
        wire bitIn;
 
        bitNegator                      bitNegatorForBitRam     (accOut[0], instField2[9], bitIn);
 
        bitRam                          RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
 
        wire [7:0] byteIn;
 
        byteNegator                     byteNegatorForByteRam   (accOut, instField2[9], byteIn);
 
        byteRam                         RAM_Byte        (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
 
        inputRegister           inputStorage    (IN, instField2[6:0], inputReadOutData);
 
        wire outIn;
 
        bitNegator                      bitNegatorForOutReg     (accOut[0], instField2[9], outIn);
 
        outputReg                       outputStorage   (reset, outputRwOut, instField2[6:0], outIn, outputReadOut, OUT);
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
 
        tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);
 
        tcAccum                         tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
 
        tcReset                         tcResetModule(tcResetEnOut, accOut[0], instField2[3:0], resetWires);
 
        tcPreset                                tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
 
        tcLoad                          tcLoadModule(instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
 
        timer                                   timer0  (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
 
        timer                                   timer1  (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
 
        timer                                   timer2  (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
 
        timer                                   timer3  (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
 
        counter                         counter0        (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
 
        counter                         counter1        (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
 
        counter                         counter2        (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
 
        counter                         counter3        (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
        wire    brgOut;
        wire txDoneTick, txStart;
        wire rxDoneTick;
        wire [7:0] recFifoData, transFifoData;
 
 
        uartTrans       UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
 
        uartRec         UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
 
        uartBrg         UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
 
        uartFifo                UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
 
        uartFifo                UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40
41	3	maheshpalv	`include "timescale.v"
42			`include "defines.v"
43
44			`module top(clk, reset, IN, OUT`
45
46			`ifdef UART_peripheral
47			`, rx, tx`
48			`endif
49
50			`);`
51
52
53			`input clk,reset;`
54			input [`inputNumber-1:0] IN;
55			output [`outputNumber-1:0] OUT;
56
57			`ifdef UART_peripheral
58			`input rx;`
59			`output tx;`
60			`endif
61
62	12	maheshpalv
63	3	maheshpalv	`// wires (interconnects) of execution unit`
64
65	8	maheshpalv	wire [`instAddrLen-1:0] pcOut;
66	5	maheshpalv	wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
67	3	maheshpalv	wire [`instOpCodeLen-1:0] instOpCode;
68			wire [`instFieldLen-1:0] instField;
69
70			`wire [7:0] accMuxOut;`
71			`wire [7:0] accOut;`
72			`wire [7:0] op2MuxOut;`
73			`wire [7:0] aluOut;`
74
75			`wire bitNegatorRamOut, bitOut;`
76			`wire [7:0] byteNegatorRamOut, byteOut;`
77
78	5	maheshpalv	`wire inputReadOutData, outputReadOut;`
79	3	maheshpalv
80	5	maheshpalv	`wire branchOutc;`
81			wire [`accMuxSelLen-1:0] accMuxSelOutc;
82			`wire accEnOutc;`
83			wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
84	6	maheshpalv	`wire aluEnc;`
85	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
86			`wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;`
87	12	maheshpalv	`wire outputRwOutc;`
88	5	maheshpalv	`ifdef timerAndCounter_peripheral
89	12	maheshpalv	`wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc;`
90	5	maheshpalv	`endif
91			`ifdef UART_peripheral
92			`wire uartReadOutc, uartWriteOutc;`
93	7	maheshpalv	`wire [7:0] uartDataOut;`
94			`wire rxEmpty, txFull;`
95	5	maheshpalv	`endif
96	3	maheshpalv
97	5	maheshpalv	`wire branchOut;`
98			wire [`accMuxSelLen-1:0] accMuxSelOut;
99			`wire accEnOut;`
100			wire [`op2MuxSelLen-1:0] op2MuxSelOut;
101	6	maheshpalv	`wire aluEn;`
102	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOut;
103			`wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
104	12	maheshpalv	`wire outputRwOut;`
105	3	maheshpalv	`ifdef timerAndCounter_peripheral
106	12	maheshpalv	`wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut;`
107	5	maheshpalv	`endif
108			`ifdef UART_peripheral
109			`wire uartReadOut, uartWriteOut;`
110			`endif
111	3	maheshpalv
112	5	maheshpalv
113			`// wires (interconnects) of timer & counter`
114
115			`ifdef timerAndCounter_peripheral
116
117			wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
118	7	maheshpalv	`wire [7:0] tcAccOut;`
119	5	maheshpalv	`wire [7:0] tcLoadOut;`
120			wire [`tcNumbers-1:0] enWires;
121			wire [`tcNumbers-1:0] resetWires;
122			wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
123			wire [(`tcNumbers*2)-1:0] typeWires;
124			wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
125
126			`endif
127
128
129	8	maheshpalv	`wire clk_d, clk_t;`
130			`reg [10:0] cnt = 0;`
131	5	maheshpalv
132	8	maheshpalv	`always @ (posedge clk or posedge reset)`
133			`begin`
134			`if (reset)`
135			`begin`
136			`cnt =0;`
137			`end`
138			`else`
139			`begin`
140			`cnt = cnt + 1'b1;`
141			`end`
142			`end`
143	5	maheshpalv
144	8	maheshpalv	`assign clk_d = cnt[0];`
145			`assign clk_t = cnt[10];`
146	3	maheshpalv
147
148
149			`//-------- Fetch Unit Module Instances`
150			`// all necessary`
151	9	maheshpalv
152			`wire branch = (~romOut[14] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[10]) \| ((romOut[10] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[14]) & accOut[0]); // END = 00000; JMP = 00001`
153	3	maheshpalv
154	9	maheshpalv	`pgmCounter ProgramCounter (clk_d, reset, branch, romOut[9:0], pcOut);`
155	3	maheshpalv
156
157			`// instruction ROM is declared using xilinx primitive`
158	9	maheshpalv	`// RAMB16_S18 rom ( .DI(),`
159			`// .DIP(),`
160			`// .ADDR(pcOut),`
161			`// .EN(1'b1),`
162			`// .WE(),`
163			`// .SSR(1'b0),`
164			`// .CLK(clk_d),`
165			`// .DO(romOut),`
166			`// .DOP());`
167	3	maheshpalv
168	9	maheshpalv	`rom CodeMem (clk_d, pcOut, romOut);`
169	3	maheshpalv
170	5	maheshpalv	`// pipeline register`
171
172			wire [`instOpCodeLen-1:0] instOpCode1;
173			wire [`instFieldLen-1:0] instField1;
174			wire [`instFieldLen-1:0] instField2;
175
176	8	maheshpalv	ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
177	5	maheshpalv
178
179			`//-------- Control Unit Module Instance`
180
181	12	maheshpalv	`controlUnit CONTROL_UNIT (clk, reset, instOpCode1, instField2[8:7],`
182	6	maheshpalv	`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
183	12	maheshpalv	`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc`
184	6	maheshpalv	`ifdef timerAndCounter_peripheral
185	12	maheshpalv	`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc`
186	6	maheshpalv	`endif
187			`ifdef UART_peripheral
188			`, uartReadOutc, uartWriteOutcc`
189			`endif
190	5	maheshpalv
191			`);`
192
193
194
195			`// pipeline register`
196
197
198
199			`ppReg2 PipeLine_Reg2 (clk,`
200	6	maheshpalv	`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
201	12	maheshpalv	`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, outputRwOutc`
202	5	maheshpalv	`ifdef timerAndCounter_peripheral
203	12	maheshpalv	`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc`
204	5	maheshpalv	`endif
205			`ifdef UART_peripheral
206			`, uartReadOutc, uartWriteOutcc`
207			`endif
208			`, instField1`
209
210	12	maheshpalv	`,accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,`
211	5	maheshpalv	`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
212	12	maheshpalv	`outputRwOut`
213	5	maheshpalv
214			`ifdef timerAndCounter_peripheral
215	12	maheshpalv	`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut`
216	5	maheshpalv	`endif
217
218			`ifdef UART_peripheral
219			`, uartReadOut, uartWriteOut`
220			`endif
221
222			`, instField2`
223			`);`
224
225
226	3	maheshpalv	`//-------- Execute Unit Modules Instances`
227			`// all necessary`
228
229
230
231
232	5	maheshpalv	`accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut`
233			`ifdef timerAndCounter_peripheral
234			`, tcLoadOut, tcAccOut`
235			`endif
236			`ifdef UART_peripheral
237	7	maheshpalv	`, uartDataOut, {rxEmpty, txFull}`
238	5	maheshpalv	`endif
239			`, accMuxOut`
240			`);`
241
242	3	maheshpalv
243	5	maheshpalv	`accumulator acc (accMuxOut, accEnOut, accOut);`
244	3	maheshpalv
245	5	maheshpalv	`op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);`
246	3	maheshpalv
247	5	maheshpalv	`wire [7:0] op2Out;`
248	3	maheshpalv
249	5	maheshpalv	`byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);`
250	3	maheshpalv
251	6	maheshpalv	`alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);`
252	3	maheshpalv
253	5	maheshpalv	`wire bitIn;`
254	3	maheshpalv
255	5	maheshpalv	`bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);`
256	3	maheshpalv
257	5	maheshpalv	`bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);`
258	3	maheshpalv
259	5	maheshpalv	`wire [7:0] byteIn;`
260	3	maheshpalv
261	5	maheshpalv	`byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);`
262	3	maheshpalv
263	5	maheshpalv	`byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);`
264
265	9	maheshpalv	`inputRegister inputStorage (IN, instField2[6:0], inputReadOutData);`
266	5	maheshpalv
267	11	maheshpalv	`wire outIn;`
268	5	maheshpalv
269	11	maheshpalv	`bitNegator bitNegatorForOutReg (accOut[0], instField2[9], outIn);`
270
271			`outputReg outputStorage (reset, outputRwOut, instField2[6:0], outIn, outputReadOut, OUT);`
272
273	3	maheshpalv
274			`//---------- Timer & Counter Modules`
275			`// optional`
276
277			`ifdef timerAndCounter_peripheral
278
279	5	maheshpalv
280	11	maheshpalv	`tcEnableAndType tcEnableAndTypeModule(entypeEnOut, accOut[0], instField2[5:4], instField2[3:0], enWires, typeWires);`
281	3	maheshpalv
282	7	maheshpalv	`tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);`
283	3	maheshpalv
284	12	maheshpalv	`tcReset tcResetModule(tcResetEnOut, accOut[0], instField2[3:0], resetWires);`
285	3	maheshpalv
286	5	maheshpalv	`tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);`
287	3	maheshpalv
288	12	maheshpalv	`tcLoad tcLoadModule(instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);`
289	3	maheshpalv
290	8	maheshpalv	`timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);`
291	3	maheshpalv
292	8	maheshpalv	`timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);`
293	3	maheshpalv
294	8	maheshpalv	`timer timer2 (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);`
295	3	maheshpalv
296	8	maheshpalv	`timer timer3 (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);`
297	3	maheshpalv
298	5	maheshpalv	`counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);`
299	3	maheshpalv
300	5	maheshpalv	`counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);`
301	3	maheshpalv
302	5	maheshpalv	`counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);`
303	3	maheshpalv
304	5	maheshpalv	`counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);`
305	3	maheshpalv
306			`endif
307
308			`//---------- UART Modules`
309			`// optional`
310
311			`ifdef UART_peripheral
312
313	5	maheshpalv	`wire brgOut;`
314			`wire txDoneTick, txStart;`
315			`wire rxDoneTick;`
316			`wire [7:0] recFifoData, transFifoData;`
317
318	3	maheshpalv
319	5	maheshpalv	`uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);`
320	3	maheshpalv
321	5	maheshpalv	`uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);`
322	3	maheshpalv
323	5	maheshpalv	`uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));`
324	3	maheshpalv
325	5	maheshpalv	`uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);`
326	3	maheshpalv
327	5	maheshpalv	`uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);`
328
329	3	maheshpalv	`endif
330
331			`endmodule`

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