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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                `ifdef SPI_peripheral
                                        , MISO, MOSI, SCK
                                `endif
 
                                );
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
        `ifdef SPI_peripheral
        input MISO;
        output MOSI, SCK;
        `endif
 
// wires (interconnects) of execution unit
 
        wire    [`instAddrLen-1:0]                       pcOut;
        wire    [`instOpCodeLen+`instFieldLen-1:0] romOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOutData, outputReadOut;
 
        wire branchOutc;
        wire [`accMuxSelLen-1:0] accMuxSelOutc;
        wire accEnOutc;
        wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
        wire aluEnc;
        wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
        wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
        wire inputReadOutc, outputRwOutc;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
        `endif
        `ifdef UART_peripheral
        wire uartReadOutc, uartWriteOutc;
        wire [7:0] uartDataOut;
        wire rxEmpty, txFull;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
        `endif
 
        wire branchOut;
        wire [`accMuxSelLen-1:0] accMuxSelOut;
        wire accEnOut;
        wire [`op2MuxSelLen-1:0] op2MuxSelOut;
        wire aluEn;
        wire [`aluOpcodeLen-1:0] aluOpcodeOut;
        wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        wire inputReadOut, outputRwOut;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
        `endif
        `ifdef UART_peripheral
        wire uartReadOut, uartWriteOut;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
        `endif
 
 
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
        wire    [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
        wire    [7:0] tcAccOut;
        wire    [7:0] tcLoadOut;
        wire [`tcNumbers-1:0] enWires;
        wire [`tcNumbers-1:0] resetWires;
        wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
        wire [(`tcNumbers*2)-1:0] typeWires;
        wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
`ifdef SPI_peripheral
 
        wire [7:0] spiStatOut, spiBufOut;
`endif
 
 
        wire clk_d, clk_t;
        reg [10:0] cnt = 0;
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset)
                begin
                        cnt =0;
                end
                else
                begin
                        cnt = cnt + 1'b1;
                end
        end
 
        assign clk_d = cnt[0];
        assign clk_t = cnt[10];
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        wire branch = (~romOut[14] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[10]) | ((romOut[10] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[14]) & accOut[0]);                                // END = 00000; JMP = 00001
 
        pgmCounter              ProgramCounter (clk_d, reset, branch, romOut[9:0], pcOut);
 
 
// instruction ROM is declared using xilinx primitive
//      RAMB16_S18 rom ( .DI(),
//                               .DIP(),
//                               .ADDR(pcOut),
//                               .EN(1'b1),
//                               .WE(),   
//                               .SSR(1'b0),
//                               .CLK(clk_d),
//                               .DO(romOut),
//                               .DOP());
 
        rom     CodeMem (clk_d, pcOut, romOut);
 
// pipeline register
 
        wire    [`instOpCodeLen-1:0] instOpCode1;
        wire    [`instFieldLen-1:0] instField1;
        wire    [`instFieldLen-1:0] instField2;
 
        ppReg1  PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
 
        controlUnit             CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
                                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
 
                                                                                        );
 
 
 
// pipeline register
 
 
 
        ppReg2  PipeLine_Reg2 (clk,
                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
                                                                , instField1
 
                                                                        , branchOut,
                                                                        accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
                                                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                                                        inputReadOut, outputRwOut
 
                                                                        `ifdef timerAndCounter_peripheral
                                                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
                                                                        `endif
 
                                                                        `ifdef UART_peripheral
                                                                                , uartReadOut, uartWriteOut
                                                                        `endif
 
                                                                        `ifdef SPI_peripheral
                                                                                , sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
                                                                        `endif
 
                                                                        , instField2
                                                                );
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 (accMuxSelOut, instField2[7:0], aluOut
                                                                                `ifdef timerAndCounter_peripheral
                                                                                , tcLoadOut, tcAccOut
                                                                                `endif
                                                                                `ifdef UART_peripheral
                                                                                , uartDataOut, {rxEmpty, txFull}
                                                                                `endif
                                                                                `ifdef SPI_peripheral
                                                                                , spiStatOut, spiBufOut
                                                                                `endif
                                                                                , accMuxOut
                                                                                );
 
 
        accumulator                     acc             (accMuxOut, accEnOut, accOut);
 
        op2Mux                          op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        wire [7:0] op2Out;
 
        byteNegator                     byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
 
        alu                                     arithLogicUnit  (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
 
        wire bitIn;
 
        bitNegator                      bitNegatorForBitRam     (accOut[0], instField2[9], bitIn);
 
        bitRam                          RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
 
        wire [7:0] byteIn;
 
        byteNegator                     byteNegatorForByteRam   (accOut, instField2[9], byteIn);
 
        byteRam                         RAM_Byte        (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
 
        inputRegister           inputStorage    (IN, instField2[6:0], inputReadOutData);
 
        outputReg                       outputStorage   (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
 
 
 
        tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
 
        tcAccum                         tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
 
        tcReset                         tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
 
        tcPreset                                tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
 
        tcLoad                          tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
 
        timer                                   timer0  (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
 
        timer                                   timer1  (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
 
        timer                                   timer2  (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
 
        timer                                   timer3  (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
 
        counter                         counter0        (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
 
        counter                         counter1        (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
 
        counter                         counter2        (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
 
        counter                         counter3        (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
        wire    brgOut;
        wire txDoneTick, txStart;
        wire rxDoneTick;
        wire [7:0] recFifoData, transFifoData;
 
 
        uartTrans       UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
 
        uartRec         UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
 
        uartBrg         UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
 
        uartFifo                UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
 
        uartFifo                UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
 
        spi_top         SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
 
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40
41	3	maheshpalv	`include "timescale.v"
42			`include "defines.v"
43
44			`module top(clk, reset, IN, OUT`
45
46			`ifdef UART_peripheral
47			`, rx, tx`
48			`endif
49
50			`ifdef SPI_peripheral
51			`, MISO, MOSI, SCK`
52			`endif
53
54			`);`
55
56
57			`input clk,reset;`
58			input [`inputNumber-1:0] IN;
59			output [`outputNumber-1:0] OUT;
60
61			`ifdef UART_peripheral
62			`input rx;`
63			`output tx;`
64			`endif
65
66			`ifdef SPI_peripheral
67			`input MISO;`
68			`output MOSI, SCK;`
69			`endif
70
71			`// wires (interconnects) of execution unit`
72
73	8	maheshpalv	wire [`instAddrLen-1:0] pcOut;
74	5	maheshpalv	wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
75	3	maheshpalv	wire [`instOpCodeLen-1:0] instOpCode;
76			wire [`instFieldLen-1:0] instField;
77
78			`wire [7:0] accMuxOut;`
79			`wire [7:0] accOut;`
80			`wire [7:0] op2MuxOut;`
81			`wire [7:0] aluOut;`
82
83			`wire bitNegatorRamOut, bitOut;`
84			`wire [7:0] byteNegatorRamOut, byteOut;`
85
86	5	maheshpalv	`wire inputReadOutData, outputReadOut;`
87	3	maheshpalv
88	5	maheshpalv	`wire branchOutc;`
89			wire [`accMuxSelLen-1:0] accMuxSelOutc;
90			`wire accEnOutc;`
91			wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
92	6	maheshpalv	`wire aluEnc;`
93	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
94			`wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;`
95			`wire inputReadOutc, outputRwOutc;`
96			`ifdef timerAndCounter_peripheral
97			`wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;`
98			`endif
99			`ifdef UART_peripheral
100			`wire uartReadOutc, uartWriteOutc;`
101	7	maheshpalv	`wire [7:0] uartDataOut;`
102			`wire rxEmpty, txFull;`
103	5	maheshpalv	`endif
104			`ifdef SPI_peripheral
105			`wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;`
106			`endif
107	3	maheshpalv
108	5	maheshpalv	`wire branchOut;`
109			wire [`accMuxSelLen-1:0] accMuxSelOut;
110			`wire accEnOut;`
111			wire [`op2MuxSelLen-1:0] op2MuxSelOut;
112	6	maheshpalv	`wire aluEn;`
113	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOut;
114			`wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
115			`wire inputReadOut, outputRwOut;`
116	3	maheshpalv	`ifdef timerAndCounter_peripheral
117	5	maheshpalv	`wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;`
118			`endif
119			`ifdef UART_peripheral
120			`wire uartReadOut, uartWriteOut;`
121			`endif
122			`ifdef SPI_peripheral
123			`wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;`
124			`endif
125
126	3	maheshpalv
127	5	maheshpalv
128			`// wires (interconnects) of timer & counter`
129
130			`ifdef timerAndCounter_peripheral
131
132			wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
133	7	maheshpalv	`wire [7:0] tcAccOut;`
134	5	maheshpalv	`wire [7:0] tcLoadOut;`
135			wire [`tcNumbers-1:0] enWires;
136			wire [`tcNumbers-1:0] resetWires;
137			wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
138			wire [(`tcNumbers*2)-1:0] typeWires;
139			wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
140
141			`endif
142
143	8	maheshpalv	`ifdef SPI_peripheral
144	5	maheshpalv
145	8	maheshpalv	`wire [7:0] spiStatOut, spiBufOut;`
146			`endif
147
148
149			`wire clk_d, clk_t;`
150			`reg [10:0] cnt = 0;`
151	5	maheshpalv
152	8	maheshpalv	`always @ (posedge clk or posedge reset)`
153			`begin`
154			`if (reset)`
155			`begin`
156			`cnt =0;`
157			`end`
158			`else`
159			`begin`
160			`cnt = cnt + 1'b1;`
161			`end`
162			`end`
163	5	maheshpalv
164	8	maheshpalv	`assign clk_d = cnt[0];`
165			`assign clk_t = cnt[10];`
166	3	maheshpalv
167
168
169			`//-------- Fetch Unit Module Instances`
170			`// all necessary`
171	9	maheshpalv
172			`wire branch = (~romOut[14] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[10]) \| ((romOut[10] & ~romOut[13] & ~romOut[12] & ~romOut[11] & ~romOut[14]) & accOut[0]); // END = 00000; JMP = 00001`
173	3	maheshpalv
174	9	maheshpalv	`pgmCounter ProgramCounter (clk_d, reset, branch, romOut[9:0], pcOut);`
175	3	maheshpalv
176
177			`// instruction ROM is declared using xilinx primitive`
178	9	maheshpalv	`// RAMB16_S18 rom ( .DI(),`
179			`// .DIP(),`
180			`// .ADDR(pcOut),`
181			`// .EN(1'b1),`
182			`// .WE(),`
183			`// .SSR(1'b0),`
184			`// .CLK(clk_d),`
185			`// .DO(romOut),`
186			`// .DOP());`
187	3	maheshpalv
188	9	maheshpalv	`rom CodeMem (clk_d, pcOut, romOut);`
189	3	maheshpalv
190	5	maheshpalv	`// pipeline register`
191
192			wire [`instOpCodeLen-1:0] instOpCode1;
193			wire [`instFieldLen-1:0] instField1;
194			wire [`instFieldLen-1:0] instField2;
195
196	8	maheshpalv	ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
197	5	maheshpalv
198
199			`//-------- Control Unit Module Instance`
200
201			`controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],`
202	6	maheshpalv	`branchOutc,`
203			`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
204			`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
205			`ifdef timerAndCounter_peripheral
206			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
207			`endif
208			`ifdef UART_peripheral
209			`, uartReadOutc, uartWriteOutcc`
210			`endif
211			`ifdef SPI_peripheral
212			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
213			`endif
214	5	maheshpalv
215			`);`
216
217
218
219			`// pipeline register`
220
221
222
223			`ppReg2 PipeLine_Reg2 (clk,`
224			`branchOutc,`
225	6	maheshpalv	`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
226	5	maheshpalv	`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
227			`ifdef timerAndCounter_peripheral
228			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
229			`endif
230			`ifdef UART_peripheral
231			`, uartReadOutc, uartWriteOutcc`
232			`endif
233			`ifdef SPI_peripheral
234			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
235			`endif
236			`, instField1`
237
238			`, branchOut,`
239	6	maheshpalv	`accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,`
240	5	maheshpalv	`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
241			`inputReadOut, outputRwOut`
242
243			`ifdef timerAndCounter_peripheral
244			`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut`
245			`endif
246
247			`ifdef UART_peripheral
248			`, uartReadOut, uartWriteOut`
249			`endif
250
251			`ifdef SPI_peripheral
252			`, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut`
253			`endif
254
255			`, instField2`
256			`);`
257
258
259	3	maheshpalv	`//-------- Execute Unit Modules Instances`
260			`// all necessary`
261
262
263
264
265	5	maheshpalv	`accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut`
266			`ifdef timerAndCounter_peripheral
267			`, tcLoadOut, tcAccOut`
268			`endif
269			`ifdef UART_peripheral
270	7	maheshpalv	`, uartDataOut, {rxEmpty, txFull}`
271	5	maheshpalv	`endif
272			`ifdef SPI_peripheral
273			`, spiStatOut, spiBufOut`
274			`endif
275			`, accMuxOut`
276			`);`
277
278	3	maheshpalv
279	5	maheshpalv	`accumulator acc (accMuxOut, accEnOut, accOut);`
280	3	maheshpalv
281	5	maheshpalv	`op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);`
282	3	maheshpalv
283	5	maheshpalv	`wire [7:0] op2Out;`
284	3	maheshpalv
285	5	maheshpalv	`byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);`
286	3	maheshpalv
287	6	maheshpalv	`alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);`
288	3	maheshpalv
289	5	maheshpalv	`wire bitIn;`
290	3	maheshpalv
291	5	maheshpalv	`bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);`
292	3	maheshpalv
293	5	maheshpalv	`bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);`
294	3	maheshpalv
295	5	maheshpalv	`wire [7:0] byteIn;`
296	3	maheshpalv
297	5	maheshpalv	`byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);`
298	3	maheshpalv
299	5	maheshpalv	`byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);`
300
301	9	maheshpalv	`inputRegister inputStorage (IN, instField2[6:0], inputReadOutData);`
302	5	maheshpalv
303			`outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);`
304
305	3	maheshpalv
306			`//---------- Timer & Counter Modules`
307			`// optional`
308
309			`ifdef timerAndCounter_peripheral
310
311	5	maheshpalv
312
313
314			`tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);`
315	3	maheshpalv
316	7	maheshpalv	`tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);`
317	3	maheshpalv
318	5	maheshpalv	`tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);`
319	3	maheshpalv
320	5	maheshpalv	`tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);`
321	3	maheshpalv
322	5	maheshpalv	`tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);`
323	3	maheshpalv
324	8	maheshpalv	`timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);`
325	3	maheshpalv
326	8	maheshpalv	`timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);`
327	3	maheshpalv
328	8	maheshpalv	`timer timer2 (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);`
329	3	maheshpalv
330	8	maheshpalv	`timer timer3 (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);`
331	3	maheshpalv
332	5	maheshpalv	`counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);`
333	3	maheshpalv
334	5	maheshpalv	`counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);`
335	3	maheshpalv
336	5	maheshpalv	`counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);`
337	3	maheshpalv
338	5	maheshpalv	`counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);`
339	3	maheshpalv
340			`endif
341
342			`//---------- UART Modules`
343			`// optional`
344
345			`ifdef UART_peripheral
346
347	5	maheshpalv	`wire brgOut;`
348			`wire txDoneTick, txStart;`
349			`wire rxDoneTick;`
350			`wire [7:0] recFifoData, transFifoData;`
351
352	3	maheshpalv
353	5	maheshpalv	`uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);`
354	3	maheshpalv
355	5	maheshpalv	`uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);`
356	3	maheshpalv
357	5	maheshpalv	`uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));`
358	3	maheshpalv
359	5	maheshpalv	`uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);`
360	3	maheshpalv
361	5	maheshpalv	`uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);`
362
363	3	maheshpalv	`endif
364
365			`//---------- SPI Modules`
366			`// optional`
367
368			`ifdef SPI_peripheral
369
370	6	maheshpalv
371			`spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);`
372
373
374	3	maheshpalv	`endif
375
376			`endmodule`

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