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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [top.v] - Blame information for rev 3

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`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                `ifdef SPI_peripheral
                                        , MISO, MOSI, SCK
                                `endif
 
                                );
 
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
        `ifdef SPI_peripheral
        input MISO;
        output MOSI, SCK;
        `endif
 
// wires (interconnects) of execution unit
 
        wire    [`instLen-1:0]                   pcOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOut, outputReadOut;
 
// wires (interconnects) of timer & counter
 
        `ifdef timerAndCounter_peripheral
 
        `endif
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        pgmCounter              ProgramCounter ();
 
        instReg                 IntructionRegister ();
 
 
// instruction ROM is declared using xilinx primitive
        RAMB16_S18 rom ( .DI(),
                                 .DIP(),
                                 .ADDR(),
                                 .EN(1'b1),
                                 .WE(),
                                 .SSR(1'b0),
                                 .CLK(),
                                 .DO(),
                                 .DOP());
 
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 ();
 
        accumulator                     acc             ();
 
        byteNegator                     byteNegatorForOp2Mux ();
 
        op2Mux                          op2MUX1 ();
 
        alu                                     arithLogicUnit  ();
 
        bitNegator                      bitNegatorForBitRam     ();
 
        bitRam                          RAM_Bit ();
 
        byteNegator                     byteNegatorForByteRam   ();
 
        byteRam                         RAM_Byte        ();
 
        inputRegister           inputStorage    ();
 
        outputReg                       outputStorage   ();
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
        tcEnableAndType tcEnableAndTypeModule();
 
        tcAccum                         tcAccumModule();
 
        tcReset                         tcResetModule();
 
        tcPreset                                tcPresetModule();
 
        tcLoad                          tcLoadModule();
 
        timer                                   timer0();
 
        timer                                   timer1();
 
        timer                                   timer2();
 
        timer                                   timer3();
 
        counter                         counter0();
 
        counter                         counter1();
 
        counter                         counter2();
 
        counter                         counter3();
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
 
        uartTrans       UART_TRANSMITTER ();
 
        uartRec         UART_RECIEVER ();
 
        uartBrg         UART_BitRateGenerator ();
 
        uartFifo                UART_TRANS_FIFO ();
 
        uartFifo                UART_REC_FIFO ();
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
        spiStatReg      SPI_STATUS_REG ();
 
        spiConReg       SPI_CONTROL_REG ();
 
        spiBufReg       SPI_BUFFER_REG ();
 
        spiEngine       SPI_MAIN        ();
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv	`include "timescale.v"
2			`include "defines.v"
3
4			`module top(clk, reset, IN, OUT`
5
6			`ifdef UART_peripheral
7			`, rx, tx`
8			`endif
9
10			`ifdef SPI_peripheral
11			`, MISO, MOSI, SCK`
12			`endif
13
14			`);`
15
16
17
18			`input clk,reset;`
19			input [`inputNumber-1:0] IN;
20			output [`outputNumber-1:0] OUT;
21
22			`ifdef UART_peripheral
23			`input rx;`
24			`output tx;`
25			`endif
26
27			`ifdef SPI_peripheral
28			`input MISO;`
29			`output MOSI, SCK;`
30			`endif
31
32			`// wires (interconnects) of execution unit`
33
34			wire [`instLen-1:0] pcOut;
35			wire [`instOpCodeLen-1:0] instOpCode;
36			wire [`instFieldLen-1:0] instField;
37
38			`wire [7:0] accMuxOut;`
39			`wire [7:0] accOut;`
40			`wire [7:0] op2MuxOut;`
41			`wire [7:0] aluOut;`
42
43			`wire bitNegatorRamOut, bitOut;`
44			`wire [7:0] byteNegatorRamOut, byteOut;`
45
46			`wire inputReadOut, outputReadOut;`
47
48			`// wires (interconnects) of timer & counter`
49
50			`ifdef timerAndCounter_peripheral
51
52			`endif
53
54
55
56			`//-------- Fetch Unit Module Instances`
57			`// all necessary`
58
59			`pgmCounter ProgramCounter ();`
60
61			`instReg IntructionRegister ();`
62
63
64			`// instruction ROM is declared using xilinx primitive`
65			`RAMB16_S18 rom ( .DI(),`
66			`.DIP(),`
67			`.ADDR(),`
68			`.EN(1'b1),`
69			`.WE(),`
70			`.SSR(1'b0),`
71			`.CLK(),`
72			`.DO(),`
73			`.DOP());`
74
75
76
77			`//-------- Execute Unit Modules Instances`
78			`// all necessary`
79
80
81
82
83			`accumulatorMUX accMUX1 ();`
84
85			`accumulator acc ();`
86
87			`byteNegator byteNegatorForOp2Mux ();`
88
89			`op2Mux op2MUX1 ();`
90
91			`alu arithLogicUnit ();`
92
93			`bitNegator bitNegatorForBitRam ();`
94
95			`bitRam RAM_Bit ();`
96
97			`byteNegator byteNegatorForByteRam ();`
98
99			`byteRam RAM_Byte ();`
100
101			`inputRegister inputStorage ();`
102
103			`outputReg outputStorage ();`
104
105
106			`//---------- Timer & Counter Modules`
107			`// optional`
108
109			`ifdef timerAndCounter_peripheral
110
111			`tcEnableAndType tcEnableAndTypeModule();`
112
113			`tcAccum tcAccumModule();`
114
115			`tcReset tcResetModule();`
116
117			`tcPreset tcPresetModule();`
118
119			`tcLoad tcLoadModule();`
120
121			`timer timer0();`
122
123			`timer timer1();`
124
125			`timer timer2();`
126
127			`timer timer3();`
128
129			`counter counter0();`
130
131			`counter counter1();`
132
133			`counter counter2();`
134
135			`counter counter3();`
136
137			`endif
138
139			`//---------- UART Modules`
140			`// optional`
141
142			`ifdef UART_peripheral
143
144
145			`uartTrans UART_TRANSMITTER ();`
146
147			`uartRec UART_RECIEVER ();`
148
149			`uartBrg UART_BitRateGenerator ();`
150
151			`uartFifo UART_TRANS_FIFO ();`
152
153			`uartFifo UART_REC_FIFO ();`
154
155			`endif
156
157			`//---------- SPI Modules`
158			`// optional`
159
160			`ifdef SPI_peripheral
161
162			`spiStatReg SPI_STATUS_REG ();`
163
164			`spiConReg SPI_CONTROL_REG ();`
165
166			`spiBufReg SPI_BUFFER_REG ();`
167
168			`spiEngine SPI_MAIN ();`
169
170			`endif
171
172			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [top.v] - Blame information for rev 3