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`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                `ifdef SPI_peripheral
                                        , MISO, MOSI, SCK
                                `endif
 
                                );
 
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
        `ifdef SPI_peripheral
        input MISO;
        output MOSI, SCK;
        `endif
 
// wires (interconnects) of execution unit
 
        wire    [`instLen-1:0]                   pcOut;
        wire    [`instOpCodeLen+`instFieldLen-1:0] romOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOutData, outputReadOut;
 
        wire branchOutc;
        wire [`accMuxSelLen-1:0] accMuxSelOutc;
        wire accEnOutc;
        wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
        wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
        wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
        wire inputReadOutc, outputRwOutc;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
        `endif
        `ifdef UART_peripheral
        wire uartReadOutc, uartWriteOutc;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
        `endif
 
        wire branchOut;
        wire [`accMuxSelLen-1:0] accMuxSelOut;
        wire accEnOut;
        wire [`op2MuxSelLen-1:0] op2MuxSelOut;
        wire [`aluOpcodeLen-1:0] aluOpcodeOut;
        wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        wire inputReadOut, outputRwOut;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
        `endif
        `ifdef UART_peripheral
        wire uartReadOut, uartWriteOut;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
        `endif
 
 
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
        wire    [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
        wire    [7:0] tcAccumOut;
        wire    [7:0] tcLoadOut;
        wire [`tcNumbers-1:0] enWires;
        wire [`tcNumbers-1:0] resetWires;
        wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
        wire [(`tcNumbers*2)-1:0] typeWires;
        wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
// wires (interconnects) of UART
 
        `ifdef UART_peripheral
 
 
 
        `endif
 
// wires (interconnects) of SPI
 
        `ifdef SPI_peripheral
 
        `endif
 
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        pgmCounter              ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
 
 
// instruction ROM is declared using xilinx primitive
        RAMB16_S18 rom ( .DI(),
                                 .DIP(),
                                 .ADDR(pcOut),
                                 .EN(1'b1),
                                 .WE(),
                                 .SSR(1'b0),
                                 .CLK(clk),
                                 .DO(romOut),
                                 .DOP());
 
        instReg                 IntructionRegister (romOut, instOpCode, instField);
 
 
// pipeline register
 
        wire    [`instOpCodeLen-1:0] instOpCode1;
        wire    [`instFieldLen-1:0] instField1;
        wire    [`instFieldLen-1:0] instField2;
 
        ppReg1  PipeLine_Reg1 (clk, instOpcode, instField, instOpcode1, instField1);
 
 
//-------- Control Unit Module Instance
 
        controlUnit             CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
                                                                                        branchc,
                                                                                        accMuxSelc, accEnc, op2MuxSelc, aluOpcodec,
                                                                                        bitRamEnc, bitRamRwc, byteRamEnc, byteRamRwc,
                                                                                        inputReadc, outputRwc
 
                                                                                        `ifdef timerAndCounter_peripheral
                                                                                                , entypeEnc, tcAccReadc, tcResetEnc, tcPresetEnc, tcLoadEnc
                                                                                        `endif
 
                                                                                        `ifdef UART_peripheral
                                                                                                , uartReadc, uartWritec
                                                                                        `endif
 
                                                                                        `ifdef SPI_peripheral
                                                                                                , sconEnc, spiStatReadc, spiBufReadc, spiBufWritec, spiBufShiftc
                                                                                        `endif
 
                                                                                        );
 
 
 
// pipeline register
 
 
 
        ppReg2  PipeLine_Reg2 (clk,
                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
                                                                , instField1
 
                                                                        , branchOut,
                                                                        accMuxSelOut, accEnOut, op2MuxSelOut, aluOpcodeOut,
                                                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                                                        inputReadOut, outputRwOut
 
                                                                        `ifdef timerAndCounter_peripheral
                                                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
                                                                        `endif
 
                                                                        `ifdef UART_peripheral
                                                                                , uartReadOut, uartWriteOut
                                                                        `endif
 
                                                                        `ifdef SPI_peripheral
                                                                                , sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
                                                                        `endif
 
                                                                        , instField2
                                                                );
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 (accMuxSelOut, instField2[7:0], aluOut
                                                                                `ifdef timerAndCounter_peripheral
                                                                                , tcLoadOut, tcAccOut
                                                                                `endif
                                                                                `ifdef UART_peripheral
                                                                                , uartDataOut
                                                                                `endif
                                                                                `ifdef SPI_peripheral
                                                                                , spiStatOut, spiBufOut
                                                                                `endif
                                                                                , accMuxOut
                                                                                );
 
 
        accumulator                     acc             (accMuxOut, accEnOut, accOut);
 
        op2Mux                          op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        wire [7:0] op2Out;
 
        byteNegator                     byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
 
        alu                                     arithLogicUnit  (aluOpcodeOut, accOut, op2Out, aluOut, carryOut);
 
        wire bitIn;
 
        bitNegator                      bitNegatorForBitRam     (accOut[0], instField2[9], bitIn);
 
        bitRam                          RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
 
        wire [7:0] byteIn;
 
        byteNegator                     byteNegatorForByteRam   (accOut, instField2[9], byteIn);
 
        byteRam                         RAM_Byte        (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
 
        inputRegister           inputStorage    (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
 
        outputReg                       outputStorage   (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
 
 
 
        tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
 
        tcAccum                         tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
 
        tcReset                         tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
 
        tcPreset                                tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
 
        tcLoad                          tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
 
        timer                                   timer0  (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
 
        timer                                   timer1  (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
 
        timer                                   timer2  (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
 
        timer                                   timer3  (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
 
        counter                         counter0        (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
 
        counter                         counter1        (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
 
        counter                         counter2        (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
 
        counter                         counter3        (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
        wire    brgOut;
        wire txDoneTick, txStart;
        wire rxDoneTick;
        wire [7:0] recFifoData, transFifoData;
 
 
        uartTrans       UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
 
        uartRec         UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
 
        uartBrg         UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
 
        uartFifo                UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
 
        uartFifo                UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
        spiStatReg      SPI_STATUS_REG ();
 
        spiConReg       SPI_CONTROL_REG ();
 
        spiBufReg       SPI_BUFFER_REG ();
 
        spiEngine       SPI_MAIN        ();
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv	`include "timescale.v"
2			`include "defines.v"
3
4			`module top(clk, reset, IN, OUT`
5
6			`ifdef UART_peripheral
7			`, rx, tx`
8			`endif
9
10			`ifdef SPI_peripheral
11			`, MISO, MOSI, SCK`
12			`endif
13
14			`);`
15
16
17
18			`input clk,reset;`
19			input [`inputNumber-1:0] IN;
20			output [`outputNumber-1:0] OUT;
21
22			`ifdef UART_peripheral
23			`input rx;`
24			`output tx;`
25			`endif
26
27			`ifdef SPI_peripheral
28			`input MISO;`
29			`output MOSI, SCK;`
30			`endif
31
32			`// wires (interconnects) of execution unit`
33
34			wire [`instLen-1:0] pcOut;
35	5	maheshpalv	wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
36	3	maheshpalv	wire [`instOpCodeLen-1:0] instOpCode;
37			wire [`instFieldLen-1:0] instField;
38
39			`wire [7:0] accMuxOut;`
40			`wire [7:0] accOut;`
41			`wire [7:0] op2MuxOut;`
42			`wire [7:0] aluOut;`
43
44			`wire bitNegatorRamOut, bitOut;`
45			`wire [7:0] byteNegatorRamOut, byteOut;`
46
47	5	maheshpalv	`wire inputReadOutData, outputReadOut;`
48	3	maheshpalv
49	5	maheshpalv	`wire branchOutc;`
50			wire [`accMuxSelLen-1:0] accMuxSelOutc;
51			`wire accEnOutc;`
52			wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
53			wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
54			`wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;`
55			`wire inputReadOutc, outputRwOutc;`
56			`ifdef timerAndCounter_peripheral
57			`wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;`
58			`endif
59			`ifdef UART_peripheral
60			`wire uartReadOutc, uartWriteOutc;`
61			`endif
62			`ifdef SPI_peripheral
63			`wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;`
64			`endif
65	3	maheshpalv
66	5	maheshpalv	`wire branchOut;`
67			wire [`accMuxSelLen-1:0] accMuxSelOut;
68			`wire accEnOut;`
69			wire [`op2MuxSelLen-1:0] op2MuxSelOut;
70			wire [`aluOpcodeLen-1:0] aluOpcodeOut;
71			`wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
72			`wire inputReadOut, outputRwOut;`
73	3	maheshpalv	`ifdef timerAndCounter_peripheral
74	5	maheshpalv	`wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;`
75			`endif
76			`ifdef UART_peripheral
77			`wire uartReadOut, uartWriteOut;`
78			`endif
79			`ifdef SPI_peripheral
80			`wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;`
81			`endif
82
83	3	maheshpalv
84	5	maheshpalv
85			`// wires (interconnects) of timer & counter`
86
87			`ifdef timerAndCounter_peripheral
88
89			wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
90			`wire [7:0] tcAccumOut;`
91			`wire [7:0] tcLoadOut;`
92			wire [`tcNumbers-1:0] enWires;
93			wire [`tcNumbers-1:0] resetWires;
94			wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
95			wire [(`tcNumbers*2)-1:0] typeWires;
96			wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
97
98			`endif
99
100			`// wires (interconnects) of UART`
101
102			`ifdef UART_peripheral
103
104
105
106	3	maheshpalv	`endif
107	5	maheshpalv
108			`// wires (interconnects) of SPI`
109	3	maheshpalv
110	5	maheshpalv	`ifdef SPI_peripheral
111	3	maheshpalv
112	5	maheshpalv	`endif
113	3	maheshpalv
114	5	maheshpalv
115
116
117	3	maheshpalv	`//-------- Fetch Unit Module Instances`
118			`// all necessary`
119
120	5	maheshpalv	`pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);`
121	3	maheshpalv
122
123			`// instruction ROM is declared using xilinx primitive`
124			`RAMB16_S18 rom ( .DI(),`
125			`.DIP(),`
126	5	maheshpalv	`.ADDR(pcOut),`
127	3	maheshpalv	`.EN(1'b1),`
128			`.WE(),`
129			`.SSR(1'b0),`
130	5	maheshpalv	`.CLK(clk),`
131			`.DO(romOut),`
132	3	maheshpalv	`.DOP());`
133
134	5	maheshpalv	`instReg IntructionRegister (romOut, instOpCode, instField);`
135	3	maheshpalv
136
137	5	maheshpalv	`// pipeline register`
138
139			wire [`instOpCodeLen-1:0] instOpCode1;
140			wire [`instFieldLen-1:0] instField1;
141			wire [`instFieldLen-1:0] instField2;
142
143			`ppReg1 PipeLine_Reg1 (clk, instOpcode, instField, instOpcode1, instField1);`
144
145
146			`//-------- Control Unit Module Instance`
147
148			`controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],`
149			`branchc,`
150			`accMuxSelc, accEnc, op2MuxSelc, aluOpcodec,`
151			`bitRamEnc, bitRamRwc, byteRamEnc, byteRamRwc,`
152			`inputReadc, outputRwc`
153
154			`ifdef timerAndCounter_peripheral
155			`, entypeEnc, tcAccReadc, tcResetEnc, tcPresetEnc, tcLoadEnc`
156			`endif
157
158			`ifdef UART_peripheral
159			`, uartReadc, uartWritec`
160			`endif
161
162			`ifdef SPI_peripheral
163			`, sconEnc, spiStatReadc, spiBufReadc, spiBufWritec, spiBufShiftc`
164			`endif
165
166			`);`
167
168
169
170			`// pipeline register`
171
172
173
174			`ppReg2 PipeLine_Reg2 (clk,`
175			`branchOutc,`
176			`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluOpcodeOutc, bitRamEnOutc,`
177			`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
178			`ifdef timerAndCounter_peripheral
179			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
180			`endif
181			`ifdef UART_peripheral
182			`, uartReadOutc, uartWriteOutcc`
183			`endif
184			`ifdef SPI_peripheral
185			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
186			`endif
187			`, instField1`
188
189			`, branchOut,`
190			`accMuxSelOut, accEnOut, op2MuxSelOut, aluOpcodeOut,`
191			`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
192			`inputReadOut, outputRwOut`
193
194			`ifdef timerAndCounter_peripheral
195			`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut`
196			`endif
197
198			`ifdef UART_peripheral
199			`, uartReadOut, uartWriteOut`
200			`endif
201
202			`ifdef SPI_peripheral
203			`, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut`
204			`endif
205
206			`, instField2`
207			`);`
208
209
210	3	maheshpalv	`//-------- Execute Unit Modules Instances`
211			`// all necessary`
212
213
214
215
216	5	maheshpalv	`accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut`
217			`ifdef timerAndCounter_peripheral
218			`, tcLoadOut, tcAccOut`
219			`endif
220			`ifdef UART_peripheral
221			`, uartDataOut`
222			`endif
223			`ifdef SPI_peripheral
224			`, spiStatOut, spiBufOut`
225			`endif
226			`, accMuxOut`
227			`);`
228
229	3	maheshpalv
230	5	maheshpalv	`accumulator acc (accMuxOut, accEnOut, accOut);`
231	3	maheshpalv
232	5	maheshpalv	`op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);`
233	3	maheshpalv
234	5	maheshpalv	`wire [7:0] op2Out;`
235	3	maheshpalv
236	5	maheshpalv	`byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);`
237	3	maheshpalv
238	5	maheshpalv	`alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluOut, carryOut);`
239	3	maheshpalv
240	5	maheshpalv	`wire bitIn;`
241	3	maheshpalv
242	5	maheshpalv	`bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);`
243	3	maheshpalv
244	5	maheshpalv	`bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);`
245	3	maheshpalv
246	5	maheshpalv	`wire [7:0] byteIn;`
247	3	maheshpalv
248	5	maheshpalv	`byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);`
249	3	maheshpalv
250	5	maheshpalv	`byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);`
251
252			`inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);`
253
254			`outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);`
255
256	3	maheshpalv
257			`//---------- Timer & Counter Modules`
258			`// optional`
259
260			`ifdef timerAndCounter_peripheral
261
262	5	maheshpalv
263
264
265			`tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);`
266	3	maheshpalv
267	5	maheshpalv	`tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);`
268	3	maheshpalv
269	5	maheshpalv	`tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);`
270	3	maheshpalv
271	5	maheshpalv	`tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);`
272	3	maheshpalv
273	5	maheshpalv	`tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);`
274	3	maheshpalv
275	5	maheshpalv	`timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);`
276	3	maheshpalv
277	5	maheshpalv	`timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);`
278	3	maheshpalv
279	5	maheshpalv	`timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);`
280	3	maheshpalv
281	5	maheshpalv	`timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);`
282	3	maheshpalv
283	5	maheshpalv	`counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);`
284	3	maheshpalv
285	5	maheshpalv	`counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);`
286	3	maheshpalv
287	5	maheshpalv	`counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);`
288	3	maheshpalv
289	5	maheshpalv	`counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);`
290	3	maheshpalv
291			`endif
292
293			`//---------- UART Modules`
294			`// optional`
295
296			`ifdef UART_peripheral
297
298	5	maheshpalv	`wire brgOut;`
299			`wire txDoneTick, txStart;`
300			`wire rxDoneTick;`
301			`wire [7:0] recFifoData, transFifoData;`
302
303	3	maheshpalv
304	5	maheshpalv	`uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);`
305	3	maheshpalv
306	5	maheshpalv	`uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);`
307	3	maheshpalv
308	5	maheshpalv	`uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));`
309	3	maheshpalv
310	5	maheshpalv	`uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);`
311	3	maheshpalv
312	5	maheshpalv	`uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);`
313
314	3	maheshpalv	`endif
315
316			`//---------- SPI Modules`
317			`// optional`
318
319			`ifdef SPI_peripheral
320
321			`spiStatReg SPI_STATUS_REG ();`
322
323			`spiConReg SPI_CONTROL_REG ();`
324
325			`spiBufReg SPI_BUFFER_REG ();`
326
327			`spiEngine SPI_MAIN ();`
328
329			`endif
330
331			`endmodule`

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