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`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                `ifdef SPI_peripheral
                                        , MISO, MOSI, SCK
                                `endif
 
                                );
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
        `ifdef SPI_peripheral
        input MISO;
        output MOSI, SCK;
        `endif
 
// wires (interconnects) of execution unit
 
        wire    [`instLen-1:0]                   pcOut;
        wire    [`instOpCodeLen+`instFieldLen-1:0] romOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOutData, outputReadOut;
 
        wire branchOutc;
        wire [`accMuxSelLen-1:0] accMuxSelOutc;
        wire accEnOutc;
        wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
        wire aluEnc;
        wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
        wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
        wire inputReadOutc, outputRwOutc;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
        `endif
        `ifdef UART_peripheral
        wire uartReadOutc, uartWriteOutc;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
        `endif
 
        wire branchOut;
        wire [`accMuxSelLen-1:0] accMuxSelOut;
        wire accEnOut;
        wire [`op2MuxSelLen-1:0] op2MuxSelOut;
        wire aluEn;
        wire [`aluOpcodeLen-1:0] aluOpcodeOut;
        wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        wire inputReadOut, outputRwOut;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
        `endif
        `ifdef UART_peripheral
        wire uartReadOut, uartWriteOut;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
        `endif
 
 
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
        wire    [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
        wire    [7:0] tcAccumOut;
        wire    [7:0] tcLoadOut;
        wire [`tcNumbers-1:0] enWires;
        wire [`tcNumbers-1:0] resetWires;
        wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
        wire [(`tcNumbers*2)-1:0] typeWires;
        wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
// wires (interconnects) of UART
 
        `ifdef UART_peripheral
 
 
 
        `endif
 
// wires (interconnects) of SPI
 
        `ifdef SPI_peripheral
 
        `endif
 
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        pgmCounter              ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);
 
 
// instruction ROM is declared using xilinx primitive
        RAMB16_S18 rom ( .DI(),
                                 .DIP(),
                                 .ADDR(pcOut),
                                 .EN(1'b1),
                                 .WE(),
                                 .SSR(1'b0),
                                 .CLK(clk),
                                 .DO(romOut),
                                 .DOP());
 
        instReg                 IntructionRegister (romOut, instOpCode, instField);
 
 
// pipeline register
 
        wire    [`instOpCodeLen-1:0] instOpCode1;
        wire    [`instFieldLen-1:0] instField1;
        wire    [`instFieldLen-1:0] instField2;
 
        ppReg1  PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
 
        controlUnit             CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
                                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
 
                                                                                        );
 
 
 
// pipeline register
 
 
 
        ppReg2  PipeLine_Reg2 (clk,
                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
                                                                , instField1
 
                                                                        , branchOut,
                                                                        accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
                                                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                                                        inputReadOut, outputRwOut
 
                                                                        `ifdef timerAndCounter_peripheral
                                                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
                                                                        `endif
 
                                                                        `ifdef UART_peripheral
                                                                                , uartReadOut, uartWriteOut
                                                                        `endif
 
                                                                        `ifdef SPI_peripheral
                                                                                , sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
                                                                        `endif
 
                                                                        , instField2
                                                                );
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 (accMuxSelOut, instField2[7:0], aluOut
                                                                                `ifdef timerAndCounter_peripheral
                                                                                , tcLoadOut, tcAccOut
                                                                                `endif
                                                                                `ifdef UART_peripheral
                                                                                , uartDataOut
                                                                                `endif
                                                                                `ifdef SPI_peripheral
                                                                                , spiStatOut, spiBufOut
                                                                                `endif
                                                                                , accMuxOut
                                                                                );
 
 
        accumulator                     acc             (accMuxOut, accEnOut, accOut);
 
        op2Mux                          op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        wire [7:0] op2Out;
 
        byteNegator                     byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
 
        alu                                     arithLogicUnit  (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
 
        wire bitIn;
 
        bitNegator                      bitNegatorForBitRam     (accOut[0], instField2[9], bitIn);
 
        bitRam                          RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
 
        wire [7:0] byteIn;
 
        byteNegator                     byteNegatorForByteRam   (accOut, instField2[9], byteIn);
 
        byteRam                         RAM_Byte        (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
 
        inputRegister           inputStorage    (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
 
        outputReg                       outputStorage   (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
 
 
 
        tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
 
        tcAccum                         tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);
 
        tcReset                         tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
 
        tcPreset                                tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
 
        tcLoad                          tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
 
        timer                                   timer0  (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
 
        timer                                   timer1  (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
 
        timer                                   timer2  (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
 
        timer                                   timer3  (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
 
        counter                         counter0        (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
 
        counter                         counter1        (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
 
        counter                         counter2        (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
 
        counter                         counter3        (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
        wire    brgOut;
        wire txDoneTick, txStart;
        wire rxDoneTick;
        wire [7:0] recFifoData, transFifoData;
 
 
        uartTrans       UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
 
        uartRec         UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
 
        uartBrg         UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
 
        uartFifo                UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
 
        uartFifo                UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
 
        spi_top         SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
 
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv	`include "timescale.v"
2			`include "defines.v"
3
4			`module top(clk, reset, IN, OUT`
5
6			`ifdef UART_peripheral
7			`, rx, tx`
8			`endif
9
10			`ifdef SPI_peripheral
11			`, MISO, MOSI, SCK`
12			`endif
13
14			`);`
15
16
17			`input clk,reset;`
18			input [`inputNumber-1:0] IN;
19			output [`outputNumber-1:0] OUT;
20
21			`ifdef UART_peripheral
22			`input rx;`
23			`output tx;`
24			`endif
25
26			`ifdef SPI_peripheral
27			`input MISO;`
28			`output MOSI, SCK;`
29			`endif
30
31			`// wires (interconnects) of execution unit`
32
33			wire [`instLen-1:0] pcOut;
34	5	maheshpalv	wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
35	3	maheshpalv	wire [`instOpCodeLen-1:0] instOpCode;
36			wire [`instFieldLen-1:0] instField;
37
38			`wire [7:0] accMuxOut;`
39			`wire [7:0] accOut;`
40			`wire [7:0] op2MuxOut;`
41			`wire [7:0] aluOut;`
42
43			`wire bitNegatorRamOut, bitOut;`
44			`wire [7:0] byteNegatorRamOut, byteOut;`
45
46	5	maheshpalv	`wire inputReadOutData, outputReadOut;`
47	3	maheshpalv
48	5	maheshpalv	`wire branchOutc;`
49			wire [`accMuxSelLen-1:0] accMuxSelOutc;
50			`wire accEnOutc;`
51			wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
52	6	maheshpalv	`wire aluEnc;`
53	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
54			`wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;`
55			`wire inputReadOutc, outputRwOutc;`
56			`ifdef timerAndCounter_peripheral
57			`wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;`
58			`endif
59			`ifdef UART_peripheral
60			`wire uartReadOutc, uartWriteOutc;`
61			`endif
62			`ifdef SPI_peripheral
63			`wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;`
64			`endif
65	3	maheshpalv
66	5	maheshpalv	`wire branchOut;`
67			wire [`accMuxSelLen-1:0] accMuxSelOut;
68			`wire accEnOut;`
69			wire [`op2MuxSelLen-1:0] op2MuxSelOut;
70	6	maheshpalv	`wire aluEn;`
71	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOut;
72			`wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
73			`wire inputReadOut, outputRwOut;`
74	3	maheshpalv	`ifdef timerAndCounter_peripheral
75	5	maheshpalv	`wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;`
76			`endif
77			`ifdef UART_peripheral
78			`wire uartReadOut, uartWriteOut;`
79			`endif
80			`ifdef SPI_peripheral
81			`wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;`
82			`endif
83
84	3	maheshpalv
85	5	maheshpalv
86			`// wires (interconnects) of timer & counter`
87
88			`ifdef timerAndCounter_peripheral
89
90			wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
91			`wire [7:0] tcAccumOut;`
92			`wire [7:0] tcLoadOut;`
93			wire [`tcNumbers-1:0] enWires;
94			wire [`tcNumbers-1:0] resetWires;
95			wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
96			wire [(`tcNumbers*2)-1:0] typeWires;
97			wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
98
99			`endif
100
101			`// wires (interconnects) of UART`
102
103			`ifdef UART_peripheral
104
105
106
107	3	maheshpalv	`endif
108	5	maheshpalv
109			`// wires (interconnects) of SPI`
110	3	maheshpalv
111	5	maheshpalv	`ifdef SPI_peripheral
112	3	maheshpalv
113	5	maheshpalv	`endif
114	3	maheshpalv
115	5	maheshpalv
116
117
118	3	maheshpalv	`//-------- Fetch Unit Module Instances`
119			`// all necessary`
120
121	5	maheshpalv	`pgmCounter ProgramCounter (clk, reset, branchOutc, instField[7:0], pcOut);`
122	3	maheshpalv
123
124			`// instruction ROM is declared using xilinx primitive`
125			`RAMB16_S18 rom ( .DI(),`
126			`.DIP(),`
127	5	maheshpalv	`.ADDR(pcOut),`
128	3	maheshpalv	`.EN(1'b1),`
129			`.WE(),`
130			`.SSR(1'b0),`
131	5	maheshpalv	`.CLK(clk),`
132			`.DO(romOut),`
133	3	maheshpalv	`.DOP());`
134
135	5	maheshpalv	`instReg IntructionRegister (romOut, instOpCode, instField);`
136	3	maheshpalv
137
138	5	maheshpalv	`// pipeline register`
139
140			wire [`instOpCodeLen-1:0] instOpCode1;
141			wire [`instFieldLen-1:0] instField1;
142			wire [`instFieldLen-1:0] instField2;
143
144	6	maheshpalv	`ppReg1 PipeLine_Reg1 (clk, instOpCode, instField, instOpCode1, instField1);`
145	5	maheshpalv
146
147			`//-------- Control Unit Module Instance`
148
149			`controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],`
150	6	maheshpalv	`branchOutc,`
151			`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
152			`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
153			`ifdef timerAndCounter_peripheral
154			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
155			`endif
156			`ifdef UART_peripheral
157			`, uartReadOutc, uartWriteOutcc`
158			`endif
159			`ifdef SPI_peripheral
160			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
161			`endif
162	5	maheshpalv
163			`);`
164
165
166
167			`// pipeline register`
168
169
170
171			`ppReg2 PipeLine_Reg2 (clk,`
172			`branchOutc,`
173	6	maheshpalv	`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
174	5	maheshpalv	`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
175			`ifdef timerAndCounter_peripheral
176			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
177			`endif
178			`ifdef UART_peripheral
179			`, uartReadOutc, uartWriteOutcc`
180			`endif
181			`ifdef SPI_peripheral
182			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
183			`endif
184			`, instField1`
185
186			`, branchOut,`
187	6	maheshpalv	`accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,`
188	5	maheshpalv	`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
189			`inputReadOut, outputRwOut`
190
191			`ifdef timerAndCounter_peripheral
192			`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut`
193			`endif
194
195			`ifdef UART_peripheral
196			`, uartReadOut, uartWriteOut`
197			`endif
198
199			`ifdef SPI_peripheral
200			`, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut`
201			`endif
202
203			`, instField2`
204			`);`
205
206
207	3	maheshpalv	`//-------- Execute Unit Modules Instances`
208			`// all necessary`
209
210
211
212
213	5	maheshpalv	`accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut`
214			`ifdef timerAndCounter_peripheral
215			`, tcLoadOut, tcAccOut`
216			`endif
217			`ifdef UART_peripheral
218			`, uartDataOut`
219			`endif
220			`ifdef SPI_peripheral
221			`, spiStatOut, spiBufOut`
222			`endif
223			`, accMuxOut`
224			`);`
225
226	3	maheshpalv
227	5	maheshpalv	`accumulator acc (accMuxOut, accEnOut, accOut);`
228	3	maheshpalv
229	5	maheshpalv	`op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);`
230	3	maheshpalv
231	5	maheshpalv	`wire [7:0] op2Out;`
232	3	maheshpalv
233	5	maheshpalv	`byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);`
234	3	maheshpalv
235	6	maheshpalv	`alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);`
236	3	maheshpalv
237	5	maheshpalv	`wire bitIn;`
238	3	maheshpalv
239	5	maheshpalv	`bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);`
240	3	maheshpalv
241	5	maheshpalv	`bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);`
242	3	maheshpalv
243	5	maheshpalv	`wire [7:0] byteIn;`
244	3	maheshpalv
245	5	maheshpalv	`byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);`
246	3	maheshpalv
247	5	maheshpalv	`byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);`
248
249			`inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);`
250
251			`outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);`
252
253	3	maheshpalv
254			`//---------- Timer & Counter Modules`
255			`// optional`
256
257			`ifdef timerAndCounter_peripheral
258
259	5	maheshpalv
260
261
262			`tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);`
263	3	maheshpalv
264	5	maheshpalv	`tcAccum tcAccumModule(tcAccumReadOut, instField2[3:0], tcAccumWires, tcAccOut);`
265	3	maheshpalv
266	5	maheshpalv	`tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);`
267	3	maheshpalv
268	5	maheshpalv	`tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);`
269	3	maheshpalv
270	5	maheshpalv	`tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);`
271	3	maheshpalv
272	5	maheshpalv	`timer timer0 (clk, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);`
273	3	maheshpalv
274	5	maheshpalv	`timer timer1 (clk, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);`
275	3	maheshpalv
276	5	maheshpalv	`timer timer2 (clk, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);`
277	3	maheshpalv
278	5	maheshpalv	`timer timer3 (clk, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);`
279	3	maheshpalv
280	5	maheshpalv	`counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);`
281	3	maheshpalv
282	5	maheshpalv	`counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);`
283	3	maheshpalv
284	5	maheshpalv	`counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);`
285	3	maheshpalv
286	5	maheshpalv	`counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);`
287	3	maheshpalv
288			`endif
289
290			`//---------- UART Modules`
291			`// optional`
292
293			`ifdef UART_peripheral
294
295	5	maheshpalv	`wire brgOut;`
296			`wire txDoneTick, txStart;`
297			`wire rxDoneTick;`
298			`wire [7:0] recFifoData, transFifoData;`
299
300	3	maheshpalv
301	5	maheshpalv	`uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);`
302	3	maheshpalv
303	5	maheshpalv	`uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);`
304	3	maheshpalv
305	5	maheshpalv	`uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));`
306	3	maheshpalv
307	5	maheshpalv	`uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);`
308	3	maheshpalv
309	5	maheshpalv	`uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);`
310
311	3	maheshpalv	`endif
312
313			`//---------- SPI Modules`
314			`// optional`
315
316			`ifdef SPI_peripheral
317
318	6	maheshpalv
319			`spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);`
320
321
322	3	maheshpalv	`endif
323
324			`endmodule`

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