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`include "timescale.v"
`include "defines.v"
 
module top(clk, reset, IN, OUT
 
                                `ifdef UART_peripheral
                                        , rx, tx
                                `endif
 
                                `ifdef SPI_peripheral
                                        , MISO, MOSI, SCK
                                `endif
 
                                );
 
 
        input   clk,reset;
        input [`inputNumber-1:0] IN;
        output [`outputNumber-1:0] OUT;
 
        `ifdef UART_peripheral
        input rx;
        output tx;
        `endif
 
        `ifdef SPI_peripheral
        input MISO;
        output MOSI, SCK;
        `endif
 
// wires (interconnects) of execution unit
 
        wire    [`instAddrLen-1:0]                       pcOut;
        wire    [`instOpCodeLen+`instFieldLen-1:0] romOut;
        wire    [`instOpCodeLen-1:0]     instOpCode;
        wire    [`instFieldLen-1:0]      instField;
 
        wire    [7:0]            accMuxOut;
        wire    [7:0]            accOut;
        wire    [7:0]            op2MuxOut;
        wire    [7:0]            aluOut;
 
        wire    bitNegatorRamOut, bitOut;
        wire    [7:0]    byteNegatorRamOut, byteOut;
 
        wire    inputReadOutData, outputReadOut;
 
        wire branchOutc;
        wire [`accMuxSelLen-1:0] accMuxSelOutc;
        wire accEnOutc;
        wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
        wire aluEnc;
        wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
        wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;
        wire inputReadOutc, outputRwOutc;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;
        `endif
        `ifdef UART_peripheral
        wire uartReadOutc, uartWriteOutc;
        wire [7:0] uartDataOut;
        wire rxEmpty, txFull;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;
        `endif
 
        wire branchOut;
        wire [`accMuxSelLen-1:0] accMuxSelOut;
        wire accEnOut;
        wire [`op2MuxSelLen-1:0] op2MuxSelOut;
        wire aluEn;
        wire [`aluOpcodeLen-1:0] aluOpcodeOut;
        wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;
        wire inputReadOut, outputRwOut;
        `ifdef timerAndCounter_peripheral
        wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;
        `endif
        `ifdef UART_peripheral
        wire uartReadOut, uartWriteOut;
        `endif
        `ifdef SPI_peripheral
        wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;
        `endif
 
 
 
// wires (interconnects) of timer & counter
 
`ifdef timerAndCounter_peripheral
 
        wire    [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
        wire    [7:0] tcAccOut;
        wire    [7:0] tcLoadOut;
        wire [`tcNumbers-1:0] enWires;
        wire [`tcNumbers-1:0] resetWires;
        wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
        wire [(`tcNumbers*2)-1:0] typeWires;
        wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
 
`endif
 
`ifdef SPI_peripheral
 
        wire [7:0] spiStatOut, spiBufOut;
`endif
 
 
        wire clk_d, clk_t;
        reg [10:0] cnt = 0;
 
        always @ (posedge clk or posedge reset)
        begin
                if (reset)
                begin
                        cnt =0;
                end
                else
                begin
                        cnt = cnt + 1'b1;
                end
        end
 
        assign clk_d = cnt[0];
        assign clk_t = cnt[10];
 
 
 
//-------- Fetch Unit Module Instances
// all necessary
 
        pgmCounter              ProgramCounter (clk_d, reset, branchOutc, instField[9:0], pcOut);
 
 
// instruction ROM is declared using xilinx primitive
        RAMB16_S18 rom ( .DI(),
                                 .DIP(),
                                 .ADDR(pcOut),
                                 .EN(1'b1),
                                 .WE(),
                                 .SSR(1'b0),
                                 .CLK(clk_d),
                                 .DO(romOut),
                                 .DOP());
 
//      rom     CodeMem (pcOut, romOut);
 
// pipeline register
 
        wire    [`instOpCodeLen-1:0] instOpCode1;
        wire    [`instFieldLen-1:0] instField1;
        wire    [`instFieldLen-1:0] instField2;
 
        ppReg1  PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
 
 
//-------- Control Unit Module Instance
 
        controlUnit             CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],
                                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
 
                                                                                        );
 
 
 
// pipeline register
 
 
 
        ppReg2  PipeLine_Reg2 (clk,
                                                                        branchOutc,
                                                                        accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,
                                                                        bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc
                                                                `ifdef timerAndCounter_peripheral
                                                                , entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc
                                                                `endif
                                                                `ifdef UART_peripheral
                                                                , uartReadOutc, uartWriteOutcc
                                                                `endif
                                                                `ifdef SPI_peripheral
                                                                , sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc
                                                                `endif
                                                                , instField1
 
                                                                        , branchOut,
                                                                        accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,
                                                                        bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,
                                                                        inputReadOut, outputRwOut
 
                                                                        `ifdef timerAndCounter_peripheral
                                                                                , entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut
                                                                        `endif
 
                                                                        `ifdef UART_peripheral
                                                                                , uartReadOut, uartWriteOut
                                                                        `endif
 
                                                                        `ifdef SPI_peripheral
                                                                                , sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut
                                                                        `endif
 
                                                                        , instField2
                                                                );
 
 
//-------- Execute Unit Modules Instances
// all necessary
 
 
 
 
        accumulatorMUX          accMUX1 (accMuxSelOut, instField2[7:0], aluOut
                                                                                `ifdef timerAndCounter_peripheral
                                                                                , tcLoadOut, tcAccOut
                                                                                `endif
                                                                                `ifdef UART_peripheral
                                                                                , uartDataOut, {rxEmpty, txFull}
                                                                                `endif
                                                                                `ifdef SPI_peripheral
                                                                                , spiStatOut, spiBufOut
                                                                                `endif
                                                                                , accMuxOut
                                                                                );
 
 
        accumulator                     acc             (accMuxOut, accEnOut, accOut);
 
        op2Mux                          op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);
 
        wire [7:0] op2Out;
 
        byteNegator                     byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);
 
        alu                                     arithLogicUnit  (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);
 
        wire bitIn;
 
        bitNegator                      bitNegatorForBitRam     (accOut[0], instField2[9], bitIn);
 
        bitRam                          RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);
 
        wire [7:0] byteIn;
 
        byteNegator                     byteNegatorForByteRam   (accOut, instField2[9], byteIn);
 
        byteRam                         RAM_Byte        (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);
 
        inputRegister           inputStorage    (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);
 
        outputReg                       outputStorage   (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);
 
 
//---------- Timer & Counter Modules
// optional
 
`ifdef timerAndCounter_peripheral
 
 
 
 
        tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);
 
        tcAccum                         tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);
 
        tcReset                         tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);
 
        tcPreset                                tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);
 
        tcLoad                          tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);
 
        timer                                   timer0  (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);
 
        timer                                   timer1  (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);
 
        timer                                   timer2  (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);
 
        timer                                   timer3  (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);
 
        counter                         counter0        (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);
 
        counter                         counter1        (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);
 
        counter                         counter2        (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);
 
        counter                         counter3        (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);
 
`endif
 
//---------- UART Modules
// optional
 
`ifdef UART_peripheral
 
        wire    brgOut;
        wire txDoneTick, txStart;
        wire rxDoneTick;
        wire [7:0] recFifoData, transFifoData;
 
 
        uartTrans       UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);
 
        uartRec         UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);
 
        uartBrg         UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));
 
        uartFifo                UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);
 
        uartFifo                UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);
 
`endif
 
//---------- SPI Modules
// optional
 
`ifdef SPI_peripheral
 
 
        spi_top         SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);
 
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	3	maheshpalv	`include "timescale.v"
2			`include "defines.v"
3
4			`module top(clk, reset, IN, OUT`
5
6			`ifdef UART_peripheral
7			`, rx, tx`
8			`endif
9
10			`ifdef SPI_peripheral
11			`, MISO, MOSI, SCK`
12			`endif
13
14			`);`
15
16
17			`input clk,reset;`
18			input [`inputNumber-1:0] IN;
19			output [`outputNumber-1:0] OUT;
20
21			`ifdef UART_peripheral
22			`input rx;`
23			`output tx;`
24			`endif
25
26			`ifdef SPI_peripheral
27			`input MISO;`
28			`output MOSI, SCK;`
29			`endif
30
31			`// wires (interconnects) of execution unit`
32
33	8	maheshpalv	wire [`instAddrLen-1:0] pcOut;
34	5	maheshpalv	wire [`instOpCodeLen+`instFieldLen-1:0] romOut;
35	3	maheshpalv	wire [`instOpCodeLen-1:0] instOpCode;
36			wire [`instFieldLen-1:0] instField;
37
38			`wire [7:0] accMuxOut;`
39			`wire [7:0] accOut;`
40			`wire [7:0] op2MuxOut;`
41			`wire [7:0] aluOut;`
42
43			`wire bitNegatorRamOut, bitOut;`
44			`wire [7:0] byteNegatorRamOut, byteOut;`
45
46	5	maheshpalv	`wire inputReadOutData, outputReadOut;`
47	3	maheshpalv
48	5	maheshpalv	`wire branchOutc;`
49			wire [`accMuxSelLen-1:0] accMuxSelOutc;
50			`wire accEnOutc;`
51			wire [`op2MuxSelLen-1:0] op2MuxSelOutc;
52	6	maheshpalv	`wire aluEnc;`
53	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOutc;
54			`wire bitRamEnOutc, bitRamRwOutc, byteRamEnOutc, byteRamRwOutc;`
55			`wire inputReadOutc, outputRwOutc;`
56			`ifdef timerAndCounter_peripheral
57			`wire entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc;`
58			`endif
59			`ifdef UART_peripheral
60			`wire uartReadOutc, uartWriteOutc;`
61	7	maheshpalv	`wire [7:0] uartDataOut;`
62			`wire rxEmpty, txFull;`
63	5	maheshpalv	`endif
64			`ifdef SPI_peripheral
65			`wire sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc;`
66			`endif
67	3	maheshpalv
68	5	maheshpalv	`wire branchOut;`
69			wire [`accMuxSelLen-1:0] accMuxSelOut;
70			`wire accEnOut;`
71			wire [`op2MuxSelLen-1:0] op2MuxSelOut;
72	6	maheshpalv	`wire aluEn;`
73	5	maheshpalv	wire [`aluOpcodeLen-1:0] aluOpcodeOut;
74			`wire bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut;`
75			`wire inputReadOut, outputRwOut;`
76	3	maheshpalv	`ifdef timerAndCounter_peripheral
77	5	maheshpalv	`wire entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut;`
78			`endif
79			`ifdef UART_peripheral
80			`wire uartReadOut, uartWriteOut;`
81			`endif
82			`ifdef SPI_peripheral
83			`wire sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut;`
84			`endif
85
86	3	maheshpalv
87	5	maheshpalv
88			`// wires (interconnects) of timer & counter`
89
90			`ifdef timerAndCounter_peripheral
91
92			wire [(`tcNumbers*`tcPresetLen)-1:0] presetWires;
93	7	maheshpalv	`wire [7:0] tcAccOut;`
94	5	maheshpalv	`wire [7:0] tcLoadOut;`
95			wire [`tcNumbers-1:0] enWires;
96			wire [`tcNumbers-1:0] resetWires;
97			wire [`tcNumbers-1:0] dnWires, ttWires, cuWires, cdWires;
98			wire [(`tcNumbers*2)-1:0] typeWires;
99			wire [(`tcNumbers*`tcAccLen)-1:0] tcAccWires;
100
101			`endif
102
103	8	maheshpalv	`ifdef SPI_peripheral
104	5	maheshpalv
105	8	maheshpalv	`wire [7:0] spiStatOut, spiBufOut;`
106			`endif
107
108
109			`wire clk_d, clk_t;`
110			`reg [10:0] cnt = 0;`
111	5	maheshpalv
112	8	maheshpalv	`always @ (posedge clk or posedge reset)`
113			`begin`
114			`if (reset)`
115			`begin`
116			`cnt =0;`
117			`end`
118			`else`
119			`begin`
120			`cnt = cnt + 1'b1;`
121			`end`
122			`end`
123	5	maheshpalv
124	8	maheshpalv	`assign clk_d = cnt[0];`
125			`assign clk_t = cnt[10];`
126	3	maheshpalv
127
128
129			`//-------- Fetch Unit Module Instances`
130			`// all necessary`
131
132	8	maheshpalv	`pgmCounter ProgramCounter (clk_d, reset, branchOutc, instField[9:0], pcOut);`
133	3	maheshpalv
134
135			`// instruction ROM is declared using xilinx primitive`
136			`RAMB16_S18 rom ( .DI(),`
137			`.DIP(),`
138	5	maheshpalv	`.ADDR(pcOut),`
139	3	maheshpalv	`.EN(1'b1),`
140			`.WE(),`
141			`.SSR(1'b0),`
142	8	maheshpalv	`.CLK(clk_d),`
143	5	maheshpalv	`.DO(romOut),`
144	3	maheshpalv	`.DOP());`
145
146	8	maheshpalv	`// rom CodeMem (pcOut, romOut);`
147	3	maheshpalv
148	5	maheshpalv	`// pipeline register`
149
150			wire [`instOpCodeLen-1:0] instOpCode1;
151			wire [`instFieldLen-1:0] instField1;
152			wire [`instFieldLen-1:0] instField2;
153
154	8	maheshpalv	ppReg1 PipeLine_Reg1 (clk_d, romOut[`instLen-1:`instLen-`instOpCodeLen], romOut[`instFieldLen-1:0], instOpCode1, instField1);
155	5	maheshpalv
156
157			`//-------- Control Unit Module Instance`
158
159			`controlUnit CONTROL_UNIT (clk, reset, instOpCode1, accOut[0], instField2[8:7],`
160	6	maheshpalv	`branchOutc,`
161			`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
162			`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
163			`ifdef timerAndCounter_peripheral
164			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
165			`endif
166			`ifdef UART_peripheral
167			`, uartReadOutc, uartWriteOutcc`
168			`endif
169			`ifdef SPI_peripheral
170			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
171			`endif
172	5	maheshpalv
173			`);`
174
175
176
177			`// pipeline register`
178
179
180
181			`ppReg2 PipeLine_Reg2 (clk,`
182			`branchOutc,`
183	6	maheshpalv	`accMuxSelOutc, accEnOutc, op2MuxSelOutc, aluEnc, aluOpcodeOutc, bitRamEnOutc,`
184	5	maheshpalv	`bitRamRwOutc, byteRamEnOutc, byteRamRwOutc, inputReadOutc, outputRwOutc`
185			`ifdef timerAndCounter_peripheral
186			`, entypeEnOutc, tcAccReadOutc, tcResetEnOutc, tcPresetEnOutc, tcLoadEnOutc`
187			`endif
188			`ifdef UART_peripheral
189			`, uartReadOutc, uartWriteOutcc`
190			`endif
191			`ifdef SPI_peripheral
192			`, sconEnOutc, spiStatReadOutc, spiBufReadOutc, spiBufWriteOutc, spiBufShiftOutc`
193			`endif
194			`, instField1`
195
196			`, branchOut,`
197	6	maheshpalv	`accMuxSelOut, accEnOut, op2MuxSelOut, aluEn, aluOpcodeOut,`
198	5	maheshpalv	`bitRamEnOut, bitRamRwOut, byteRamEnOut, byteRamRwOut,`
199			`inputReadOut, outputRwOut`
200
201			`ifdef timerAndCounter_peripheral
202			`, entypeEnOut, tcAccReadOut, tcResetEnOut, tcPresetEnOut, tcLoadEnOut`
203			`endif
204
205			`ifdef UART_peripheral
206			`, uartReadOut, uartWriteOut`
207			`endif
208
209			`ifdef SPI_peripheral
210			`, sconEnOut, spiStatReadOut, spiBufReadOut, spiBufWriteOut, spiBufShiftOut`
211			`endif
212
213			`, instField2`
214			`);`
215
216
217	3	maheshpalv	`//-------- Execute Unit Modules Instances`
218			`// all necessary`
219
220
221
222
223	5	maheshpalv	`accumulatorMUX accMUX1 (accMuxSelOut, instField2[7:0], aluOut`
224			`ifdef timerAndCounter_peripheral
225			`, tcLoadOut, tcAccOut`
226			`endif
227			`ifdef UART_peripheral
228	7	maheshpalv	`, uartDataOut, {rxEmpty, txFull}`
229	5	maheshpalv	`endif
230			`ifdef SPI_peripheral
231			`, spiStatOut, spiBufOut`
232			`endif
233			`, accMuxOut`
234			`);`
235
236	3	maheshpalv
237	5	maheshpalv	`accumulator acc (accMuxOut, accEnOut, accOut);`
238	3	maheshpalv
239	5	maheshpalv	`op2Mux op2MUX1 (op2MuxSelOut, inputReadOutData, outputReadOut, bitOut, byteOut, op2MuxOut);`
240	3	maheshpalv
241	5	maheshpalv	`wire [7:0] op2Out;`
242	3	maheshpalv
243	5	maheshpalv	`byteNegator byteNegatorForOp2Mux (op2MuxOut, instField2[9], op2Out);`
244	3	maheshpalv
245	6	maheshpalv	`alu arithLogicUnit (aluOpcodeOut, accOut, op2Out, aluEn, aluOut, carryOut);`
246	3	maheshpalv
247	5	maheshpalv	`wire bitIn;`
248	3	maheshpalv
249	5	maheshpalv	`bitNegator bitNegatorForBitRam (accOut[0], instField2[9], bitIn);`
250	3	maheshpalv
251	5	maheshpalv	`bitRam RAM_Bit (clk, reset, bitRamEnOut, bitRamRwOut, bitIn, instField2[6:0], bitOut);`
252	3	maheshpalv
253	5	maheshpalv	`wire [7:0] byteIn;`
254	3	maheshpalv
255	5	maheshpalv	`byteNegator byteNegatorForByteRam (accOut, instField2[9], byteIn);`
256	3	maheshpalv
257	5	maheshpalv	`byteRam RAM_Byte (clk, reset, byteRamEnOut, byteRamRwOut, byteIn, instField2[6:0], byteOut);`
258
259			`inputRegister inputStorage (reset, IN, inputReadOut, instField2[6:0], inputReadOutData);`
260
261			`outputReg outputStorage (reset, outputRwOut, instField2[6:0], accOut[0], outputReadOut, OUT);`
262
263	3	maheshpalv
264			`//---------- Timer & Counter Modules`
265			`// optional`
266
267			`ifdef timerAndCounter_peripheral
268
269	5	maheshpalv
270
271
272			`tcEnableAndType tcEnableAndTypeModule(entypeEnOut, instField2[6], instField2[5:4], instField2[3:0], enWires, typeWires);`
273	3	maheshpalv
274	7	maheshpalv	`tcAccum tcAccumModule(tcAccReadOut, instField2[3:0], tcAccWires, tcAccOut);`
275	3	maheshpalv
276	5	maheshpalv	`tcReset tcResetModule(tcResetEnOut, instField2[4], instField2[3:0], resetWires);`
277	3	maheshpalv
278	5	maheshpalv	`tcPreset tcPresetModule(tcPresetEnOut, accOut, instField2[3:0], presetWires);`
279	3	maheshpalv
280	5	maheshpalv	`tcLoad tcLoadModule(tcLoadEnOut, instField2[3:0], dnWires, ttWires, cuWires, cdWires, tcLoadOut);`
281	3	maheshpalv
282	8	maheshpalv	`timer timer0 (clk_t, enWires[0], resetWires[0], typeWires[1:0], presetWires[7:0], dnWires[0], ttWires[0], tcAccWires[7:0]);`
283	3	maheshpalv
284	8	maheshpalv	`timer timer1 (clk_t, enWires[1], resetWires[1], typeWires[3:2], presetWires[15:8], dnWires[1], ttWires[1], tcAccWires[15:8]);`
285	3	maheshpalv
286	8	maheshpalv	`timer timer2 (clk_t, enWires[2], resetWires[2], typeWires[5:4], presetWires[23:16], dnWires[2], ttWires[2], tcAccWires[23:16]);`
287	3	maheshpalv
288	8	maheshpalv	`timer timer3 (clk_t, enWires[3], resetWires[3], typeWires[7:6], presetWires[31:24], dnWires[3], ttWires[3], tcAccWires[31:24]);`
289	3	maheshpalv
290	5	maheshpalv	`counter counter0 (enWires[4], resetWires[4], presetWires[39:32], typeWires[9:8], dnWires[4], cuWires[0], cdWires[0], tcAccWires[39:32]);`
291	3	maheshpalv
292	5	maheshpalv	`counter counter1 (enWires[5], resetWires[5], presetWires[47:40], typeWires[11:10], dnWires[5], cuWires[1], cdWires[1], tcAccWires[47:40]);`
293	3	maheshpalv
294	5	maheshpalv	`counter counter2 (enWires[6], resetWires[6], presetWires[55:48], typeWires[13:12], dnWires[6], cuWires[2], cdWires[2], tcAccWires[55:48]);`
295	3	maheshpalv
296	5	maheshpalv	`counter counter3 (enWires[7], resetWires[7], presetWires[63:56], typeWires[15:14], dnWires[7], cuWires[3], cdWires[3], tcAccWires[63:56]);`
297	3	maheshpalv
298			`endif
299
300			`//---------- UART Modules`
301			`// optional`
302
303			`ifdef UART_peripheral
304
305	5	maheshpalv	`wire brgOut;`
306			`wire txDoneTick, txStart;`
307			`wire rxDoneTick;`
308			`wire [7:0] recFifoData, transFifoData;`
309
310	3	maheshpalv
311	5	maheshpalv	`uartTrans UART_TRANSMITTER (clk, reset, brgOut, txDoneTick, transFifoData, tx, ~txStart);`
312	3	maheshpalv
313	5	maheshpalv	`uartRec UART_RECIEVER (clk, reset, brgOut, rx, rxDoneTick, recFifoData);`
314	3	maheshpalv
315	5	maheshpalv	`uartBrg UART_BitRateGenerator (.clk(clk), .reset(reset), .outp(brgOut));`
316	3	maheshpalv
317	5	maheshpalv	`uartFifo UART_TRANS_FIFO (clk, reset, accOut, transFifoData, uartWriteOut, txDoneTick, txFull, txStart);`
318	3	maheshpalv
319	5	maheshpalv	`uartFifo UART_REC_FIFO (clk, reset, recFifoData, uartDataOut, rxDoneTick, uartReadOut, rxFull, rxEmpty);`
320
321	3	maheshpalv	`endif
322
323			`//---------- SPI Modules`
324			`// optional`
325
326			`ifdef SPI_peripheral
327
328	6	maheshpalv
329			`spi_top SPI_TOP (clk, sconEnOut, spiStatReadOut, instField2[7:0], spiStatOut, spiBufWriteOut, spiBufReadOut, aluOut, spiBufOut, MI, MO, SCK);`
330
331
332	3	maheshpalv	`endif
333
334			`endmodule`

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