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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [uartFifo.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module uartFifo(clk, reset, wData, rData, wr, rd, full, empty);
 
                parameter dataBits = `dataBits;
                parameter fifoWidth = `fifoWidth;
                parameter fiforegs = `number_fifo_regs;
                parameter fifoCntrWidth = `fifoCntrWidth;
                parameter fifodepth = `fifoDepth;
 
        //      integer i;
 
                input [dataBits-1 : 0] wData;
                input clk, reset, rd, wr;
                output [`dataBits-1 : 0] rData;
                output full, empty;
 
                reg [dataBits-1 : 0] fifoReg [0:fiforegs-1];
 
                reg [dataBits-1 : 0] rData;
 
                reg full=1'b0, empty=1'b1;
 
                // pointers
                reg [fifoWidth-1 : 0] top = 4'b1111, bottom = 4'b1111;
                wire [fifoWidth-1 : 0] topPlusOne = top + 1'b1;
 
                //counter
                reg [fifoCntrWidth-1 : 0] cntr = 0;
 
 
                        always @ (posedge clk or posedge reset)
                        begin
 
                                if (reset)
                                begin
                                                top = 0;
                                                bottom = 0;
 
                                                fifoReg[0] = 0;
                                                fifoReg[1] = 0;
                                                fifoReg[2] = 0;
                                                fifoReg[3] = 0;
                                                fifoReg[4] = 0;
                                                fifoReg[5] = 0;
                                                fifoReg[6] = 0;
                                                fifoReg[7] = 0;
                                                fifoReg[8] = 0;
                                                fifoReg[9] = 0;
                                                fifoReg[10] = 0;
                                                fifoReg[11] = 0;
                                                fifoReg[12] = 0;
                                                fifoReg[13] = 0;
                                                fifoReg[14] = 0;
                                                fifoReg[15] = 0;
                                end //end if(reset)
 
 
 
                                else
                                begin
 
                                        case ({rd, wr})
 
                                                2'b 01  :       if (cntr <= fifodepth)
                                                                                begin
                                                                                fifoReg[top] = wData;
                                                                                top = topPlusOne;
                                                                                cntr = cntr + 1'b1;
                                                                                end
 
                                                2'b 10  :       if (cntr > 0)
                                                                                begin
                                                                                rData = fifoReg[bottom];
                                                                                fifoReg[bottom] = 0;
                                                                                bottom = bottom + 1'b1;
                                                                                cntr = cntr - 1'b1;
 
                                                                                end
 
                                                2'b 11  :       if ((cntr >0) & (cntr <= fifodepth))
                                                                                begin
                                                                                rData = fifoReg[bottom];
                                                                                fifoReg[bottom] = 0;
                                                                                bottom = bottom + 1'b1;
                                                                                fifoReg[top] = wData;
                                                                                top = topPlusOne;
                                                                                end
 
                                                default :       ;
                                        endcase
 
                                end // end else
 
                        end // end always
 
                        //assign rData = fifoReg[bottom];
 
                        always @ (posedge clk or posedge reset)
                        begin
 
                                if (reset)
                                begin
                                        full <= 1'b0;
                                        empty <= 1'b1;  end
 
                                else
                                begin
                                        if(~rd & (cntr>=(fifodepth-1)))
                                        begin
                                                full <= 1'b1;
                                                //$display ($time, " ns \t * FIFO FULL ");
                                                empty <= 1'b0;  end
 
                                        else if (~wr & (cntr==4'b0000))
                                        begin
                                                empty <= 1'b1;
                                                full <= 1'b0;   end
 
                                        else if ((cntr != 0) | (cntr != fifodepth))
                                        begin
                                                empty <= 1'b0;
                                                full <= 1'b0;   end
                                        end     // end else i.e. (!reset)
 
                        end     // end always 
 
 
                        always @ *
                        begin
 
                                if (full & wr)
                                $display ($time, "ns \t\t attempting to write to full fifo.... data overwritten");
 
                                else
                                if (empty & rd)
                                $display ($time, "ns \t\t attempting to read from empty fifo...");
 
                        end
 
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45			`module uartFifo(clk, reset, wData, rData, wr, rd, full, empty);`
46
47			parameter dataBits = `dataBits;
48			parameter fifoWidth = `fifoWidth;
49			parameter fiforegs = `number_fifo_regs;
50			parameter fifoCntrWidth = `fifoCntrWidth;
51			parameter fifodepth = `fifoDepth;
52
53			`// integer i;`
54
55			`input [dataBits-1 : 0] wData;`
56			`input clk, reset, rd, wr;`
57			output [`dataBits-1 : 0] rData;
58			`output full, empty;`
59
60			`reg [dataBits-1 : 0] fifoReg [0:fiforegs-1];`
61
62			`reg [dataBits-1 : 0] rData;`
63
64			`reg full=1'b0, empty=1'b1;`
65
66			`// pointers`
67			`reg [fifoWidth-1 : 0] top = 4'b1111, bottom = 4'b1111;`
68			`wire [fifoWidth-1 : 0] topPlusOne = top + 1'b1;`
69
70			`//counter`
71			`reg [fifoCntrWidth-1 : 0] cntr = 0;`
72
73
74			`always @ (posedge clk or posedge reset)`
75			`begin`
76
77			`if (reset)`
78			`begin`
79			`top = 0;`
80			`bottom = 0;`
81
82			`fifoReg[0] = 0;`
83			`fifoReg[1] = 0;`
84			`fifoReg[2] = 0;`
85			`fifoReg[3] = 0;`
86			`fifoReg[4] = 0;`
87			`fifoReg[5] = 0;`
88			`fifoReg[6] = 0;`
89			`fifoReg[7] = 0;`
90			`fifoReg[8] = 0;`
91			`fifoReg[9] = 0;`
92			`fifoReg[10] = 0;`
93			`fifoReg[11] = 0;`
94			`fifoReg[12] = 0;`
95			`fifoReg[13] = 0;`
96			`fifoReg[14] = 0;`
97			`fifoReg[15] = 0;`
98			`end //end if(reset)`
99
100
101
102			`else`
103			`begin`
104
105			`case ({rd, wr})`
106
107			`2'b 01 : if (cntr <= fifodepth)`
108			`begin`
109			`fifoReg[top] = wData;`
110			`top = topPlusOne;`
111			`cntr = cntr + 1'b1;`
112			`end`
113
114			`2'b 10 : if (cntr > 0)`
115			`begin`
116			`rData = fifoReg[bottom];`
117			`fifoReg[bottom] = 0;`
118			`bottom = bottom + 1'b1;`
119			`cntr = cntr - 1'b1;`
120
121			`end`
122
123			`2'b 11 : if ((cntr >0) & (cntr <= fifodepth))`
124			`begin`
125			`rData = fifoReg[bottom];`
126			`fifoReg[bottom] = 0;`
127			`bottom = bottom + 1'b1;`
128			`fifoReg[top] = wData;`
129			`top = topPlusOne;`
130			`end`
131
132			`default : ;`
133			`endcase`
134
135			`end // end else`
136
137			`end // end always`
138
139			`//assign rData = fifoReg[bottom];`
140
141			`always @ (posedge clk or posedge reset)`
142			`begin`
143
144			`if (reset)`
145			`begin`
146			`full <= 1'b0;`
147			`empty <= 1'b1; end`
148
149			`else`
150			`begin`
151			`if(~rd & (cntr>=(fifodepth-1)))`
152			`begin`
153			`full <= 1'b1;`
154			`//$display ($time, " ns \t * FIFO FULL ");`
155			`empty <= 1'b0; end`
156
157			`else if (~wr & (cntr==4'b0000))`
158			`begin`
159			`empty <= 1'b1;`
160			`full <= 1'b0; end`
161
162			`else if ((cntr != 0) \| (cntr != fifodepth))`
163			`begin`
164			`empty <= 1'b0;`
165			`full <= 1'b0; end`
166			`end // end else i.e. (!reset)`
167
168			`end // end always`
169
170
171			`always @ *`
172			`begin`
173
174			`if (full & wr)`
175			`$display ($time, "ns \t\t attempting to write to full fifo.... data overwritten");`
176
177			`else`
178			`if (empty & rd)`
179			`$display ($time, "ns \t\t attempting to read from empty fifo...");`
180
181			`end`
182
183
184			`endmodule`

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [uartFifo.v] - Blame information for rev 10