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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [uartFifo.v] - Blame information for rev 8

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1 3 maheshpalv 
 
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`include "timescale.v"
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`include "defines.v"
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module uartFifo(clk, reset, wData, rData, wr, rd, full, empty);
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                parameter dataBits = `dataBits;
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                parameter fifoWidth = `fifoWidth;
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                parameter fiforegs = `number_fifo_regs;
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                parameter fifoCntrWidth = `fifoCntrWidth;
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                parameter fifodepth = `fifoDepth;
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        //      integer i;
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                input [dataBits-1 : 0] wData;
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                input clk, reset, rd, wr;
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                output [`dataBits-1 : 0] rData;
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                output full, empty;
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                reg [dataBits-1 : 0] fifoReg [0:fiforegs-1];
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                reg [dataBits-1 : 0] rData;
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                reg full=1'b0, empty=1'b1;
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                // pointers
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                reg [fifoWidth-1 : 0] top = 4'b1111, bottom = 4'b1111;
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                wire [fifoWidth-1 : 0] topPlusOne = top + 1'b1;
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                //counter
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                reg [fifoCntrWidth-1 : 0] cntr = 0;
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                        always @ (posedge clk or posedge reset)
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                        begin
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                                if (reset)
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                                begin
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                                                top = 0;
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                                                bottom = 0;
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                                                fifoReg[0] = 0;
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                                                fifoReg[1] = 0;
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                                                fifoReg[2] = 0;
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                                                fifoReg[3] = 0;
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                                                fifoReg[4] = 0;
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                                                fifoReg[5] = 0;
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                                                fifoReg[6] = 0;
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                                                fifoReg[7] = 0;
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                                                fifoReg[8] = 0;
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                                                fifoReg[9] = 0;
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                                                fifoReg[10] = 0;
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                                                fifoReg[11] = 0;
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                                                fifoReg[12] = 0;
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                                                fifoReg[13] = 0;
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                                                fifoReg[14] = 0;
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                                                fifoReg[15] = 0;
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                                end //end if(reset)
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                                else
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                                begin
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                                        case ({rd, wr})
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                                                2'b 01  :       if (cntr <= fifodepth)
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                                                                                begin
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                                                                                fifoReg[top] = wData;
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                                                                                top = topPlusOne;
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                                                                                cntr = cntr + 1'b1;
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                                                                                end
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                                                2'b 10  :       if (cntr > 0)
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                                                                                begin
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                                                                                rData = fifoReg[bottom];
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                                                                                fifoReg[bottom] = 0;
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                                                                                bottom = bottom + 1'b1;
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                                                                                cntr = cntr - 1'b1;
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                                                                                end
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                                                2'b 11  :       if ((cntr >0) & (cntr <= fifodepth))
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                                                                                begin
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                                                                                rData = fifoReg[bottom];
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                                                                                fifoReg[bottom] = 0;
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                                                                                bottom = bottom + 1'b1;
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                                                                                fifoReg[top] = wData;
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                                                                                top = topPlusOne;
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                                                                                end
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                                                default :       ;
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                                        endcase
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                                end // end else
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                        end // end always
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                        //assign rData = fifoReg[bottom];
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                        always @ (posedge clk or posedge reset)
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                        begin
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                                if (reset)
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                                begin
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                                        full <= 1'b0;
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                                        empty <= 1'b1;  end
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                                else
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                                begin
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                                        if(~rd & (cntr>=(fifodepth-1)))
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                                        begin
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                                                full <= 1'b1;
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                                                //$display ($time, " ns \t * FIFO FULL ");
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                                                empty <= 1'b0;  end
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                                        else if (~wr & (cntr==4'b0000))
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                                        begin
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                                                empty <= 1'b1;
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                                                full <= 1'b0;   end
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                                        else if ((cntr != 0) | (cntr != fifodepth))
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                                        begin
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                                                empty <= 1'b0;
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                                                full <= 1'b0;   end
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                                        end     // end else i.e. (!reset)
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                        end     // end always
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                        always @ *
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                        begin
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                                if (full & wr)
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                                $display ($time, "ns \t\t attempting to write to full fifo.... data overwritten");
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                                else
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                                if (empty & rd)
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                                $display ($time, "ns \t\t attempting to read from empty fifo...");
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                        end
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endmodule

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