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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [uartTrans.v] - Blame information for rev 10

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////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                    ////
////                                                                                                                    ////
////    This file is part of the project                                                                                        ////
////    "instruction_list_pipelined_processor_with_peripherals"                                                         ////
////                                                                                                                    ////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals        ////
////                                                                                                                    ////
////                                                                                                                    ////
////                             Author:                                                                                ////
////                            - Mahesh Sukhdeo Palve                                                                                                  ////
////                                                                                                                                                                            ////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
////                                                                                                                                                                            ////
////                                                                                                                                                            ////
////                                                                                                                    ////
////                                    This source file may be used and distributed without                    ////
////                                    restriction provided that this copyright statement is not               ////
////                                    removed from the file and that any derivative work contains             ////
////                                    the original copyright notice and the associated disclaimer.            ////
////                                                                                                                    ////
////                                    This source file is free software; you can redistribute it              ////
////                                    and/or modify it under the terms of the GNU Lesser General              ////
////                                    Public License as published by the Free Software Foundation;            ////
////                                    either version 2.1 of the License, or (at your option) any              ////
////                                    later version.                                                          ////
////                                                                                                                    ////
////                                    This source is distributed in the hope that it will be                  ////
////                                    useful, but WITHOUT ANY WARRANTY; without even the implied              ////
////                                    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR                 ////
////                                    PURPOSE.  See the GNU Lesser General Public License for more            ////
////                                    details.                                                                ////
////                                                                                                                    ////
////                                    You should have received a copy of the GNU Lesser General               ////
////                                    Public License along with this source; if not, download it              ////
////                                    from http://www.opencores.org/lgpl.shtml                                ////
////                                                                                                                    ////
////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module uartTrans (clk, reset, sTick, txDoneTick, din, tx, txStart);
 
                parameter dataBits = `dataBits;
                parameter sbTick = `sbTick;
 
                input [dataBits-1 :0] din;
                input clk, reset, sTick, txStart;
                output tx, txDoneTick;
 
                reg txDoneTick;
 
/*
should be impleneted as a 4-state FSM : idle, start, data, stop;
 
*/
 
        localparam [1:0] idle = 2'b00, start = 2'b01, data = 2'b10, stop = 2'b11;
 
                reg [1:0] stateReg, stateNext;   // current and next states
                reg [3:0] sReg, sNext;           //      counter
                reg [2:0] nReg, nNext;           // counter
                reg [7:0] bReg, bNext;           // perhaps keeps data to be sent
                reg              txReg, txNext; // current bit being transferred
 
 
                //      reset and non-reset conditions:
 
                always @ (posedge clk or posedge reset)
                begin
                        if (reset)
                        begin
                                stateReg <= idle;
                                sReg <= 1'b0;
                                bReg <= 1'b0;
                                nReg <= 1'b0;
                                txReg <= 1'b1;
                        end     // end if
 
                        else
                        begin
                                stateReg <= stateNext;
                                sReg <= sNext;
                                bReg <= bNext;
                                nReg <= nNext;
                                txReg <= txNext;
                        end     // end else
 
                end     // end always
 
                // FSM:
 
                always @ *
                begin
                                stateNext = stateReg;
                                sNext = sReg;
                                bNext = bReg;
                                nNext = nReg;
                                txNext = txReg;
 
                                txDoneTick = 1'b0;              // not done yet!
 
                        case    (stateReg)
 
                                idle    :       begin
                                                                txNext = 1'b1;  // start bit '0'; thus, send '1' in idle
 
                                                                if (txStart)
                                                                begin
                                                                        txDoneTick = 1'b1;      // generate rd for fifo **
                                                                        stateNext = start;      // should go into start state
                                                                        sNext = 0;
                                                                end     // end if txStart
                                                        // in idle state unless txStart...
                                                        end     // end idle case
 
                                start   :       begin
                                                                txNext = 0;
                                                                txDoneTick = 1'b0;              // **
                                                                bNext = din;            // take din into bReg
                                                                if (sTick)
                                                                        if (sReg == 15)
                                                                        begin
                                                                                stateNext = data;
                                                                                sNext = 1'b0;
                                                                                nNext = 1'b0;
                                                                        end     // end if sReg==15
 
                                                                        else
                                                                                sNext = sReg + 1;       // keep incrementing sNext (sReg)
                                                                                // sReg = sNext on each clk edge !!
                                                        end     // end start case
 
                                data    :       begin
                                                                txNext = bReg[0];        // keep sending LSB of bReg
 
                                                                if (sTick)
                                                                        if (sReg == 15)
                                                                        begin
                                                                                sNext = 0;       // reset counter
                                                                                bNext = bReg >> 1;      // shift word to be sent
 
                                                                                if (nReg == (dataBits-1))
                                                                                        stateNext = stop;
                                                                                else
                                                                                        nNext = nReg +1;
                                                                        end     // end if sReg==15
                                                                else
                                                                        sNext = sReg + 1;
 
                                                        end     // end data state
 
                                stop    :       begin
                                                                txNext = 1'b1;
 
                                                                if (sTick)
                                                                        if (sReg == sbTick-1)
                                                                        begin
                                                                                stateNext = idle;
                                                                                //txDoneTick = 1'b1; it's working as read signal to
                                                                                // fifo, so, used at starting . . .
                                                                        end //end if sReg==15
                                                                        else
                                                                                sNext = sReg + 1;
                                                        end     // end stop state
 
                        endcase
 
                end     // end always combinatorial
 
 
                // output bit-stream
 
                assign tx = txReg;
 
endmodule

Line No.	Rev	Author	Line
1	10	maheshpalv	`////////////////////////////////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ////`
4			`//// This file is part of the project ////`
5			`//// "instruction_list_pipelined_processor_with_peripherals" ////`
6			`//// ////`
7			`//// http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals ////`
8			`//// ////`
9			`//// ////`
10			`//// Author: ////`
11			`//// - Mahesh Sukhdeo Palve ////`
12			`//// ////`
13			`////////////////////////////////////////////////////////////////////////////////////////////////`
14			`////////////////////////////////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`////////////////////////////////////////////////////////////////////////////////////////////////`
40	3	maheshpalv
41			`include "timescale.v"
42			`include "defines.v"
43
44
45			`module uartTrans (clk, reset, sTick, txDoneTick, din, tx, txStart);`
46
47			parameter dataBits = `dataBits;
48			parameter sbTick = `sbTick;
49
50			`input [dataBits-1 :0] din;`
51			`input clk, reset, sTick, txStart;`
52			`output tx, txDoneTick;`
53
54			`reg txDoneTick;`
55
56			`/*`
57			`should be impleneted as a 4-state FSM : idle, start, data, stop;`
58
59			`*/`
60
61			`localparam [1:0] idle = 2'b00, start = 2'b01, data = 2'b10, stop = 2'b11;`
62
63			`reg [1:0] stateReg, stateNext; // current and next states`
64			`reg [3:0] sReg, sNext; // counter`
65			`reg [2:0] nReg, nNext; // counter`
66			`reg [7:0] bReg, bNext; // perhaps keeps data to be sent`
67			`reg txReg, txNext; // current bit being transferred`
68
69
70			`// reset and non-reset conditions:`
71
72			`always @ (posedge clk or posedge reset)`
73			`begin`
74			`if (reset)`
75			`begin`
76			`stateReg <= idle;`
77			`sReg <= 1'b0;`
78			`bReg <= 1'b0;`
79			`nReg <= 1'b0;`
80			`txReg <= 1'b1;`
81			`end // end if`
82
83			`else`
84			`begin`
85			`stateReg <= stateNext;`
86			`sReg <= sNext;`
87			`bReg <= bNext;`
88			`nReg <= nNext;`
89			`txReg <= txNext;`
90			`end // end else`
91
92			`end // end always`
93
94			`// FSM:`
95
96			`always @ *`
97			`begin`
98			`stateNext = stateReg;`
99			`sNext = sReg;`
100			`bNext = bReg;`
101			`nNext = nReg;`
102			`txNext = txReg;`
103
104			`txDoneTick = 1'b0; // not done yet!`
105
106			`case (stateReg)`
107
108			`idle : begin`
109			`txNext = 1'b1; // start bit '0'; thus, send '1' in idle`
110
111			`if (txStart)`
112			`begin`
113			`txDoneTick = 1'b1; // generate rd for fifo **`
114			`stateNext = start; // should go into start state`
115			`sNext = 0;`
116			`end // end if txStart`
117			`// in idle state unless txStart...`
118			`end // end idle case`
119
120			`start : begin`
121			`txNext = 0;`
122			`txDoneTick = 1'b0; // **`
123			`bNext = din; // take din into bReg`
124			`if (sTick)`
125			`if (sReg == 15)`
126			`begin`
127			`stateNext = data;`
128			`sNext = 1'b0;`
129			`nNext = 1'b0;`
130			`end // end if sReg==15`
131
132			`else`
133			`sNext = sReg + 1; // keep incrementing sNext (sReg)`
134			`// sReg = sNext on each clk edge !!`
135			`end // end start case`
136
137			`data : begin`
138			`txNext = bReg[0]; // keep sending LSB of bReg`
139
140			`if (sTick)`
141			`if (sReg == 15)`
142			`begin`
143			`sNext = 0; // reset counter`
144			`bNext = bReg >> 1; // shift word to be sent`
145
146			`if (nReg == (dataBits-1))`
147			`stateNext = stop;`
148			`else`
149			`nNext = nReg +1;`
150			`end // end if sReg==15`
151			`else`
152			`sNext = sReg + 1;`
153
154			`end // end data state`
155
156			`stop : begin`
157			`txNext = 1'b1;`
158
159			`if (sTick)`
160			`if (sReg == sbTick-1)`
161			`begin`
162			`stateNext = idle;`
163			`//txDoneTick = 1'b1; it's working as read signal to`
164			`// fifo, so, used at starting . . .`
165			`end //end if sReg==15`
166			`else`
167			`sNext = sReg + 1;`
168			`end // end stop state`
169
170			`endcase`
171
172			`end // end always combinatorial`
173
174
175			`// output bit-stream`
176
177			`assign tx = txReg;`
178
179			`endmodule`

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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [uartTrans.v] - Blame information for rev 10