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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [program_rom/] [romCreate.plx] - Blame information for rev 10

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# programmer for 8-bit pipelined processor
# Mahesh Sukhdeo Palve
# 09042014
# !/usr/bin/perl
use warnings;
# use strict;
 
my $file_asm = '> C:\asm.txt';
open FILE_ASM, $file_asm or die " PROBLEM READING FILE : $! \n";
 
 
my $file_rom = '> C:\rom.v';
open FILE_V, $file_rom or die "PROBLEM READING FILE : $! \n";
 
 
print ("\n\nLast modified by : Mahesh Sukhdeo Palve");
print (" \n\n8-bit Pipeline Processor");
print (" \n\n for Open Cores (opencores.org)");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n\t\tPROGRAMMER . . .\n\n");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
print ("\n\n------------------------------------------------");
 
print ("\nStart entering instructions-\n");
 
#       take instruction?
 
my $inst = 0;
my $addr = 0;
 
 
                        print FILE_V "`include \"defines.v\"\n`include \"timescale.v\"\n\n";
                        print FILE_V "\tmodule\trom (clk, addr, code);\n";
                        print FILE_V "\t\tinput clk;\n\t\tinput [`instAddrLen-1:0] addr; \n\t\t output [`instLen-1:0] code;\n\n";
                        print FILE_V "\t\treg [`instLen-1:0] code;";
                        print FILE_V "\n\n\n\t\t\talways @ (posedge clk)\n\t\t\tbegin\n\n";
                        print FILE_V "\t\t\t case (addr)";
 
 
while ($inst ne END)
{
        print "\nmnemonic :\t";
        $inst = ;
        chop ($inst);
 
 
        my $opcode = getOpcode($inst);
        # print "\nopcode for $inst is $opcode\n";
 
        my $field = getField($inst);
        # print "\nfield for $inst is $field\n";
 
        my $instruction = $opcode.$field;
        print "\n The instruction at address $addr is $instruction\n\n";
 
        my $zero = 0;
 
        print FILE_ASM $inst."\t\t".$field."\n";
 
        print FILE_V "\n\t\t\t\t$addr\t:\tcode = 15'b$instruction;";
 
        $addr = $addr + 1;
}
 
        print FILE_V "\n\n\t\t\tdefault\t:\tcode = 15'b111111111111111;";
        print FILE_V "\n\t\tendcase\nend\n\nendmodule\n";
 
 
 
 
 
##############
# getOpcode
 
sub getOpcode{
 
my $temp;
my $zero = 0;
my $opcod;
use Switch;
 
switch ($inst) {
 
                        case END                { $temp = 0;            $opcod = $temp.$temp.$temp.$temp.$temp;};
                        case JMP                { $temp = 1;            $opcod = $zero.$zero.$zero.$zero.$temp;};
                        case Ld                 { $temp = 10;           $opcod = $zero.$zero.$zero.$temp;};
                        case Ldi                { $temp = 11;           $opcod = $zero.$zero.$zero.$temp;};
                        case ST                 { $temp = 100;          $opcod = $zero.$zero.$temp;};
                        case ADD                { $temp = 101;          $opcod = $zero.$zero.$temp;};
                        case SUB                { $temp = 110;          $opcod = $zero.$zero.$temp;};
                        case MUL                { $temp = 111;          $opcod = $zero.$zero.$temp;};
                        case DIV                { $temp = 1000;         $opcod = $zero.$temp;};
                        case AND                { $temp = 1001;         $opcod = $zero.$temp;};
                        case OR                 { $temp = 1010;         $opcod = $zero.$temp;};
                        case XOR                { $temp = 1011;         $opcod = $zero.$temp;};
                        case GT                 { $temp = 1100;         $opcod = $zero.$temp;};
                        case GE                 { $temp = 1101;         $opcod = $zero.$temp;};
                        case EQ                 { $temp = 1110;         $opcod = $zero.$temp;};
                        case LE                 { $temp = 1111;         $opcod = $zero.$temp;};
                        case LT                 { $opcod = 10000;};
                        case PRE                { $opcod = 10001;};
                        case ETY                { $opcod = 10010;};
                        case RST                { $opcod = 10011;};
                        case LdTC               { $opcod = 10100;};
                        case LdACC              { $opcod = 10101;};
                        case UARTrd             { $opcod = 10110;};
                        case UARTwr             { $opcod = 10111;};
                        case UARTstat   { $opcod = 11000;};
                        case SPIxFER    { $opcod = 11001;};
                        case SPIstat    { $opcod = 11010;};
                        case SPIwBUF    { $opcod = 11011;};
                        case SPIrBUF    { $opcod = 11100;}
                        else                    {print " Inserted NOP!";        $opcod = 11111;};
                }
 
        return $opcod;
 
}
 
 
 
##################
#       getField
 
sub getField{
 
my $fld = 0;
use Switch;
my $zero = 0;
my $tmp;
my $response = 0;
 
my $negate = 0;
my $iomem = 0;
my $iomemaddr = 0;
 
        switch ($inst){
 
 
                case END{
                                        print "\nis start address 0? Y or N\t";
                                        $response = ;   chop($response);
                                        if ($response eq Y){
                                                $tmp = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                                }
                                        else{
                                                print "\nstart address (10 bit) :\t";
                                                $tmp = ;
                                                chop($tmp);
                                                }
                                        $fld = $tmp;
                                        };
 
                case JMP {
                                        print "\n Jump to address :\t";
                                        $fld = ;
                                        chop($fld);
                                        };
 
                case Ld {
                                $fld = sub1();
                                };
 
 
                case Ldi        {
                                        print "\nImmediate Data (8-bit):\t";
                                        $temp = ;       chop($temp);
                                        $fld = $zero.$zero.$temp;
                                        }
 
                case ST         {
                                $fld = sub1();
                                };
                case ADD        {
                                $fld = sub1();
                                };
                case SUB        {
                                $fld = sub1();
                                };
                case MUL        {
                                $fld = sub1();
                                };
                case DIV        {
                                $fld = sub1();
                                };
                case AND        {
                                $fld = sub1();
                                };
                case OR         {
                                $fld = sub1();
                                };
                case XOR        {
                                $fld = sub1();
                                };
                case GT         {
                                $fld = sub1();
                                };
                case GE         {
                                $fld = sub1();
                                };
                case EQ         {
                                $fld = sub1();
                                };
                case LE         {
                                $fld = sub1();
                                };
                case LT         {
                                $fld = sub1();
                                };
 
 
                case PRE        {
                                                my $addr = sub2(); my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
                                };
                case ETY        {
                                                print "\nAssert (1) or De-assert (0) enable signal?\t";
                                                my $resp = ;            chop($resp);
                                                print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t";
                                                my $resp2 = ;   chop($resp2);
                                                my $addr = sub2();              my $zero = 0;
 
                                                $fld = $zero.$zero.$zero.$resp.$resp2.$addr;
                                };
                case RST        {
                                                print "\nAssert (1) or De-assert (0) Reset signal?\t";
                                                my $resp = ;            chop($resp);
                                                my $zero = 0;
                                                my $addr = sub2();
                                                $fld = $zero.$zero.$zero.$zero.$zero.$resp.$addr;
                                };
                case LdTC       {
                                                my $addr = sub2();              my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
                                };
                case LdACC      {
                                                my $addr = sub2();              my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;
                                };
 
                case UARTrd     {
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                };
                case UARTwr     {
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                };
                case UARTstat{
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                };
 
                case SPIxFER{
                                                print "\nEnable (1) or disable (0)?\t";
                                                my $resp = ;            chop($resp);
                                                print "\nShift (1) or Stop shift (0)?\t";
                                                my $resp2 = ;           chop($resp2);
                                                my $zero = 0;
 
                                                $fld = $zero.$zero.$resp.$zero.$zero.$zero.$zero.$zero.$zero.$resp2;
                                }
                case SPIstat{
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                };
                case SPIrBUF{
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                };
                case SPIwBUF{
                                                my $zero = 0;
                                                $fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;
                                }
 
                else    {
                                $fld = 1111111111;
                                };
 
                }
 
        return $fld;
 
}
 
 
sub     sub1{
                                        print "\nNegate? Y or N\t";
                                        $response = ;   chop($response);
                                        if ($response eq Y){    $negate = 1;}
                                        else {$negate = 0};
 
                                        print "\nInput (i) / Output (o) / bitRAM (b) / ByteRAM (B)?";
                                        my $select = ;  chop($select);
                                        if ($select eq i){
                                                                                my $zero = 0;   $iomem = $zero.$zero;
                                                                                print "\ninput address :\t";
                                                                                $iomemaddr = ;  chop($iomemaddr);
                                                                                }
                                        if ($select eq o){
                                                                                $temp = 1;      $zero = 0;
                                                                                $iomem = $zero.$temp;
                                                                                print "\noutput address :\t";
                                                                                $iomemaddr = ;  chop($iomemaddr);
                                                                                }
                                        if ($select eq b){
                                                                                $iomem = 10;
                                                                                print "\nbit RAM address :\t";
                                                                                $iomemaddr = ;  chop($iomemaddr);
                                                                                }
                                        if ($select eq B){
                                                                                $iomem = 11;
                                                                                print "\nByte RAM address :\t";
                                                                                $iomemaddr = ;  chop($iomemaddr);
                                                                                }
                                        $fld = $negate.$iomem.$iomemaddr;
                                        return $fld;
}
 
 
 
sub sub2 {
 
                                print "\nEnter Timer/Counter Address (4-bit):\t";
                                my $addrs = ;
                                chop ($addrs);
                                return $addrs;
}

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Subversion Repositories instruction_list_pipelined_processor_with_peripherals

[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [program_rom/] [romCreate.plx] - Blame information for rev 10

Line No.	Rev	Author	Line
1	9	maheshpalv	`# programmer for 8-bit pipelined processor`
2			`# Mahesh Sukhdeo Palve`
3			`# 09042014`
4			`# !/usr/bin/perl`
5			`use warnings;`
6			`# use strict;`
7
8			`my $file_asm = '> C:\asm.txt';`
9			`open FILE_ASM, $file_asm or die " PROBLEM READING FILE : $! \n";`
10
11
12			`my $file_rom = '> C:\rom.v';`
13			`open FILE_V, $file_rom or die "PROBLEM READING FILE : $! \n";`
14
15
16			`print ("\n\nLast modified by : Mahesh Sukhdeo Palve");`
17			`print (" \n\n8-bit Pipeline Processor");`
18			`print (" \n\n for Open Cores (opencores.org)");`
19			`print ("\n\n------------------------------------------------");`
20			`print ("\n\n------------------------------------------------");`
21			`print ("\n\n------------------------------------------------");`
22			`print ("\n\n\t\tPROGRAMMER . . .\n\n");`
23			`print ("\n\n------------------------------------------------");`
24			`print ("\n\n------------------------------------------------");`
25			`print ("\n\n------------------------------------------------");`
26
27			`print ("\nStart entering instructions-\n");`
28
29			`# take instruction?`
30
31			`my $inst = 0;`
32			`my $addr = 0;`
33
34
35			print FILE_V "`include \"defines.v\"\n`include \"timescale.v\"\n\n";
36			`print FILE_V "\tmodule\trom (clk, addr, code);\n";`
37			print FILE_V "\t\tinput clk;\n\t\tinput [`instAddrLen-1:0] addr; \n\t\t output [`instLen-1:0] code;\n\n";
38			print FILE_V "\t\treg [`instLen-1:0] code;";
39			`print FILE_V "\n\n\n\t\t\talways @ (posedge clk)\n\t\t\tbegin\n\n";`
40			`print FILE_V "\t\t\t case (addr)";`
41
42
43			`while ($inst ne END)`
44			`{`
45			`print "\nmnemonic :\t";`
46			`$inst = ;`
47			`chop ($inst);`
48
49
50			`my $opcode = getOpcode($inst);`
51			`# print "\nopcode for $inst is $opcode\n";`
52
53			`my $field = getField($inst);`
54			`# print "\nfield for $inst is $field\n";`
55
56			`my $instruction = $opcode.$field;`
57			`print "\n The instruction at address $addr is $instruction\n\n";`
58
59			`my $zero = 0;`
60
61			`print FILE_ASM $inst."\t\t".$field."\n";`
62
63			`print FILE_V "\n\t\t\t\t$addr\t:\tcode = 15'b$instruction;";`
64
65			`$addr = $addr + 1;`
66			`}`
67
68			`print FILE_V "\n\n\t\t\tdefault\t:\tcode = 15'b111111111111111;";`
69			`print FILE_V "\n\t\tendcase\nend\n\nendmodule\n";`
70
71
72
73
74
75			`##############`
76			`# getOpcode`
77
78			`sub getOpcode{`
79
80			`my $temp;`
81			`my $zero = 0;`
82			`my $opcod;`
83			`use Switch;`
84
85			`switch ($inst) {`
86
87			`case END { $temp = 0; $opcod = $temp.$temp.$temp.$temp.$temp;};`
88			`case JMP { $temp = 1; $opcod = $zero.$zero.$zero.$zero.$temp;};`
89			`case Ld { $temp = 10; $opcod = $zero.$zero.$zero.$temp;};`
90			`case Ldi { $temp = 11; $opcod = $zero.$zero.$zero.$temp;};`
91			`case ST { $temp = 100; $opcod = $zero.$zero.$temp;};`
92			`case ADD { $temp = 101; $opcod = $zero.$zero.$temp;};`
93			`case SUB { $temp = 110; $opcod = $zero.$zero.$temp;};`
94			`case MUL { $temp = 111; $opcod = $zero.$zero.$temp;};`
95			`case DIV { $temp = 1000; $opcod = $zero.$temp;};`
96			`case AND { $temp = 1001; $opcod = $zero.$temp;};`
97			`case OR { $temp = 1010; $opcod = $zero.$temp;};`
98			`case XOR { $temp = 1011; $opcod = $zero.$temp;};`
99			`case GT { $temp = 1100; $opcod = $zero.$temp;};`
100			`case GE { $temp = 1101; $opcod = $zero.$temp;};`
101			`case EQ { $temp = 1110; $opcod = $zero.$temp;};`
102			`case LE { $temp = 1111; $opcod = $zero.$temp;};`
103			`case LT { $opcod = 10000;};`
104			`case PRE { $opcod = 10001;};`
105			`case ETY { $opcod = 10010;};`
106			`case RST { $opcod = 10011;};`
107			`case LdTC { $opcod = 10100;};`
108			`case LdACC { $opcod = 10101;};`
109			`case UARTrd { $opcod = 10110;};`
110			`case UARTwr { $opcod = 10111;};`
111			`case UARTstat { $opcod = 11000;};`
112			`case SPIxFER { $opcod = 11001;};`
113			`case SPIstat { $opcod = 11010;};`
114			`case SPIwBUF { $opcod = 11011;};`
115			`case SPIrBUF { $opcod = 11100;}`
116			`else {print " Inserted NOP!"; $opcod = 11111;};`
117			`}`
118
119			`return $opcod;`
120
121			`}`
122
123
124
125			`##################`
126			`# getField`
127
128			`sub getField{`
129
130			`my $fld = 0;`
131			`use Switch;`
132			`my $zero = 0;`
133			`my $tmp;`
134			`my $response = 0;`
135
136			`my $negate = 0;`
137			`my $iomem = 0;`
138			`my $iomemaddr = 0;`
139
140			`switch ($inst){`
141
142
143			`case END{`
144			`print "\nis start address 0? Y or N\t";`
145			`$response = ; chop($response);`
146			`if ($response eq Y){`
147			`$tmp = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
148			`}`
149			`else{`
150			`print "\nstart address (10 bit) :\t";`
151			`$tmp = ;`
152			`chop($tmp);`
153			`}`
154			`$fld = $tmp;`
155			`};`
156
157			`case JMP {`
158			`print "\n Jump to address :\t";`
159			`$fld = ;`
160			`chop($fld);`
161			`};`
162
163			`case Ld {`
164			`$fld = sub1();`
165			`};`
166
167
168			`case Ldi {`
169			`print "\nImmediate Data (8-bit):\t";`
170			`$temp = ; chop($temp);`
171			`$fld = $zero.$zero.$temp;`
172			`}`
173
174			`case ST {`
175			`$fld = sub1();`
176			`};`
177			`case ADD {`
178			`$fld = sub1();`
179			`};`
180			`case SUB {`
181			`$fld = sub1();`
182			`};`
183			`case MUL {`
184			`$fld = sub1();`
185			`};`
186			`case DIV {`
187			`$fld = sub1();`
188			`};`
189			`case AND {`
190			`$fld = sub1();`
191			`};`
192			`case OR {`
193			`$fld = sub1();`
194			`};`
195			`case XOR {`
196			`$fld = sub1();`
197			`};`
198			`case GT {`
199			`$fld = sub1();`
200			`};`
201			`case GE {`
202			`$fld = sub1();`
203			`};`
204			`case EQ {`
205			`$fld = sub1();`
206			`};`
207			`case LE {`
208			`$fld = sub1();`
209			`};`
210			`case LT {`
211			`$fld = sub1();`
212			`};`
213
214
215			`case PRE {`
216			`my $addr = sub2(); my $zero = 0;`
217			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;`
218			`};`
219			`case ETY {`
220			`print "\nAssert (1) or De-assert (0) enable signal?\t";`
221			`my $resp = ; chop($resp);`
222			`print "\nTimer or Counter Type :\t 00 = on-delayTimer, 01 = off-delayTimer, 10 = retOn-delayTimer\n\t\t\t01 = up-counter, 10 = down-counter\n\t\t";`
223			`my $resp2 = ; chop($resp2);`
224			`my $addr = sub2(); my $zero = 0;`
225
226			`$fld = $zero.$zero.$zero.$resp.$resp2.$addr;`
227			`};`
228			`case RST {`
229			`print "\nAssert (1) or De-assert (0) Reset signal?\t";`
230			`my $resp = ; chop($resp);`
231			`my $zero = 0;`
232			`my $addr = sub2();`
233			`$fld = $zero.$zero.$zero.$zero.$zero.$resp.$addr;`
234			`};`
235			`case LdTC {`
236			`my $addr = sub2(); my $zero = 0;`
237			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;`
238			`};`
239			`case LdACC {`
240			`my $addr = sub2(); my $zero = 0;`
241			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$addr;`
242			`};`
243
244			`case UARTrd {`
245			`my $zero = 0;`
246			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
247			`};`
248			`case UARTwr {`
249			`my $zero = 0;`
250			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
251			`};`
252			`case UARTstat{`
253			`my $zero = 0;`
254			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
255			`};`
256
257			`case SPIxFER{`
258			`print "\nEnable (1) or disable (0)?\t";`
259			`my $resp = ; chop($resp);`
260			`print "\nShift (1) or Stop shift (0)?\t";`
261			`my $resp2 = ; chop($resp2);`
262			`my $zero = 0;`
263
264			`$fld = $zero.$zero.$resp.$zero.$zero.$zero.$zero.$zero.$zero.$resp2;`
265			`}`
266			`case SPIstat{`
267			`my $zero = 0;`
268			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
269			`};`
270			`case SPIrBUF{`
271			`my $zero = 0;`
272			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
273			`};`
274			`case SPIwBUF{`
275			`my $zero = 0;`
276			`$fld = $zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero.$zero;`
277			`}`
278
279			`else {`
280			`$fld = 1111111111;`
281			`};`
282
283			`}`
284
285			`return $fld;`
286
287			`}`
288
289
290			`sub sub1{`
291			`print "\nNegate? Y or N\t";`
292			`$response = ; chop($response);`
293			`if ($response eq Y){ $negate = 1;}`
294			`else {$negate = 0};`
295
296			`print "\nInput (i) / Output (o) / bitRAM (b) / ByteRAM (B)?";`
297			`my $select = ; chop($select);`
298			`if ($select eq i){`
299			`my $zero = 0; $iomem = $zero.$zero;`
300			`print "\ninput address :\t";`
301			`$iomemaddr = ; chop($iomemaddr);`
302			`}`
303			`if ($select eq o){`
304			`$temp = 1; $zero = 0;`
305			`$iomem = $zero.$temp;`
306			`print "\noutput address :\t";`
307			`$iomemaddr = ; chop($iomemaddr);`
308			`}`
309			`if ($select eq b){`
310			`$iomem = 10;`
311			`print "\nbit RAM address :\t";`
312			`$iomemaddr = ; chop($iomemaddr);`
313			`}`
314			`if ($select eq B){`
315			`$iomem = 11;`
316			`print "\nByte RAM address :\t";`
317			`$iomemaddr = ; chop($iomemaddr);`
318			`}`
319			`$fld = $negate.$iomem.$iomemaddr;`
320			`return $fld;`
321			`}`
322
323
324
325			`sub sub2 {`
326
327			`print "\nEnter Timer/Counter Address (4-bit):\t";`
328			`my $addrs = ;`
329			`chop ($addrs);`
330			`return $addrs;`
331			`}`