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# Integer Square Root
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## Algorithm
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```
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procedure ISR(value)
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        for i<-31 to 0 do
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                proposed_solution[i]<-1
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                if proposed_solution^2 > value then
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                        proposed_solution[i]<-0
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                end if
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        end for
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end procedure
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```
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## Specification
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- If reset is asserted during a rising clock edge (synchronous reset), the value signal is to be stored.
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- If reset is asserted part way through a computation, the result of that computation is discarded and a new value is latched into the module.
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- When the module has finished computing the answer, the output is placed on the result line and done line is raised on the same cycle.
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- It must not take more than 600 clock cycles to compute a result (from the last
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  clock that reset is asserted to the first clock that done is asserted.)
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## ISR State Machine
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Computing: $\sqrt{\mathtt{value}}$
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- On a reset
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  - guess initialized to `32'h8000_0000`
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  - `value` is clocked into a register
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- guess gets the next bit set each time we cycle through the FSM again
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- Square `guess` (multiply it with itself)
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  - Wait until the multiplier raises its done
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- if `guess` <= `value`
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  - Keep the current bit
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- else
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  - Clear the current bit
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- Move to the next bit
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- After the last bit, raise `done`

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