Subversion Repositories integer_square_root

`define HALF_CYCLE 1000

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer: Yihua Liu

//

// Create Date: 2022/06/08 16:51:12

// Design Name:

// Module Name: testbench

// Project Name: lab_3_b

// Target Devices: xczu7eg-ffvf1517-2-i

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module testbench();

        logic [63:0] value;

        logic clock, reset;

        logic [31:0] result;

        logic done;

    logic [31:0] cres;

        wire correct = (cres===result)|~done|reset;

        integer value_test, j;

        time start_time = $time, finish_time;

    task ISR_test;

        input [63:0] value;

        output [31:0] cres;

                cres = 0;

        for (integer i = 31; i >= 0; i--) begin

                        cres[i] = 1;

                        if (cres * cres > value)

                            cres[i] = 0;

        end

    endtask

    ISR isr(

        .reset(reset),

        .value(value),

        .clock(clock),

        .result(result),

        .done(done)

    );

        always @(posedge clock)

                #2 if(!correct) begin

                        $display("Incorrect at time %4.0f",$time);

                        $display("cres = %h result = %h",cres,result);

                        $display("@@@Failed");

                        $finish;

                end

        always begin

                #`HALF_CYCLE;

                clock=~clock;

        end

        task wait_until_done;

                forever begin : wait_loop

                        @(posedge done);

                        @(negedge clock);

                        if(done) begin

                                finish_time = $time;

                                $display("Done one calculation of ISR");

                            // Calculate the total number of cycles you need to do one calculation of ISR

                            // Note that in this way the additional cycles added during simulation will be counted

                            // So the displayed value may be 1 to 3 cycles more than 600 cycles

                                $display("Number of cycles needed: %d", (finish_time - start_time) / (2 * `HALF_CYCLE));

                                start_time = finish_time;

                                disable wait_until_done;

                        end

                end

        endtask

        initial begin

                $monitor("Time:%4.0f done:%b cres:%h result:%h reset:%h",$time,done,cres,result,reset);

                // Test 1

                value = 0;  // square number

                reset = 1;

                clock = 0;

                ISR_test(value, cres);

                #2000;

                @(negedge clock);

                reset = 0;

                wait_until_done();

                @(negedge clock);

                // Test 2

        reset = 1;

                value = 4;  // square number

                ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                @(negedge clock);

                // Test 3

                reset = 1;

                value = 121;  // square number

                ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                @(negedge clock);

                // Test 4

        reset = 1;

                value = 1000000;  // square number

        ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                // Test 5

                reset = 1;

                value = 130;  // non square number

        ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                // Test 6

                @(negedge clock);

                reset = 1;

                value = 2;  // non square number (value to be discarded)

        ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                @(negedge clock);

                @(negedge clock);

                @(negedge clock);

                reset = 1;  // reset is asserted part way through a computation

                value = 3;  // non square number (new value to be latched into)

        ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                @(negedge clock);

                @(negedge clock);

                // Test 7

                reset = 1;

                value = 64'h7FFF_FFFF_FFFF_FFFF;

        ISR_test(value, cres);

                @(negedge clock);

                reset = 0;

                wait_until_done();

                @(negedge clock);

                value_test = 64'hFFFF_FFFF_FFFF_FFFF;

                // Short loops

                for (j = 0; j < 100; j++) begin

                        reset = 1;

                        value = value_test;

            ISR_test(value, cres);

                        @(negedge clock);

                        reset = 0;

                        wait_until_done();

                        value_test = value_test - 64'h0000_0000_7FFF_FFFF;

                end

                // Random testing

                for (j = 0; j < 1000; j++) begin

                        reset = 1;

                        value = {$random, $random};

            ISR_test(value, cres);

                        @(negedge clock);

                        reset = 0;

                        wait_until_done();

                end

                $display("@@@Passed");

                $finish;

        end

endmodule