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[/] [interrupt_controller/] [trunk/] [rtl/] [int_contr.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Bjarneorn 
`timescale 1ns / 1ps
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module interrupt_controller( clk,
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                             reset,
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                                                                          cs,
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                                                                          adr,
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                                                                          oe,
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                                                                          we,
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                                                                          data_i,
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                                                                          data_o,
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                                                                          int1,
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                             int2,
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                                                                          int3,
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                                                                          int4,
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                                                                          int5,
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                                                                          int6,
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                                                                          int7,
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                                                                          ack,
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                                                                          dtack,
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                                                                          ipl
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                            );
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input  clk;
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input  reset;
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input  cs;
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input  [3:0] adr;
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input  oe;
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input  we;
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input  [7:0] data_i;
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output [7:0] data_o;
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input  int1, int2, int3, int4, int5, int6, int7;
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input  ack;
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output dtack;
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output [2:0] ipl;
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reg dtack = 1'b0;
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reg ack_r = 1'b0;
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reg [7:0] data_r;
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reg [7:0] vectors [0:6];
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reg [2:0] irq_nr [0:6];
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reg [6:0] int_mask;
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reg [6:0] int_pending;
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reg [6:0] ie_reg;
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reg [2:0] ipl_r, ipl_n;
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wire [2:0] int_no = (6 - ipl_r);
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wire assert_ack   = (ack && ~ack_r);
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wire deassert_ack = (ack_r && ~ack);
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wire [2:0] ix = adr[2:0];
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wire vectors_stb_we = (cs && we && adr[3] == 1'b0 && adr[2:0] != 3'b111 );
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wire vectors_stb_oe = (cs && oe && adr[3] == 1'b0 && adr[2:0] != 3'b111 );
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wire irq_stb_we     = (cs && we && adr[3] == 1'b1 && adr[2:0] != 3'b111 );
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wire irq_stb_oe     = (cs && oe && adr[3] == 1'b1 && adr[2:0] != 3'b111 );
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wire ier_stb_we     = (cs && we && adr == 4'b0111);
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wire ier_stb_oe     = (cs && oe && adr == 4'b0111);
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reg int1_r, int2_r, int3_r, int4_r, int5_r, int6_r, int7_r;
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wire int1_on = (int1_r == 1'b0 && int1);
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wire int2_on = (int2_r == 1'b0 && int2);
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wire int3_on = (int3_r == 1'b0 && int3);
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wire int4_on = (int4_r == 1'b0 && int4);
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wire int5_on = (int5_r == 1'b0 && int5);
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wire int6_on = (int6_r == 1'b0 && int6);
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wire int7_on = (int7_r == 1'b0 && int7);
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wire int1_of = (int1_r == 1'b1 && !int1);
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wire int2_of = (int2_r == 1'b1 && !int2);
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wire int3_of = (int3_r == 1'b1 && !int3);
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wire int4_of = (int4_r == 1'b1 && !int4);
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wire int5_of = (int5_r == 1'b1 && !int5);
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wire int6_of = (int6_r == 1'b1 && !int6);
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wire int7_of = (int7_r == 1'b1 && !int7);
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wire pos_edge_trigger = (int1_on || int2_on || int3_on || int4_on || int5_on || int6_on || int7_on );
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wire neg_edge_trigger = (int1_of || int2_of || int3_of || int4_of || int5_of || int6_of || int7_of );
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integer i;
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initial
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begin
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        int_pending = 7'b0000000;
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        int_mask    = 7'b1111111;
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        ie_reg      = 7'b1111111;
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        ipl_r       = 3'b111;
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        dtack       = 1'b1;
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        int1_r      = 1'b0;
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        int2_r      = 1'b0;
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        int3_r      = 1'b0;
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        int4_r      = 1'b0;
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        int5_r      = 1'b0;
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        int6_r      = 1'b0;
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        int7_r      = 1'b0;
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        for(i=0;i<7;i=i+1)
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        begin
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                vectors[i] = 25 + i;
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                irq_nr[i]  = i;
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        end
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end
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always @(posedge clk)
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begin
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        if( reset )
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        begin
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                int1_r <= 1'b0;
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                int2_r <= 1'b0;
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                int3_r <= 1'b0;
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                int4_r <= 1'b0;
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                int5_r <= 1'b0;
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                int6_r <= 1'b0;
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                int7_r <= 1'b0;
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        end else begin
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                int1_r <= int1;
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                int2_r <= int2;
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                int3_r <= int3;
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                int4_r <= int4;
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                int5_r <= int5;
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                int6_r <= int6;
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                int7_r <= int7;
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        end
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end
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always @(posedge clk)
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        if( reset )
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                ack_r <= 1'b0;
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        else
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                ack_r <= ack;
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always @(posedge clk)
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begin
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        if( vectors_stb_we )
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                vectors[ix] = data_i;
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end
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always @(posedge clk)
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begin
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        if( irq_stb_we )
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                irq_nr[ix]  = data_i;
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end
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always @(posedge clk)
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begin
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        if( reset )
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                ie_reg      = 7'b1111111;
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        else if( ier_stb_we )
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                ie_reg      = data_i;
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end
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always @(posedge clk)
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begin
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        dtack = 1'b1;
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        if( ack )
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        begin
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                if( assert_ack )
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                        data_r = vectors[int_no];
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                dtack  = (ipl_r == 3'b111);
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        end else if( cs ) begin
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                if( vectors_stb_oe )
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                        data_r = vectors[ix];
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                else if( irq_stb_oe )
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                        data_r = irq_nr[ix];
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                else if( ier_stb_oe )
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                        data_r = ie_reg;
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                else
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                        data_r = 8'bZ;
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                dtack = 1'b0;
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        end else
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                data_r = 8'bZ;
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end
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always @(posedge clk)
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begin
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        if( reset )
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        begin
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                int_pending = 7'b0000000;
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        end else if( pos_edge_trigger ) begin
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                if(int7 && ie_reg[6])
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                        int_pending[6] = 1;
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                else if(int6 && ie_reg[5])
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                        int_pending[5] = 1;
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                else if(int5 && ie_reg[4])
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                        int_pending[4] = 1;
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                else if(int4 && ie_reg[3])
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                        int_pending[3] = 1;
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                else if(int3 && ie_reg[2])
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                        int_pending[2] = 1;
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                else if(int2 && ie_reg[1])
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                        int_pending[1] = 1;
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                else if(int1 && ie_reg[0])
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                        int_pending[0] = 1;
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        end else if( neg_edge_trigger ) begin
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                if(!int7)
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                        int_pending[6] = 0;
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                if(!int6)
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                        int_pending[5] = 0;
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                if(!int5)
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                        int_pending[4] = 0;
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                if(!int4)
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                        int_pending[3] = 0;
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                if(!int3)
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                        int_pending[2] = 0;
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                if(!int2)
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                        int_pending[1] = 0;
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                if(!int1)
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                        int_pending[0] = 0;
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        end
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end
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always @(posedge clk)
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begin
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        if( deassert_ack || reset )
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        begin
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                ipl_r  = 3'b111;
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        end else if( ipl_r == 3'b111 ) begin
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                if( int_pending[6] && int_mask[6] )
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                        ipl_r     = ~irq_nr[6];
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                else if( int_pending[5] && int_mask[5] )
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                        ipl_r     = ~irq_nr[5];
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                else if( int_pending[4] && int_mask[4] )
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                        ipl_r     = ~irq_nr[4];
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                else if( int_pending[3] && int_mask[3] )
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                        ipl_r     = ~irq_nr[3];
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                else if( int_pending[2] && int_mask[2] )
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                        ipl_r     = ~irq_nr[2];
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                else if( int_pending[1] && int_mask[1] )
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                        ipl_r     = ~irq_nr[1];
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                else if( int_pending[0] && int_mask[0] )
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                        ipl_r     = ~irq_nr[0];
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        end
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end
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always @(posedge clk)
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begin
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        if( reset )
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                int_mask = 7'b1111111;
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        else if ( !pos_edge_trigger && !neg_edge_trigger )
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                casex(int_pending)
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                        7'b1xxxxxx: int_mask = 7'b0000000;
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                        7'b01xxxxx: int_mask = 7'b1000000;
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                        7'b001xxxx: int_mask = 7'b1100000;
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                        7'b0001xxx: int_mask = 7'b1110000;
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                        7'b00001xx: int_mask = 7'b1111000;
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                        7'b000001x: int_mask = 7'b1111100;
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                        7'b0000001: int_mask = 7'b1111110;
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                        7'b0000000: int_mask = 7'b1111111;
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                endcase
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end
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assign data_o = data_r;
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assign ipl = ipl_r;
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endmodule

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