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ja_rd |
\clearpage
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This file contains usage instructions and notes about the Ion CPU core project.
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The core structure is briefly explained in sections 1 to 4. The rest of this
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doc describes other aspects of the project: code samples, utility scripts,
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etc.\\
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This document is not yet a full reference on the Ion core. Instead, it should be
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taken as a companion and commentary to the source code.\\
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This document assumes you know in some depth the MIPS-I architecture. Terms and
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concepts from \cite['See MIPS Run']{see_mips_run} and
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\cite['IDT R3K Reference Manual']{r3k_ref_man} are used throughout the text.\\
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Last modified: \today
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\clearpage
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\chapter{Introduction}
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\section{Features}
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\label{features}
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This is a MIPS-I compatible CPU, aiming at compatibility with IDT's R3000
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MIPS derivative:\\
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\begin{framed}
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\subsection{Key features}
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\begin{enumerate}
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\item Binary compatible to R3000 series of CPUs.\\
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Can use regular R3000 toolchains despite a few unimplemented opcodes
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listed below.
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\item Kernel/user mode operation as per the architecture definition.
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\item Exception handling compatible to MIPS-I standard.
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\item 4KB direct-mapped code cache.
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\item 4KB direct-mapped, writethrough data cache.
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\item Simplified CP0, mostly compatible to R3000.
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\item All unimplemented opcodes trigger the proper traps.
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\item Includes minimalistic memory handler with interfaces for external
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SRAM (or FLASH) on 8- and 16-bit data bus.
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\item Size and speed compares favorably to other free MIPS cores.
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\item Fully sinchronous (rising clock edge only). No latches.
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\item Source HDL is vendor independent (Though it has only been tested on
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Xilinx and Altera synthesis tools).
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\end{enumerate}
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\end{framed}
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The implementation departs from the standard R3000 in some points:
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\begin{framed}
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\subsection{Non-standard features}
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\begin{enumerate}
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\item No MMU and no TLB -- meaning no memory address translation at all.
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\item Cache management simplified in an incompatible way.
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\item A number of R3000 opcodes are unimplemented or implemented in an
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incompatible way:\\
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Unaligned load/store instructions (formerly patented).\\
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All CPA instructions.\\
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All CP0 instructions related to TLB and the cache.
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\item Some other R3000 CP0 features have been omitted.\\
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This includes the CP0 timer.
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\item Interrupt mask handling simplified in an incompatible way.
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\end{enumerate}
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\end{framed}
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Finally, there are some flaws and missing features meant to be fixed in
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subsequent versions:
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\begin{framed}
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\subsection{Missing features to be implemented eventually}
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\begin{enumerate}
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\item Hardware interrupts not implemented.
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\item Memory handler does not support dynamic RAM.
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\item Caches are not configurable or parametrizable.
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\item Documentation is disastrously inadequate.
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\end{enumerate}
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\end{framed}
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