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\chapter{Usage}
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\section{Main Modules}
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\label{main_modules}
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The core is split in three main modules:
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\begin{enumerate}
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\item The CPU (mips\_cpu.vhdl).
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\item The cache+memory controller (mips\_cache.vhdl).
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\item An 'MCU' entity which combines CPU+Cache (mips\_mpu.vhdl).
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\end{enumerate}
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The entity you should use in your projects is the MCU module. The project
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includes a 'hardware demo' built around this module (see section
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~\ref{pregenerated_demo}) which can be used as an usage example.\\
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The main modules are briefly described in the following subsections.
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\section{MCU Module}
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\label{mcu_module}
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The MCU module main purpose is to encapsulate the somewhat complex
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interconnection between the CPU and the Cache module.
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If some project demands that some piece of hardware be directly connected to the
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CPU, bypassing the cache, this is where it should be -- an MMU comes to mind.
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Any peripherals deemed common enough that they will be present in all projects
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might be placed in the MCU module too -- after all, the MCU name has been chosen
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to imply that 'bundling together' of a CPU and a bunch of peripherals.
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In the current version of the MCU module, there is only a peripheral included in
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it -- a hardwired UART module. There is no penalty for placing peripherals
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ouside the MCU module, so there is no incentive to place them inside, thus
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making the interface more complex. This is an implementation option of yours.\\
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\subsection{MCU Ports}
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\label{mcu_ports}
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\begin{figure}[h]
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\makebox[\textwidth]{\framebox[9cm]{\rule{0pt}{9cm}
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\includegraphics[width=8cm]{img/mpu_symbol.png}}}
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\caption{MPU module interface\label{mpu_symbol}}
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\end{figure}
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\begin{table}[h]
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\caption{MCU module interface ports}
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\begin{tabularx}{\textwidth}{ lll|X }
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\toprule
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Name & Type & Width & Description \\
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\midrule
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clk & in & 1 & Clock input, active rising edge. \\
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reset & in & 1 & Synchronous global reset. \\
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\midrule
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sram\_address & out & 16 & Memory word address (bit 0 absent). \\
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sram\_data\_wr & out & 16 & Memory write data. Only valid when one of the \\
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& & & memory byte write enable outputs is active.\\
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sram\_data\_rd & in & 16 & Memory read data. Latched when xxx. \\
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sram\_byte\_we\_n & out & 2 & Memory byte write enable, active low. \\
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& & & (0) enables the low byte (7 downto 0) \\
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& & & (1) enables the high byte (15 downto 8). \\
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\midrule
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io\_rd\_addr & out & 30 & I/O port read address (bits 1..0 absent). \\
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& & & Only valid when io\_rd\_vma is high. \\
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io\_wr\_addr & out & 30 & I/O port write address (bits 1..0 absent). \\
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io\_wr\_data & out & 32 & I/O write data. Only valid when one of the \\
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& & & i/o byte write enable outputs is active.\\
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io\_rd\_data & in & 32 & I/O read data. Latched when xxx. \\
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io\_byte\_we & out & 4 & I/O byte write enable, active high. \\
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& & & (0) enables the low byte (7 downto 0) \\
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& & & (3) enables the high byte (31 downto 24). \\
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io\_rd\_vma & out & 1 & Active high on i/o read cycles. \\
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\midrule
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uart\_rxd & in & 1 & RxD input to internal UART. \\
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uart\_txd & out & 1 & TxD output from internal UART. \\
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\midrule
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interrupt & in & 8 & Interrupt request inputs, active high. \\
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\bottomrule
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\end{tabularx}
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\end{table}
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As you can see in figure~\ref{mpu_symbol} (symbol generated by Xilinx ISE),
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the MCU has the following interfaces:
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\begin{enumerate}
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\item Interface to external static asynchronous memory (SRAM, FLASH...).
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\item Interface to on-chip peripherals.
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\item Interrupt inputs.
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\end{enumerate}
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These interfaces will be explained in the following subsections. The top module
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for the demo supplied with the project (c2sb\_demo.vhdl) will be used for
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illustration.
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\emph{NOTE}: This section needs a lot of elaboration -- ideally this should be
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equivalent to
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a datasheet in thoroughness and detail. This work, like many other parts of this
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project, will have to wait.
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\subsection{MCU interface to static memory}
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\label{mcu_if_sram}
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The interface to external memory in the MCU module is essentially that of the
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internal cache/memory controller. Its timing is described in section
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~\ref{cache_state_machine}.\\
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The MCU inputs are meant to be connected straight to the FPGA i/o pins. The only
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trick is the bidirectional memory data bus: as you can see, the MCU data buses
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are unidirectional and thus you will need to provide an interconnection
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external to this module. This interconnection shall include the requisite
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3-state buffers:
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\begin{verbatim}
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sram_databus <= sram_data_wr when sram_byte_we_n/="11" else (others => 'Z');
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\end{verbatim}
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The top level module can be used as a fully tested example of how to use this
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interface to connect to a common SRAM chip (ISSI IS61LV25616).
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In reviewing the top module source, note that I had to adapt the dual
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byte-write-enable outputs to the SRAM
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configuration of a single write-enable plus dual byte-enable inputs.
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Note too that the static memory bus is used to access both the 16-bit wide SRAM
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and an 8-bit wide FLASH. These chips are connected to separate buses on the
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target board, so the top module needs to conflate both buses before connecting
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them to the MPU. This is why a multiplexor is used in the mpu\_sram\_data\_rd
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bus. A real-world board would probably have the SRAM and the FLASH connected
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to the same bus, simplifying the interface logic.
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\subsection{MCU interface to peripherals}
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\label{mcu_if_io}
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TODO Documentation to be done
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\subsection{MCU interrupt inputs}
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\label{mcu_irqs}
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TODO Documentation to be done
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