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Summary of the directories and files in this project.
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./
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================================================================================
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./files.txt This file
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./doc Documentation
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================================================================================
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ion_project.pdf Project documentation (built with LaTeX).
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./doc/src/* LaTeX source files, including images.
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./src C and assembler sources for some tests and demos
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================================================================================
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readme.txt Short usage instructions for the code samples
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bin2hdl.py Python script that builds vhdl tables from bin files
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(no longer used)
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ion_noxram.lds Load script for default bare system configuration
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mips_mpu_template.vhdl Template for mpu system, no longer used.
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mips_tb1_template.vhdl Template for simulation, no longer used.
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mips_tb0_template.vhdl Template for sim. test bench (single memory block)
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mips_tb2_template.vhdl Template for sim. test bench, no longer used.
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./src/common Source files common to all samples
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--------------------------------------------------------------------------------
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makefile Makefile included from all other makefiles.
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bootstrap.s Reset code (cache initialization, etc.)
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opcode_emu.s MIPS-32 opcode emulation (optional).
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c_startup.s C startup code.
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libsoc/ Minimalistic libc replacement.
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./src/opcodes Simple opcode tester for simulation only.
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./src/hello Hello World sample.
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./src/memtest Simple memory tester.
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./src/adventure Adventure classic.
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./vhdl VHDL sources
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================================================================================
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mips_pkg.vhdl Package with declarations common to all modules
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mips_cpu.vhdl Main CPU core module (excludes caches)
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mips_shifter.vhdl Barrel shifter module
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mips_alu.vhdl ALU module
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mips_mult.vhdl Multiplier/divider mudule (from Plasma)
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mips_cache.vhdl Cache + memory controller module.
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mips_cache_stub.vhdl 'Stub', empty cache module, no longer used.
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mips_sdram_controller.vhdl SDRAM controller, yet to be used.
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./vhdl/SoC Source files for ION SoC module
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mips_soc.vhdl SoC built around the ION core.
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uart.vhdl Hardwired UART.
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bootstrap_code_pkg.vhdl Pack. with bootstrap code (dynamically generated).
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./vhdl/tb VHDL source for simulation test bench
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txt_util.vhdl Utility functions for string handling
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mips_tb.vhdl Simulation test bench (see project doc)
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mips_tb_pkg.vhdl Simulation utility package, including logger.
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sim_params_pkg.vhdl Simulation parameters & code (generated dynamically)
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./vhdl/demo Source files for hardware demo on DE-1 board
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c2sb_demo.csv Assignments file to be imported from Altera IDE
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c2sb_demo.vhdl Top level source of demo
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./sim Simulation scripts for Modelsim (tcl)
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================================================================================
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mips_tb.do Runs test bench /vhdl/tb/mips_tb.vhdl
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mips_tb_wave.do Sub-script used to set-up Modelsim's wave window
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./tools Assorted
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================================================================================
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./tools/slite SW simulator, plus CodeBlocks project file.
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./tools/build_pkg Package builder, used in all code samples.
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./syn Simulation and synthesis runtime stuff
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================================================================================
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Simulation scripts are assumed to run from here (see ./sim/readme.txt).
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Besides, here is where I put the synthesis stuff.
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This directory is versioned but contents are not.
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