OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [adventure/] [makefile] - Blame information for rev 182

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 177 ja_rd
#-- Set up the toolchain -------------------------------------------------------
2 90 ja_rd
 
3 177 ja_rd
BIN_MIPS = C:/dev/embedded/SourceryGpp/mips-elf-11-03.52/bin
4
CC = $(BIN_MIPS)/mips-sde-elf-gcc.exe $(CFLAGS)
5
AS = $(BIN_MIPS)/mips-sde-elf-as
6
LD = $(BIN_MIPS)/mips-sde-elf-ld
7
DUMP = $(BIN_MIPS)/mips-sde-elf-objdump
8
COPY = $(BIN_MIPS)/mips-sde-elf-objcopy
9
TO_VHDL   = python ../bin2hdl.py
10 90 ja_rd
 
11 177 ja_rd
 
12
#-- Set up the code structure --------------------------------------------------
13
 
14
# Root test code source directory, where python script and vhdl templates are
15
SRC_DIR = ..
16
# VHDL test bench directory, where VHDL output files will be created
17
TB_DIR = ../../vhdl/tb
18
# VHDL DE-1 board demo root directory, for vhdl output
19
DEMO_DIR = ../../vhdl/demo
20
# Path to local libraries
21
LIB_PATH = $(SRC_DIR)/common/libsoc
22 182 ja_rd
# Link script to be used
23
LINK_SCRIPT = $(SRC_DIR)/common/flash.lds
24 177 ja_rd
 
25
#-- Configure the VHDL simulation environment ----------------------------------
26
 
27
# Simulation length in cycles; long enough to let the program run to completion.
28 143 ja_rd
SIM_LENGTH = 400000000
29 90 ja_rd
 
30 177 ja_rd
 
31
#-- Configure the memory map ---------------------------------------------------
32
# FIXME this info is redundant with the linker script
33
 
34 90 ja_rd
# FPGA Block RAM parameters
35
BRAM_START = 0xbfc00000
36
CODE_BRAM_SIZE = 2048
37
# External RAM parameters (size in words)
38 177 ja_rd
XRAM_SIZE = 200000
39 90 ja_rd
XRAM_START = 0x00000000
40 177 ja_rd
# External FLASH parameters (size in words)
41
# Note te size is for simulation only
42
FLASH_START = 0xb0000000
43
FLASH_SIM_SIZE = 65536
44 90 ja_rd
 
45 177 ja_rd
#-- Configure the code ---------------------------------------------------------
46 90 ja_rd
 
47 177 ja_rd
# Options for 'boot' code running from BRAM at 0xbfc00000:
48
# 1.- Put the code in internal BRAM and the data in external SRAM.
49
# 2.- Do not use any of the standard libraries and use libsoc instead.
50
LFLAGS_BOOT = -L $(LIB_PATH) -Ttext $(BRAM_START) -Tdata $(XRAM_START) \
51
         -nodefaultlibs -nostdlib -ereset -I elf32-big -defsym entry=$(FLASH_START)
52
CFLAGS_BOOT = -O2 -Wall -c -s -fno-builtin -nodefaultlibs -nostdlib \
53
         -msoft-float -mips1 -G0
54
AFLAGS_BOOT = --defsym RUN_FROM_BRAM=1 --defsym XRAM_BASE=$(XRAM_START)
55 90 ja_rd
 
56
 
57 177 ja_rd
# Options for 'main' code running from FLASH at 0xb0000000:
58
# 1.- Put the code in FLASH and the data in external SRAM.
59
# 2.- Do not use any of the standard libraries and use libsoc instead.
60 182 ja_rd
LFLAGS_MAIN = -T$(LINK_SCRIPT) -L $(LIB_PATH) \
61 177 ja_rd
         -nodefaultlibs -nostdlib -eentry -I elf32-big
62
CFLAGS_MAIN = -O2 -Wall -c -s -fno-builtin -nodefaultlibs -nostdlib \
63
         -msoft-float -mips1 -G0
64
AFLAGS_MAIN = --defsym XRAM_BASE=$(XRAM_START)
65 90 ja_rd
 
66 177 ja_rd
# Object files for main program
67
OBJS = c_startup.o main.o actions1.o actions2.o init.o misc.o \
68
        score.o adv_baremetal.o
69
SRCS = actions1.c actions2.c main.c init.c misc.c score.c adv_baremetal.c
70 90 ja_rd
 
71
 
72 177 ja_rd
#-- Targets & rules ------------------------------------------------------------
73 90 ja_rd
 
74 177 ja_rd
adventure: adventure.bin bootstrap
75
        @# This comment prevents use of implicit rule so our rules are used instead.
76
        @# This will save us a few harmless linker warnings.
77 90 ja_rd
 
78 177 ja_rd
adventure.bin: adventure.axf
79
        # Extract object code to be placed in code space
80
        $(COPY) -I elf32-big -O binary adventure.axf adventure.bin
81
 
82
adventure.axf: $(OBJS)
83
        $(LD) $(LFLAGS_MAIN) -Map adventure.map -s -N -o adventure.axf $(OBJS) -lsoc
84
        -@$(DUMP) -m mips --disassemble adventure.axf > adventure.lst
85 90 ja_rd
 
86 177 ja_rd
c_startup.o: $(SRC_DIR)/common/c_startup.s
87
        $(AS) $(AFLAGS_MAIN) -o c_startup.o $(SRC_DIR)/common/c_startup.s
88
 
89
 
90
actions1.o:         misc.h main.h share.h funcs.h
91
main.o:             misc.h adv_baremetal.h
92
actions2.o:         misc.h main.h share.h funcs.h
93
init.o:             misc.h main.h share.h funcs.h
94
misc.o:             misc.h main.h
95
score.o:            misc.h main.h share.h
96
adv_baremetal.o:    adv_baremetal.h
97
 
98
 
99
#-- Compilation of 'boot' code to be run from BRAM
100
 
101
bootstrap.o: $(SRC_DIR)/common/bootstrap.s
102
        $(AS) -defsym XRAM_BASE=$(XRAM_START) -o bootstrap.o $(SRC_DIR)/common/bootstrap.s
103
 
104
opcode_emu.o: $(SRC_DIR)/common/opcode_emu.s
105
        $(AS) $(AFLAGS) -o opcode_emu.o $(SRC_DIR)/common/opcode_emu.s
106
 
107
bootstrap.axf: bootstrap.o opcode_emu.o
108
        $(LD) $(LFLAGS_BOOT) -Map bootstrap.map -s -N -o bootstrap.axf bootstrap.o opcode_emu.o
109
        -@$(DUMP) -I elf32-big --disassemble bootstrap.axf > bootstrap.lst
110
 
111
bootstrap: bootstrap.axf
112
        $(COPY) -I elf32-big -j .text -j .rodata -O binary bootstrap.axf bootstrap.code
113
        $(COPY) -I elf32-big -j .sbss -j .data -j .bss -O binary bootstrap.axf bootstrap.data
114
 
115
 
116
#-- Let's make some implicit rules explicit for clarity (well, 'clarity')
117
 
118
%.o: %.c
119
        $(CC) $(CFLAGS_MAIN) $< -o $@
120
 
121
 
122
#-- Targets that build the synthesizable vhdl; meant for direct invocation -----
123
 
124
 
125
 
126 90 ja_rd
# Create VHDL file for simulation test bench using TB2 template
127 177 ja_rd
sim: bootstrap adventure
128 143 ja_rd
        $(TO_VHDL) --code bootstrap.code --log_trigger=b0000000 \
129 90 ja_rd
                --flash adventure.bin --flash_size $(FLASH_SIM_SIZE) \
130
                --code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
131
                -s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
132
                -o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2
133
 
134
 
135
# Create VHDL file for hardware demo
136 177 ja_rd
demo: bootstrap adventure
137 90 ja_rd
        $(TO_VHDL) --code bootstrap.code \
138
        --code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
139
        -v $(SRC_DIR)/mips_mpu1_template.vhdl \
140
        -o $(DEMO_DIR)/mips_mpu.vhdl -e mips_mpu
141 177 ja_rd
 
142
 
143
#-- And now the usual housekeeping stuff ---------------------------------------
144
 
145
.PHONY: clean
146
 
147
clean:
148
        -$(RM) *.o *.obj *.map *.lst *.hex *.exe *.axf *.code *.data *.bin

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.