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#-------------------------------------------------------------------------------
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# This makefile does not contain any targets, only definitions used by the
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# makefiles of all the code samples.
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# It is meant to be included and not used standalone.
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#-------------------------------------------------------------------------------
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# SYSTEM PARAMETERS
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#
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# You can define here the size and address of the memory blocks of the system,
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# though you can't change the number and type of blocks here (see
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# /vhdl/mips_cache_*.vhdl).
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# Addresses are duplicated in the linker script (ion*.lds).
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#
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#-------------------------------------------------------------------------------
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# KNOWN PROBLEMS AND WORKAROUNDS
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#
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# 1.- LINK PROBLEM IF FLAG '-G0' NOT USED
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# If flag '-G0' is not used on gcc, linker fails with 'relocation
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# truncated to fit: R_MIPS_GPREL16' error message.
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# This only happens when you use global or static veriables, initialized
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# or not.
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# (See explaination in the project docs about $gp indexed addressing in
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# MIPS architectures and the -G0 flag).
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#
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# SUSPECTED CAUSE:
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# I'm sure there is something wrong with my linker script.
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# With the default link scripts this does not happen. Yet we need to use
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# a script so that we can split code and data (including read-only) to
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# different sections (and later to different ram blocks).
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#
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# WORKAROUND:
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# Use -G0 flag so that _gp indexing is disabled. There is a performance
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# hit, though. In effect we're telling the compiler to NOT use $gp for
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# indexed access to any global variables.
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# This is only necessary for the 'bare' target (no external ram and no
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# cache) and will have to be fixed for regular targets (by using a
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# standard link script or fixing mine).
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#-------------------------------------------------------------------------------
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### Toolchain config ###########################################################
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ifeq ($(LANG),)
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#**** Customize for Windows/Cygwin
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# Some common file commands (Cygwin/sh version, use your own)
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CP = cp
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RM = RM
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DWIN32 = -DWIN32
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LINUX_PWD =
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# MIPS GCC cross-toolchain: CodeSourcery -- replace with your own
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BIN_MIPS = C:/desarrollo/SourceryGpp/bin
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GCC_MIPS = $(BIN_MIPS)/mips-sde-elf-gcc.exe $(CFLAGS)
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AS_MIPS = $(BIN_MIPS)/mips-sde-elf-as
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LD_MIPS = $(BIN_MIPS)/mips-sde-elf-ld
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DUMP_MIPS = $(BIN_MIPS)/mips-sde-elf-objdump
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COPY_MIPS = $(BIN_MIPS)/mips-sde-elf-objcopy
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TO_VHDL = python ../bin2hdl.py
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else
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#**** Customize for Linux
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# MIPS GCC cross-toolchain: BuildRoot toolchain in my home directory -- replace with your own
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# NOTE: we will not use gcc builtin functions or libc
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BIN_MIPS = /home/jaruiz/desarrollo/uClinux/MIPS/buildroot/buildroot-2010.11/output/staging/usr/bin
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GCC_MIPS = $(BIN_MIPS)/mips-unknown-linux-uclibc-gcc $(CFLAGS)
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AS_MIPS = $(BIN_MIPS)/mips-unknown-linux-uclibc-as
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LD_MIPS = $(BIN_MIPS)/mips-unknown-linux-uclibc-ld
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DUMP_MIPS = $(BIN_MIPS)/mips-unknown-linux-uclibc-objdump
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COPY_MIPS = $(BIN_MIPS)/mips-unknown-linux-uclibc-objcopy
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TO_VHDL = python ../bin2hdl.py
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endif
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### System parameters ##########################################################
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# FIXME clean up parameter names
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# 'CODE_BRAM' is meant to be a small BRAM (2 to 4KB) used for bootstrapping.
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# 'DATA_BRAM' is a small BRAM connected to the data ports, used for debugging.
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# 'XRAM' is meant to be the main external RAM, either SRAM or SDRAM.
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# Default location of code BRAM is on the reset vector address
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CODE_BRAM_ADDRESS = 0
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# Default size of code BRAM in 32-bit words
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CODE_BRAM_SIZE = 1024
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# Default size of data BRAM in 32-bit words
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DATA_BRAM_SIZE = 256
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# Default address of BRAM -- used in some simulation-only tests, see makefiles
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DATA_BRAM_ADDRESS = 0x10000
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# Default size of data external RAM (XRAM) in 32-bit words (for simulation)
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XRAM_SIZE = 2048
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# Default address of XRAM
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XRAM_ADDRESS = 0x80000000
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### Build options ##############################################################
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# Don't use gcc builtin functions, and try to target MIPS-I architecture
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# This will prevent usage of unimplemented opcodes but will insert nops after
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# load instructions, which Ion does not need.
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# (See comment above about -G0 flag)
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CFLAGS = -O2 -Wall -c -s -fno-builtin -mips1 -G0
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# For most simulations and demos we'll use these parameters
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# Set code to BRAM and use XRAM for data
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# This will only work for small programs that fit the BRAM
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LFLAGS_BOOT = -Ttext $(CODE_BRAM_ADDRESS) -Tdata $(XRAM_ADDRESS) -eentry -I elf32-big
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# For some simulations we'll want to use TB1 which requires splitting code and
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# data. Use project 'bare cpu' linker script and build elf-bigendian objects.
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LFLAGS_BARE = -T../ion_noxram.lds -I elf32-big -eentry
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### Project directories ########################################################
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# VHDL test bench directory, where VHDL output files will be created
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TB_DIR = ../../vhdl/tb
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# VHDL DE-1 board demo root directory, for vhdl output
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DEMO_DIR = ../../vhdl/demo
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# Root test code source directory, where python script and vhdl templates are
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SRC_DIR = ..
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