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[/] [ion/] [trunk/] [src/] [memtest/] [makefile] - Blame information for rev 95
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ja_rd |
# External memory test -- build simulation and execution VHDL modules
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# Get common makefile stuff (toolchain & system config)
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include ..\\common\\makefile
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# We'll run the simulation for long enough to complete the test
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SIM_LENGTH = 30000
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# FPGA Block RAM parameters
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BRAM_START = 0xbfc00000
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CODE_BRAM_SIZE = 2048
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ja_rd |
# External RAM parameters (size in words)
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XRAM_SIZE = 1024
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XRAM_START = 0x00000000
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LFLAGS = -Ttext $(BRAM_START) -Tdata $(XRAM_START) -eentry -I elf32-big
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ja_rd |
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ja_rd |
clean:
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-$(RM) *.o *.obj *.map *.lst *.hex *.exe *.axf *.code *.data
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memtest:
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$(AS_MIPS) -defsym XRAM_BASE=$(XRAM_START) -o memtest.o memtest.s
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$(LD_MIPS) $(LFLAGS) -Map memtest.map -s -N -o memtest.axf memtest.o
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-@$(DUMP_MIPS) -I elf32-big --disassemble memtest.axf > memtest.lst
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# Dump code and data to separate binaries (data binary will be empty but TB2 needs it)
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$(COPY_MIPS) -I elf32-big -j .text -j .rodata -O binary memtest.axf memtest.code
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$(COPY_MIPS) -I elf32-big -j .sbss -j .data -j .bss -O binary memtest.axf memtest.data
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# Create VHDL file for simulation test bench using TB2 template
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memtest_sim: memtest
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$(TO_VHDL) --code memtest.code --data memtest.data \
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--flash flash.bin --flash_size 128 \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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-s $(SIM_LENGTH) -v $(SRC_DIR)\\mips_tb2_template.vhdl \
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-o $(TB_DIR)\\mips_tb2.vhdl -e mips_tb2
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# Create VHDL file for hardware demo
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memtest_demo: memtest
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$(TO_VHDL) --code memtest.code --data memtest.data \
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--code_size $(CODE_BRAM_SIZE) --data_size $(XRAM_SIZE) \
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-v $(SRC_DIR)/mips_mpu1_template.vhdl \
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-o $(DEMO_DIR)/mips_mpu.vhdl -e mips_mpu
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