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################################################################################
# memtest.s -- Test external RAM memory (XRAM)
#-------------------------------------------------------------------------------
# This program tests the external RAM (connected to the core through the cache
# module). Currently it only finds the RAM top address if given the bottom
# address. Subsequent versions will add some minimal diagnostic capability,
# which will be needed when DRAM access is implemented.
#
# This program does only support a single continuous chunk of RAM. If the cache
# module ever supports more than one chunk (e.g. DRAM and SRAM as in the DE-1
# board) this program will be modified accordingly.
#
# The program assumes there's no useable r/w memory other than the XRAM so it
# does not use any memory for variables or stack.
#-------------------------------------------------------------------------------
#
#
#-------------------------------------------------------------------------------
# To be run from reset vector, standalone. Interrupts must be disabled.
#
################################################################################
 
    #---- Test parameters
    .ifndef XRAM_MAX
    .set XRAM_MAX,      1024                # max. no. of KB to test for
    .endif
    .ifndef XRAM_BASE
    .set XRAM_BASE,     0x00000000          # 1st XRAM address
    .endif
 
 
    #---- Set to >0 to enable a few debug messages
    .set DEBUG,         0
 
    #---- Cache parameters
    .set ICACHE_NUM_LINES, 256              # no. of lines in the I-Cache
    .set DCACHE_NUM_LINES, 256              # no. of lines in the D-Cache
    .set DCACHE_LINE_SIZE, 4                # D-Cache line size in words
 
 
    #---- UART stuff
    .set UART_BASE,     0x20000000          # UART base address
    .set UART_TX,       0x0000              # TX reg offset
    .set UART_STATUS,   0x0020              # status reg offset
 
    #---------------------------------------------------------------------------
 
    .text
    .align  2
    .globl  entry
    .ent    entry
entry:
    .set    noreorder
 
    b       start_test
    nop
 
    .ifgt   0
    #--- Trap handler address: we don't expect any traps -----------------------
    .org    0x0180
interrupt_vector:
    b       interrupt_vector    # just freeze there
    nop
    .endif
 
#-------------------------------------------------------------------------------
 
start_test:
    mtc0    $0,$12              # disable interrupts
 
    .ifdef  TEST_CACHE          # if we're going to test the I-caches then
    jal     init_cache          # invalidate all the I-Cache lines now
    nop
    .endif
 
    la      $a0,msg0
    jal     puts
    nop
    li      $a0,XRAM_BASE
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,crlf
    jal     puts
    nop
 
    la      $t0,XRAM_BASE+4     # address of memory word being tested
    li      $t2,XRAM_MAX        # max amount of KBs to test for
    li      $t3,1               # (used to decrement $t2)
    li      $t4,0               # no. of KBs found
    move    $t5,$t0             # keep the start addr at hand for comparison
 
    sw      $zero,0($t0)        # clear 1st test word (in case of prev. run)
 
test_loop:
    lw      $t1,0($t0)          # read word contents
    beq     $t5,$t1,hit_mirror  # if it's the start address, we hit a mirror
    nop                         # we rolled off the end of the RAM back here
    sw      $t0,0($t0)          # word = word address
    lw      $t1,0($t0)          # read word back...
    bne     $t1,$t0,bad_word    # ...and if no match, we run off the RAM
    nop                         #
    sub     $t2,$t2,$t3         # decrement loop counter...
    bnez    $t2,test_loop       # ...and go back if there's more to go
    addiu   $t0,0x400           # in any case, increment test address by 1KB
 
    b       end_test            # end of memory found, result is in $t4
    nop
 
hit_mirror:                     # memory mirror detected
    .ifgt   DEBUG
    la      $a0,msg_mirror
    jal     puts
    nop
    .endif
    b       end_test
    nop
 
bad_word:                       # readback error detected (maybe r/o area?)
    .ifgt   DEBUG
    la      $a0,msg_bad
    jal     puts
    nop
    .endif
    b       end_test
    nop
 
end_test:                       # test done, ramtop+4 in $t0, #KB in $t4
 
 
    la      $a0,msg1            # Print ramtop message...
    jal     puts
    nop
 
    addi    $a0,$t0,-4          # substract the +4 offset we added before
    move    $sp,$t0             # init SP at the top of RAM space
    addi    $sp,$sp,-16
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,crlf
    jal     puts
    nop
 
    # Clear RAM (only first words, so that simulation is not eternal)
    .ifgt 1
    li      $a0,XRAM_BASE
    addi    $a1,$a0,80*4
clear_xram_loop:
    sw      $zero,0($a0)
    blt     $a0,$a1,clear_xram_loop
    addi    $a0,$a0,4
    .endif
 
    # Test code execution from SRAM. We copy the test_exec_sram routine to
    # the base of the SRAM and then jal to it
    li      $a1,64
    li      $a0,XRAM_BASE
    la      $a3,test_exec_sram
copy_to_sram:
    lw      $a2,0($a3)
    nop
    sw      $a2,0($a0)
    addi    $a1,$a1,-4
    addi    $a3,$a3,4
    bnez    $a1,copy_to_sram
    addi    $a0,$a0,4
 
    # Optionally dump first few words of XRAM and jump onto XRAM
    .ifgt 1
    la      $a0,msg5
    jal     puts
    nop
    li      $a0,XRAM_BASE
    jal     dump_hex
    ori     $a1,$zero,20
    .endif
 
    .ifgt   1
    li      $a0,XRAM_BASE
    nop
    jalr    $a0
    nop
    .endif
 
    # If all went well in the SRAM we'll have returned here
    .ifgt   0
    # FIXME now we should do some strong test on the RAM to see if it's wired
    # correctly, using the right timing, etc.
 
    # Ok, now we know we have some RAM and stack space we can do some further
    # testing.
    # dump the first few words of FLASH
 
    la      $a0,msg2
    jal     puts
    nop
 
    # FIXME flash base address is hardcoded
    li      $a0,0xb0000000
    jal     put_hex
    ori     $a1,$zero,8
 
    la      $a0,crlf
    jal     puts
    nop
 
    la      $a0,crlf
    jal     puts
    nop
 
    li      $a0,0xb0000000
    jal     dump_hex
    ori     $a1,$zero,6
    .endif
 
 
    # Optionally jump to FLASH. This is only useful in simulation.
    .ifgt 1
    .ifdef  EXEC_FLASH
    la      $a0,msg8
    jal     puts
    nop
    li      $a0,0xb0000000
    nop
    jalr    $a0
    nop
    .endif
    .endif
 
    la      $a0,msg4
    jal     puts
    nop
 
 
$DONE:
    j       $DONE               # ...and freeze here
    nop
 
 
    # This short routine will be copied to RAM and then executed there. This
    # will test the behavior of the I-Cache.
test_exec_sram:
    #jr      $ra
    #nop
    sw      $ra,0($sp)
    addi    $sp,$sp,-4
    la      $a0,msg3
    la      $a1,puts
    jalr    $a1
    nop
    lw      $ra,4($sp)
    jr      $ra
    addi    $sp,$sp,4
test_exec_sram_end:
    nop
 
 
 
#---- Functions ----------------------------------------------------------------
 
# void dump_hex(int *address {a0}, int len {a1})
dump_hex:
    move    $t7,$a0
    move    $t6,$a1
    sw      $ra,0($sp)
    addi    $sp,$sp,-4
 
dump_hex_loop_lines:
    move    $a0,$t7
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,msg6
    jal     puts
    nop
    li      $t9,4
 
dump_hex_loop_words:
    lw      $a0,0($t7)
    jal     put_hex
    li      $a1,8
 
    la      $a0,space
    jal     puts
    addi    $t7,4
 
    addi    $t9,$t9,-1
    bnez    $t9,dump_hex_loop_words
    nop
 
    la      $a0,crlf
    jal     puts
    nop
 
    addi    $t6,$t6,-1
    bnez    $t6,dump_hex_loop_lines
    nop
 
    la      $a0,msg7
    jal     puts
    addi    $t7,4
 
    .ifgt 0
    lw      $ra,4($sp)
    move    $a0,$ra
    li      $a1,8
    jal     put_hex
    nop
qqqq:
    j       qqqq
    nop
    .endif
 
    nop
    lw      $ra,4($sp)
    jr      $ra
    addi    $sp,$sp,4
 
 
#---- Cache-related functions --------------------------------------------------
 
# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)
init_cache:
    li      $a0,0x00010000      # Disable cache, enable I-cache line invalidation
    mtc0    $a0,$12
 
    # In order to invalidate a I-Cache line we have to write its tag number to
    # any address while bits CP0[12].17:16=01. The write will be executed as a
    # regular write too, as a side effect, so we need to choose a harmless
    # target address.
 
    li      $a0,XRAM_BASE
    li      $a2,0
    li      $a1,ICACHE_NUM_LINES-1
 
inv_i_cache_loop:
    sw      $a2,0($a0)
    blt     $a2,$a1,inv_i_cache_loop
    addi    $a2,1
 
    mfc0    $a0,$12
    li      $a1,0x00020000      # Leave cache enabled
    or      $a0,$a1,$a1
    jr      $ra
    mtc0    $a0,$12
 
 
 
#--- Special functions that do not use any RAM ---------------------------------
# WARNING: Not for general use!
# All parameters in $a0..$a4, stack unused. No attempt to comply with any ABI
# has been made.
# Since we can't use any RAM, registers have been used with no regard for
# intended usage -- have to share reg bank with calling function.
 
# void puts(char *s) -- print zero-terminated string
puts:
    la      $a2,UART_BASE       # UART base address
puts_loop:
    lb      $v0,0($a0)
    beqz    $v0,puts_end
    addiu   $a0,1
puts_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    beqz    $v1,puts_wait_tx_rdy
    nop
    sw      $v0,UART_TX($a2)
    b       puts_loop
    nop
 
puts_end:
    jr      $ra
    nop
 
# void put_hex(int n, int d) -- print integer as d-digit hex
put_hex:
    la      $a2,UART_BASE
    la      $a3,put_hex_table
    addi    $a1,-1
    add     $a1,$a1,$a1
    add     $a1,$a1,$a1
 
put_hex_loop:
    srlv    $v0,$a0,$a1
    andi    $v0,$v0,0x0f
    addu    $s2,$a3,$v0
    lb      $v0,0($s2)
put_hex_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    beqz    $v1,put_hex_wait_tx_rdy
    nop
    sw      $v0,UART_TX($a2)
 
    bnez    $a1,put_hex_loop
    addi    $a1,-4
 
    jr      $ra
    nop
 
 
#---- Constant data (note we keep it in the text section) ----------------------
 
put_hex_table:
    .ascii  "0123456789abcdef"
 
msg0:
    .ascii  "\n\r"
    .asciz  "Scanning external memory at 0x"
msg1:
    .asciz  "Found XRAM top at           0x"
crlf:
    .asciz "\n\r"
space:
    .asciz "  "
msg_mirror:
    .asciz "hit mirror!\n\r"
msg_bad:
    .asciz "bad readback!\n\r"
msg2:
    .asciz "\n\rDumping the first few words of FLASH at address 0x"
msg3:
    .ascii "\n\rTesting code execution from SRAM...  "
    .asciz "if you see this, it worked\n\r"
msg4:
    .ascii  "\n\r\n\r"
    .asciz  "End of test.\n\r\n\r"
msg5:
    .asciz  "Dump of first few words of XRAM after initialization:\n\r"
msg6:
    .asciiz ": "
msg7:
    .asciiz "<end of dump>"
msg8:
    .ascii  "\n\r"
    .asciiz "Testing execution from 8-bit static memory (FLASH)\n\r"
 
    .set    reorder
    .end    entry
 

Line No.	Rev	Author	Line
1	50	ja_rd	`################################################################################`
2			`# memtest.s -- Test external RAM memory (XRAM)`
3			`#-------------------------------------------------------------------------------`
4			`# This program tests the external RAM (connected to the core through the cache`
5	109	ja_rd	`# module). Currently it only finds the RAM top address if given the bottom`
6	50	ja_rd	`# address. Subsequent versions will add some minimal diagnostic capability,`
7			`# which will be needed when DRAM access is implemented.`
8			`#`
9			`# This program does only support a single continuous chunk of RAM. If the cache`
10	109	ja_rd	`# module ever supports more than one chunk (e.g. DRAM and SRAM as in the DE-1`
11	50	ja_rd	`# board) this program will be modified accordingly.`
12	109	ja_rd	`#`
13	50	ja_rd	`# The program assumes there's no useable r/w memory other than the XRAM so it`
14			`# does not use any memory for variables or stack.`
15	109	ja_rd	`#-------------------------------------------------------------------------------`
16	50	ja_rd	`#`
17	109	ja_rd	`#`
18			`#-------------------------------------------------------------------------------`
19	50	ja_rd	`# To be run from reset vector, standalone. Interrupts must be disabled.`
20			`#`
21			`################################################################################`
22
23	109	ja_rd	`#---- Test parameters`
24			`.ifndef XRAM_MAX`
25			`.set XRAM_MAX, 1024 # max. no. of KB to test for`
26			`.endif`
27			`.ifndef XRAM_BASE`
28			`.set XRAM_BASE, 0x00000000 # 1st XRAM address`
29			`.endif`
30
31
32	50	ja_rd	`#---- Set to >0 to enable a few debug messages`
33			`.set DEBUG, 0`
34
35	109	ja_rd	`#---- Cache parameters`
36			`.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache`
37			`.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache`
38			`.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words`
39	50	ja_rd
40	109	ja_rd
41			`#---- UART stuff`
42	50	ja_rd	`.set UART_BASE, 0x20000000 # UART base address`
43			`.set UART_TX, 0x0000 # TX reg offset`
44			`.set UART_STATUS, 0x0020 # status reg offset`
45
46			`#---------------------------------------------------------------------------`
47
48			`.text`
49			`.align 2`
50			`.globl entry`
51			`.ent entry`
52			`entry:`
53			`.set noreorder`
54
55			`b start_test`
56			`nop`
57
58	66	ja_rd	`.ifgt 0`
59	50	ja_rd	`#--- Trap handler address: we don't expect any traps -----------------------`
60	66	ja_rd	`.org 0x0180`
61	50	ja_rd	`interrupt_vector:`
62	109	ja_rd	`b interrupt_vector # just freeze there`
63	50	ja_rd	`nop`
64	66	ja_rd	`.endif`
65	109	ja_rd
66	50	ja_rd	`#-------------------------------------------------------------------------------`
67
68	109	ja_rd	`start_test:`
69	50	ja_rd	`mtc0 $0,$12 # disable interrupts`
70	109	ja_rd
71			`.ifdef TEST_CACHE # if we're going to test the I-caches then`
72			`jal init_cache # invalidate all the I-Cache lines now`
73			`nop`
74			`.endif`
75
76	50	ja_rd	`la $a0,msg0`
77			`jal puts`
78			`nop`
79			`li $a0,XRAM_BASE`
80			`li $a1,8`
81			`jal put_hex`
82			`nop`
83			`la $a0,crlf`
84			`jal puts`
85			`nop`
86	109	ja_rd
87	66	ja_rd	`la $t0,XRAM_BASE+4 # address of memory word being tested`
88	50	ja_rd	`li $t2,XRAM_MAX # max amount of KBs to test for`
89			`li $t3,1 # (used to decrement $t2)`
90			`li $t4,0 # no. of KBs found`
91			`move $t5,$t0 # keep the start addr at hand for comparison`
92	109	ja_rd
93	50	ja_rd	`sw $zero,0($t0) # clear 1st test word (in case of prev. run)`
94	109	ja_rd
95	50	ja_rd	`test_loop:`
96			`lw $t1,0($t0) # read word contents`
97			`beq $t5,$t1,hit_mirror # if it's the start address, we hit a mirror`
98			`nop # we rolled off the end of the RAM back here`
99			`sw $t0,0($t0) # word = word address`
100			`lw $t1,0($t0) # read word back...`
101			`bne $t1,$t0,bad_word # ...and if no match, we run off the RAM`
102	109	ja_rd	`nop #`
103	50	ja_rd	`sub $t2,$t2,$t3 # decrement loop counter...`
104			`bnez $t2,test_loop # ...and go back if there's more to go`
105			`addiu $t0,0x400 # in any case, increment test address by 1KB`
106	109	ja_rd
107	50	ja_rd	`b end_test # end of memory found, result is in $t4`
108			`nop`
109	109	ja_rd
110	50	ja_rd	`hit_mirror: # memory mirror detected`
111			`.ifgt DEBUG`
112			`la $a0,msg_mirror`
113			`jal puts`
114			`nop`
115			`.endif`
116			`b end_test`
117			`nop`
118	109	ja_rd
119	50	ja_rd	`bad_word: # readback error detected (maybe r/o area?)`
120			`.ifgt DEBUG`
121			`la $a0,msg_bad`
122			`jal puts`
123			`nop`
124			`.endif`
125			`b end_test`
126			`nop`
127
128	78	ja_rd	`end_test: # test done, ramtop+4 in $t0, #KB in $t4`
129
130	109	ja_rd
131	50	ja_rd	`la $a0,msg1 # Print ramtop message...`
132			`jal puts`
133			`nop`
134	109	ja_rd
135	66	ja_rd	`addi $a0,$t0,-4 # substract the +4 offset we added before`
136	78	ja_rd	`move $sp,$t0 # init SP at the top of RAM space`
137	90	ja_rd	`addi $sp,$sp,-16`
138	50	ja_rd	`li $a1,8`
139			`jal put_hex`
140			`nop`
141			`la $a0,crlf`
142			`jal puts`
143			`nop`
144	109	ja_rd
145			`# Clear RAM (only first words, so that simulation is not eternal)`
146			`.ifgt 1`
147			`li $a0,XRAM_BASE`
148			`addi $a1,$a0,80*4`
149			`clear_xram_loop:`
150			`sw $zero,0($a0)`
151			`blt $a0,$a1,clear_xram_loop`
152			`addi $a0,$a0,4`
153			`.endif`
154
155			`# Test code execution from SRAM. We copy the test_exec_sram routine to`
156	90	ja_rd	`# the base of the SRAM and then jal to it`
157			`li $a1,64`
158			`li $a0,XRAM_BASE`
159			`la $a3,test_exec_sram`
160			`copy_to_sram:`
161			`lw $a2,0($a3)`
162			`nop`
163			`sw $a2,0($a0)`
164			`addi $a1,$a1,-4`
165			`addi $a3,$a3,4`
166			`bnez $a1,copy_to_sram`
167			`addi $a0,$a0,4`
168	109	ja_rd
169			`# Optionally dump first few words of XRAM and jump onto XRAM`
170			`.ifgt 1`
171			`la $a0,msg5`
172			`jal puts`
173			`nop`
174			`li $a0,XRAM_BASE`
175	90	ja_rd	`jal dump_hex`
176	109	ja_rd	`ori $a1,$zero,20`
177	90	ja_rd	`.endif`
178	109	ja_rd
179			`.ifgt 1`
180	90	ja_rd	`li $a0,XRAM_BASE`
181	109	ja_rd	`nop`
182	90	ja_rd	`jalr $a0`
183			`nop`
184	109	ja_rd	`.endif`
185
186			`# If all went well in the SRAM we'll have returned here`
187	90	ja_rd	`.ifgt 0`
188	109	ja_rd	`# FIXME now we should do some strong test on the RAM to see if it's wired`
189	78	ja_rd	`# correctly, using the right timing, etc.`
190	109	ja_rd
191	78	ja_rd	`# Ok, now we know we have some RAM and stack space we can do some further`
192			`# testing.`
193			`# dump the first few words of FLASH`
194	109	ja_rd
195	78	ja_rd	`la $a0,msg2`
196			`jal puts`
197			`nop`
198	109	ja_rd
199	78	ja_rd	`# FIXME flash base address is hardcoded`
200			`li $a0,0xb0000000`
201			`jal put_hex`
202			`ori $a1,$zero,8`
203	109	ja_rd
204	78	ja_rd	`la $a0,crlf`
205			`jal puts`
206			`nop`
207
208			`la $a0,crlf`
209			`jal puts`
210			`nop`
211	109	ja_rd
212	78	ja_rd	`li $a0,0xb0000000`
213			`jal dump_hex`
214	109	ja_rd	`ori $a1,$zero,6`
215	90	ja_rd	`.endif`
216	109	ja_rd
217
218			`# Optionally jump to FLASH. This is only useful in simulation.`
219			`.ifgt 1`
220			`.ifdef EXEC_FLASH`
221			`la $a0,msg8`
222			`jal puts`
223			`nop`
224			`li $a0,0xb0000000`
225			`nop`
226			`jalr $a0`
227			`nop`
228			`.endif`
229			`.endif`
230
231			`la $a0,msg4`
232			`jal puts`
233			`nop`
234
235
236	50	ja_rd	`$DONE:`
237			`j $DONE # ...and freeze here`
238			`nop`
239
240
241	109	ja_rd	`# This short routine will be copied to RAM and then executed there. This`
242			`# will test the behavior of the I-Cache.`
243	90	ja_rd	`test_exec_sram:`
244			`#jr $ra`
245			`#nop`
246			`sw $ra,0($sp)`
247			`addi $sp,$sp,-4`
248			`la $a0,msg3`
249			`la $a1,puts`
250			`jalr $a1`
251			`nop`
252			`lw $ra,4($sp)`
253			`jr $ra`
254			`addi $sp,$sp,4`
255			`test_exec_sram_end:`
256	109	ja_rd	`nop`
257	90	ja_rd
258
259
260	50	ja_rd	`#---- Functions ----------------------------------------------------------------`
261	78	ja_rd
262	109	ja_rd	`# void dump_hex(int *address {a0}, int len {a1})`
263	78	ja_rd	`dump_hex:`
264			`move $t7,$a0`
265	109	ja_rd	`move $t6,$a1`
266	78	ja_rd	`sw $ra,0($sp)`
267			`addi $sp,$sp,-4`
268	109	ja_rd
269			`dump_hex_loop_lines:`
270			`move $a0,$t7`
271			`li $a1,8`
272			`jal put_hex`
273			`nop`
274			`la $a0,msg6`
275			`jal puts`
276			`nop`
277			`li $t9,4`
278
279			`dump_hex_loop_words:`
280	78	ja_rd	`lw $a0,0($t7)`
281			`jal put_hex`
282			`li $a1,8`
283	109	ja_rd
284	78	ja_rd	`la $a0,space`
285			`jal puts`
286			`addi $t7,4`
287	109	ja_rd
288			`addi $t9,$t9,-1`
289			`bnez $t9,dump_hex_loop_words`
290	78	ja_rd	`nop`
291	109	ja_rd
292			`la $a0,crlf`
293			`jal puts`
294			`nop`
295
296			`addi $t6,$t6,-1`
297			`bnez $t6,dump_hex_loop_lines`
298			`nop`
299
300			`la $a0,msg7`
301			`jal puts`
302			`addi $t7,4`
303
304			`.ifgt 0`
305	78	ja_rd	`lw $ra,4($sp)`
306	109	ja_rd	`move $a0,$ra`
307			`li $a1,8`
308			`jal put_hex`
309			`nop`
310			`qqqq:`
311			`j qqqq`
312			`nop`
313			`.endif`
314
315			`nop`
316			`lw $ra,4($sp)`
317	78	ja_rd	`jr $ra`
318			`addi $sp,$sp,4`
319
320
321	109	ja_rd	`#---- Cache-related functions --------------------------------------------------`
322
323			`# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)`
324			`init_cache:`
325			`li $a0,0x00010000 # Disable cache, enable I-cache line invalidation`
326			`mtc0 $a0,$12`
327
328			`# In order to invalidate a I-Cache line we have to write its tag number to`
329			`# any address while bits CP0[12].17:16=01. The write will be executed as a`
330			`# regular write too, as a side effect, so we need to choose a harmless`
331			`# target address.`
332
333			`li $a0,XRAM_BASE`
334			`li $a2,0`
335			`li $a1,ICACHE_NUM_LINES-1`
336
337			`inv_i_cache_loop:`
338			`sw $a2,0($a0)`
339			`blt $a2,$a1,inv_i_cache_loop`
340			`addi $a2,1`
341
342			`mfc0 $a0,$12`
343			`li $a1,0x00020000 # Leave cache enabled`
344			`or $a0,$a1,$a1`
345			`jr $ra`
346			`mtc0 $a0,$12`
347
348
349
350	78	ja_rd	`#--- Special functions that do not use any RAM ---------------------------------`
351	50	ja_rd	`# WARNING: Not for general use!`
352			`# All parameters in $a0..$a4, stack unused. No attempt to comply with any ABI`
353			`# has been made.`
354	109	ja_rd	`# Since we can't use any RAM, registers have been used with no regard for`
355			`# intended usage -- have to share reg bank with calling function.`
356
357	50	ja_rd	`# void puts(char *s) -- print zero-terminated string`
358	109	ja_rd	`puts:`
359	78	ja_rd	`la $a2,UART_BASE # UART base address`
360	50	ja_rd	`puts_loop:`
361			`lb $v0,0($a0)`
362			`beqz $v0,puts_end`
363			`addiu $a0,1`
364	109	ja_rd	`puts_wait_tx_rdy:`
365	78	ja_rd	`lw $v1,UART_STATUS($a2)`
366	50	ja_rd	`andi $v1,$v1,0x02`
367			`beqz $v1,puts_wait_tx_rdy`
368			`nop`
369	78	ja_rd	`sw $v0,UART_TX($a2)`
370	50	ja_rd	`b puts_loop`
371			`nop`
372	109	ja_rd
373	50	ja_rd	`puts_end:`
374			`jr $ra`
375	109	ja_rd	`nop`
376	50	ja_rd
377			`# void put_hex(int n, int d) -- print integer as d-digit hex`
378			`put_hex:`
379	78	ja_rd	`la $a2,UART_BASE`
380			`la $a3,put_hex_table`
381	50	ja_rd	`addi $a1,-1`
382			`add $a1,$a1,$a1`
383			`add $a1,$a1,$a1`
384
385			`put_hex_loop:`
386			`srlv $v0,$a0,$a1`
387			`andi $v0,$v0,0x0f`
388	78	ja_rd	`addu $s2,$a3,$v0`
389	50	ja_rd	`lb $v0,0($s2)`
390			`put_hex_wait_tx_rdy:`
391	78	ja_rd	`lw $v1,UART_STATUS($a2)`
392	50	ja_rd	`andi $v1,$v1,0x02`
393			`beqz $v1,put_hex_wait_tx_rdy`
394			`nop`
395	78	ja_rd	`sw $v0,UART_TX($a2)`
396	109	ja_rd
397	50	ja_rd	`bnez $a1,put_hex_loop`
398			`addi $a1,-4`
399
400			`jr $ra`
401			`nop`
402
403	109	ja_rd
404	50	ja_rd	`#---- Constant data (note we keep it in the text section) ----------------------`
405
406			`put_hex_table:`
407			`.ascii "0123456789abcdef"`
408
409	109	ja_rd	`msg0:`
410	50	ja_rd	`.ascii "\n\r"`
411			`.asciz "Scanning external memory at 0x"`
412			`msg1:`
413			`.asciz "Found XRAM top at 0x"`
414			`crlf:`
415			`.asciz "\n\r"`
416			`space:`
417			`.asciz " "`
418			`msg_mirror:`
419			`.asciz "hit mirror!\n\r"`
420			`msg_bad:`
421			`.asciz "bad readback!\n\r"`
422	78	ja_rd	`msg2:`
423			`.asciz "\n\rDumping the first few words of FLASH at address 0x"`
424	90	ja_rd	`msg3:`
425			`.ascii "\n\rTesting code execution from SRAM... "`
426			`.asciz "if you see this, it worked\n\r"`
427	109	ja_rd	`msg4:`
428			`.ascii "\n\r\n\r"`
429			`.asciz "End of test.\n\r\n\r"`
430			`msg5:`
431			`.asciz "Dump of first few words of XRAM after initialization:\n\r"`
432			`msg6:`
433			`.asciiz ": "`
434			`msg7:`
435			`.asciiz "<end of dump>"`
436			`msg8:`
437			`.ascii "\n\r"`
438			`.asciiz "Testing execution from 8-bit static memory (FLASH)\n\r"`
439
440	50	ja_rd	`.set reorder`
441			`.end entry`
442	109	ja_rd

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