URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [memtest/] [memtest.s] - Blame information for rev 190

Go to most recent revision | Details | Compare with Previous | View Log


################################################################################
# memtest.s -- Test external RAM memory (XRAM)
#-------------------------------------------------------------------------------
# This program tests the external RAM (connected to the core through the cache
# module). Currently it only finds the RAM top address if given the bottom
# address. Subsequent versions will add some minimal diagnostic capability,
# which will be needed when DRAM access is implemented.
#
# This program does only support a single continuous chunk of RAM. If the cache
# module ever supports more than one chunk (e.g. DRAM and SRAM as in the DE-1
# board) this program will be modified accordingly.
#
# The program assumes there's no useable r/w memory other than the XRAM so it
# does not use any memory for variables or stack.
#-------------------------------------------------------------------------------
#
#
#-------------------------------------------------------------------------------
# To be run from reset vector, standalone. Interrupts must be disabled.
#
################################################################################
 
    #---- Test parameters
    .ifndef XRAM_MAX
    .set XRAM_MAX,      1024                # max. no. of KB to test for
    .endif
    .ifndef XRAM_BASE
    .set XRAM_BASE,     0x00000000          # 1st XRAM address
    .endif
 
 
    #---- Set to >0 to enable a few debug messages
    .set DEBUG,         0
 
    #---- Cache parameters
    .set ICACHE_NUM_LINES, 256              # no. of lines in the I-Cache
    .set DCACHE_NUM_LINES, 256              # no. of lines in the D-Cache
    .set DCACHE_LINE_SIZE, 4                # D-Cache line size in words
 
 
    #---- UART stuff
    .set UART_BASE,     0x20000000          # UART base address
    .set UART_TX,       0x0000              # TX reg offset
    .set UART_STATUS,   0x0020              # status reg offset
 
    #---------------------------------------------------------------------------
 
    .text
    .align  2
    .globl  entry
    .ent    entry
entry:
    .set    noreorder
 
    b       start_test
    nop
 
    .ifgt   0
    #--- Trap handler address: we don't expect any traps -----------------------
    .org    0x0180
interrupt_vector:
    b       interrupt_vector    # just freeze there
    nop
    .endif
 
#-------------------------------------------------------------------------------
 
start_test:
    li      $a0,0x00000002
    mtc0    $a0,$12             # disable interrupts and cache
 
    .ifdef  TEST_CACHE          # if we're going to test the I-caches then
    jal     init_cache          # invalidate all the I-Cache lines now
    nop
    .endif
 
    la      $a0,msg0
    jal     puts
    nop
    li      $a0,XRAM_BASE
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,crlf
    jal     puts
    nop
 
    la      $t0,XRAM_BASE+4     # address of memory word being tested
    li      $t2,XRAM_MAX        # max amount of KBs to test for
    li      $t3,1               # (used to decrement $t2)
    li      $t4,0               # no. of KBs found
    move    $t5,$t0             # keep the start addr at hand for comparison
 
    sw      $zero,0($t0)        # clear 1st test word (in case of prev. run)
 
test_loop:
    lw      $t1,0($t0)          # read word contents
    beq     $t5,$t1,hit_mirror  # if it's the start address, we hit a mirror
    nop                         # we rolled off the end of the RAM back here
    sw      $t0,0($t0)          # word = word address
    lw      $t1,0($t0)          # read word back...
    bne     $t1,$t0,bad_word    # ...and if no match, we run off the RAM
    nop                         #
    sub     $t2,$t2,$t3         # decrement loop counter...
    bnez    $t2,test_loop       # ...and go back if there's more to go
    addiu   $t0,0x400           # in any case, increment test address by 1KB
 
    b       end_test            # end of memory found, result is in $t4
    nop
 
hit_mirror:                     # memory mirror detected
    .ifgt   DEBUG
    la      $a0,msg_mirror
    jal     puts
    nop
    .endif
    b       end_test
    nop
 
bad_word:                       # readback error detected (maybe r/o area?)
    .ifgt   DEBUG
    la      $a0,msg_bad
    jal     puts
    nop
    .endif
    b       end_test
    nop
 
end_test:                       # test done, ramtop+4 in $t0, #KB in $t4
 
 
    la      $a0,msg1            # Print ramtop message...
    jal     puts
    nop
 
    addi    $a0,$t0,-4          # substract the +4 offset we added before
    move    $sp,$t0             # init SP at the top of RAM space
    addi    $sp,$sp,-16
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,crlf
    jal     puts
    nop
 
    # Clear RAM (only first words, so that simulation is not eternal)
    .ifgt 1
    li      $a0,XRAM_BASE
    addi    $a1,$a0,80*4
clear_xram_loop:
    sw      $zero,0($a0)
    blt     $a0,$a1,clear_xram_loop
    addi    $a0,$a0,4
    .endif
 
    # Test code execution from SRAM. We copy the test_exec_sram routine to
    # the base of the SRAM and then jal to it
    li      $a1,64
    li      $a0,XRAM_BASE
    la      $a3,test_exec_sram
copy_to_sram:
    lw      $a2,0($a3)
    nop
    sw      $a2,0($a0)
    addi    $a1,$a1,-4
    addi    $a3,$a3,4
    bnez    $a1,copy_to_sram
    addi    $a0,$a0,4
 
    # Optionally dump first few words of XRAM and jump onto XRAM
    .ifgt 1
    la      $a0,msg5
    jal     puts
    nop
    li      $a0,XRAM_BASE
    jal     dump_hex
    ori     $a1,$zero,20
    .endif
 
    .ifgt   1
    li      $a0,XRAM_BASE
    nop
    jalr    $a0
    nop
    .endif
 
    # If all went well in the SRAM we'll have returned here
    .ifgt   0
    # FIXME now we should do some strong test on the RAM to see if it's wired
    # correctly, using the right timing, etc.
 
    # Ok, now we know we have some RAM and stack space we can do some further
    # testing.
    # dump the first few words of FLASH
 
    la      $a0,msg2
    jal     puts
    nop
 
    # FIXME flash base address is hardcoded
    li      $a0,0xb0000000
    jal     put_hex
    ori     $a1,$zero,8
 
    la      $a0,crlf
    jal     puts
    nop
 
    la      $a0,crlf
    jal     puts
    nop
 
    li      $a0,0xb0000000
    jal     dump_hex
    ori     $a1,$zero,6
    .endif
 
 
    # Optionally jump to FLASH. This is only useful in simulation.
    .ifgt 1
    .ifdef  EXEC_FLASH
    la      $a0,msg8
    jal     puts
    nop
    li      $a0,0xb0000000
    nop
    jalr    $a0
    nop
    .endif
    .endif
 
    la      $a0,msg4
    jal     puts
    nop
 
 
$DONE:
    j       $DONE               # ...and freeze here
    nop
 
 
    # This short routine will be copied to RAM and then executed there. This
    # will test the behavior of the I-Cache.
test_exec_sram:
    #jr      $ra
    #nop
    sw      $ra,0($sp)
    addi    $sp,$sp,-4
    la      $a0,msg3
    la      $a1,puts
    jalr    $a1
    nop
    lw      $ra,4($sp)
    jr      $ra
    addi    $sp,$sp,4
test_exec_sram_end:
    nop
 
 
 
#---- Functions ----------------------------------------------------------------
 
# void dump_hex(int *address {a0}, int len {a1})
dump_hex:
    move    $t7,$a0
    move    $t6,$a1
    sw      $ra,0($sp)
    addi    $sp,$sp,-4
 
dump_hex_loop_lines:
    move    $a0,$t7
    li      $a1,8
    jal     put_hex
    nop
    la      $a0,msg6
    jal     puts
    nop
    li      $t9,4
 
dump_hex_loop_words:
    lw      $a0,0($t7)
    jal     put_hex
    li      $a1,8
 
    la      $a0,space
    jal     puts
    addi    $t7,4
 
    addi    $t9,$t9,-1
    bnez    $t9,dump_hex_loop_words
    nop
 
    la      $a0,crlf
    jal     puts
    nop
 
    addi    $t6,$t6,-1
    bnez    $t6,dump_hex_loop_lines
    nop
 
    la      $a0,msg7
    jal     puts
    addi    $t7,4
 
    .ifgt 0
    lw      $ra,4($sp)
    move    $a0,$ra
    li      $a1,8
    jal     put_hex
    nop
qqqq:
    j       qqqq
    nop
    .endif
 
    nop
    lw      $ra,4($sp)
    jr      $ra
    addi    $sp,$sp,4
 
 
#---- Cache-related functions --------------------------------------------------
 
# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)
init_cache:
    li      $a0,0x00010000      # Disable cache, enable I-cache line invalidation
    mfc0    $a1,$12
    or      $a0,$a0,$a1
    mtc0    $a0,$12
 
    # In order to invalidate a I-Cache line we have to write its tag number to
    # any address while bits CP0[12].17:16=01. The write will be executed as a
    # regular write too, as a side effect, so we need to choose a harmless
    # target address.
 
    li      $a0,XRAM_BASE
    li      $a2,0
    li      $a1,ICACHE_NUM_LINES-1
 
inv_i_cache_loop:
    sw      $a2,0($a0)
    blt     $a2,$a1,inv_i_cache_loop
    addi    $a2,1
 
    mfc0    $a0,$12
    li      $a1,0x00020000      # Leave cache enabled
    or      $a0,$a0,$a1
    jr      $ra
    mtc0    $a0,$12
 
 
 
#--- Special functions that do not use any RAM ---------------------------------
# WARNING: Not for general use!
# All parameters in $a0..$a4, stack unused. No attempt to comply with any ABI
# has been made.
# Since we can't use any RAM, registers have been used with no regard for
# intended usage -- have to share reg bank with calling function.
 
# void puts(char *s) -- print zero-terminated string
puts:
    la      $a2,UART_BASE       # UART base address
puts_loop:
    lb      $v0,0($a0)
    beqz    $v0,puts_end
    addiu   $a0,1
puts_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    beqz    $v1,puts_wait_tx_rdy
    nop
    sw      $v0,UART_TX($a2)
    b       puts_loop
    nop
 
puts_end:
    jr      $ra
    nop
 
# void put_hex(int n, int d) -- print integer as d-digit hex
put_hex:
    la      $a2,UART_BASE
    la      $a3,put_hex_table
    addi    $a1,-1
    add     $a1,$a1,$a1
    add     $a1,$a1,$a1
 
put_hex_loop:
    srlv    $v0,$a0,$a1
    andi    $v0,$v0,0x0f
    addu    $s2,$a3,$v0
    lb      $v0,0($s2)
put_hex_wait_tx_rdy:
    lw      $v1,UART_STATUS($a2)
    andi    $v1,$v1,0x02
    beqz    $v1,put_hex_wait_tx_rdy
    nop
    sw      $v0,UART_TX($a2)
 
    bnez    $a1,put_hex_loop
    addi    $a1,-4
 
    jr      $ra
    nop
 
 
#---- Constant data (note we keep it in the text section) ----------------------
 
put_hex_table:
    .ascii  "0123456789abcdef"
 
msg0:
    .ascii  "\n\r"
    .asciz  "Scanning external memory at 0x"
msg1:
    .asciz  "Found XRAM top at           0x"
crlf:
    .asciz "\n\r"
space:
    .asciz "  "
msg_mirror:
    .asciz "hit mirror!\n\r"
msg_bad:
    .asciz "bad readback!\n\r"
msg2:
    .asciz "\n\rDumping the first few words of FLASH at address 0x"
msg3:
    .ascii "\n\rTesting code execution from SRAM...  "
    .asciz "if you see this, it worked\n\r"
msg4:
    .ascii  "\n\r\n\r"
    .asciz  "End of test.\n\r\n\r"
msg5:
    .asciz  "Dump of first few words of XRAM after initialization:\n\r"
msg6:
    .asciiz ": "
msg7:
    .asciiz "<end of dump>"
msg8:
    .ascii  "\n\r"
    .asciiz "Testing execution from 8-bit static memory (FLASH)\n\r"
 
    .set    reorder
    .end    entry
 

Line No.	Rev	Author	Line
1	50	ja_rd	`################################################################################`
2			`# memtest.s -- Test external RAM memory (XRAM)`
3			`#-------------------------------------------------------------------------------`
4			`# This program tests the external RAM (connected to the core through the cache`
5	109	ja_rd	`# module). Currently it only finds the RAM top address if given the bottom`
6	50	ja_rd	`# address. Subsequent versions will add some minimal diagnostic capability,`
7			`# which will be needed when DRAM access is implemented.`
8			`#`
9			`# This program does only support a single continuous chunk of RAM. If the cache`
10	109	ja_rd	`# module ever supports more than one chunk (e.g. DRAM and SRAM as in the DE-1`
11	50	ja_rd	`# board) this program will be modified accordingly.`
12	109	ja_rd	`#`
13	50	ja_rd	`# The program assumes there's no useable r/w memory other than the XRAM so it`
14			`# does not use any memory for variables or stack.`
15	109	ja_rd	`#-------------------------------------------------------------------------------`
16	50	ja_rd	`#`
17	109	ja_rd	`#`
18			`#-------------------------------------------------------------------------------`
19	50	ja_rd	`# To be run from reset vector, standalone. Interrupts must be disabled.`
20			`#`
21			`################################################################################`
22
23	109	ja_rd	`#---- Test parameters`
24			`.ifndef XRAM_MAX`
25			`.set XRAM_MAX, 1024 # max. no. of KB to test for`
26			`.endif`
27			`.ifndef XRAM_BASE`
28			`.set XRAM_BASE, 0x00000000 # 1st XRAM address`
29			`.endif`
30
31
32	50	ja_rd	`#---- Set to >0 to enable a few debug messages`
33			`.set DEBUG, 0`
34
35	109	ja_rd	`#---- Cache parameters`
36			`.set ICACHE_NUM_LINES, 256 # no. of lines in the I-Cache`
37			`.set DCACHE_NUM_LINES, 256 # no. of lines in the D-Cache`
38			`.set DCACHE_LINE_SIZE, 4 # D-Cache line size in words`
39	50	ja_rd
40	109	ja_rd
41			`#---- UART stuff`
42	50	ja_rd	`.set UART_BASE, 0x20000000 # UART base address`
43			`.set UART_TX, 0x0000 # TX reg offset`
44			`.set UART_STATUS, 0x0020 # status reg offset`
45
46			`#---------------------------------------------------------------------------`
47
48			`.text`
49			`.align 2`
50			`.globl entry`
51			`.ent entry`
52			`entry:`
53			`.set noreorder`
54
55			`b start_test`
56			`nop`
57
58	66	ja_rd	`.ifgt 0`
59	50	ja_rd	`#--- Trap handler address: we don't expect any traps -----------------------`
60	66	ja_rd	`.org 0x0180`
61	50	ja_rd	`interrupt_vector:`
62	109	ja_rd	`b interrupt_vector # just freeze there`
63	50	ja_rd	`nop`
64	66	ja_rd	`.endif`
65	109	ja_rd
66	50	ja_rd	`#-------------------------------------------------------------------------------`
67
68	109	ja_rd	`start_test:`
69	152	ja_rd	`li $a0,0x00000002`
70			`mtc0 $a0,$12 # disable interrupts and cache`
71	109	ja_rd
72			`.ifdef TEST_CACHE # if we're going to test the I-caches then`
73			`jal init_cache # invalidate all the I-Cache lines now`
74			`nop`
75			`.endif`
76
77	50	ja_rd	`la $a0,msg0`
78			`jal puts`
79			`nop`
80			`li $a0,XRAM_BASE`
81			`li $a1,8`
82			`jal put_hex`
83			`nop`
84			`la $a0,crlf`
85			`jal puts`
86			`nop`
87	109	ja_rd
88	66	ja_rd	`la $t0,XRAM_BASE+4 # address of memory word being tested`
89	50	ja_rd	`li $t2,XRAM_MAX # max amount of KBs to test for`
90			`li $t3,1 # (used to decrement $t2)`
91			`li $t4,0 # no. of KBs found`
92			`move $t5,$t0 # keep the start addr at hand for comparison`
93	109	ja_rd
94	50	ja_rd	`sw $zero,0($t0) # clear 1st test word (in case of prev. run)`
95	109	ja_rd
96	50	ja_rd	`test_loop:`
97			`lw $t1,0($t0) # read word contents`
98			`beq $t5,$t1,hit_mirror # if it's the start address, we hit a mirror`
99			`nop # we rolled off the end of the RAM back here`
100			`sw $t0,0($t0) # word = word address`
101			`lw $t1,0($t0) # read word back...`
102			`bne $t1,$t0,bad_word # ...and if no match, we run off the RAM`
103	109	ja_rd	`nop #`
104	50	ja_rd	`sub $t2,$t2,$t3 # decrement loop counter...`
105			`bnez $t2,test_loop # ...and go back if there's more to go`
106			`addiu $t0,0x400 # in any case, increment test address by 1KB`
107	109	ja_rd
108	50	ja_rd	`b end_test # end of memory found, result is in $t4`
109			`nop`
110	109	ja_rd
111	50	ja_rd	`hit_mirror: # memory mirror detected`
112			`.ifgt DEBUG`
113			`la $a0,msg_mirror`
114			`jal puts`
115			`nop`
116			`.endif`
117			`b end_test`
118			`nop`
119	109	ja_rd
120	50	ja_rd	`bad_word: # readback error detected (maybe r/o area?)`
121			`.ifgt DEBUG`
122			`la $a0,msg_bad`
123			`jal puts`
124			`nop`
125			`.endif`
126			`b end_test`
127			`nop`
128
129	78	ja_rd	`end_test: # test done, ramtop+4 in $t0, #KB in $t4`
130
131	109	ja_rd
132	50	ja_rd	`la $a0,msg1 # Print ramtop message...`
133			`jal puts`
134			`nop`
135	109	ja_rd
136	66	ja_rd	`addi $a0,$t0,-4 # substract the +4 offset we added before`
137	78	ja_rd	`move $sp,$t0 # init SP at the top of RAM space`
138	90	ja_rd	`addi $sp,$sp,-16`
139	50	ja_rd	`li $a1,8`
140			`jal put_hex`
141			`nop`
142			`la $a0,crlf`
143			`jal puts`
144			`nop`
145	109	ja_rd
146			`# Clear RAM (only first words, so that simulation is not eternal)`
147			`.ifgt 1`
148			`li $a0,XRAM_BASE`
149			`addi $a1,$a0,80*4`
150			`clear_xram_loop:`
151			`sw $zero,0($a0)`
152			`blt $a0,$a1,clear_xram_loop`
153			`addi $a0,$a0,4`
154			`.endif`
155
156			`# Test code execution from SRAM. We copy the test_exec_sram routine to`
157	90	ja_rd	`# the base of the SRAM and then jal to it`
158			`li $a1,64`
159			`li $a0,XRAM_BASE`
160			`la $a3,test_exec_sram`
161			`copy_to_sram:`
162			`lw $a2,0($a3)`
163			`nop`
164			`sw $a2,0($a0)`
165			`addi $a1,$a1,-4`
166			`addi $a3,$a3,4`
167			`bnez $a1,copy_to_sram`
168			`addi $a0,$a0,4`
169	109	ja_rd
170			`# Optionally dump first few words of XRAM and jump onto XRAM`
171			`.ifgt 1`
172			`la $a0,msg5`
173			`jal puts`
174			`nop`
175			`li $a0,XRAM_BASE`
176	90	ja_rd	`jal dump_hex`
177	109	ja_rd	`ori $a1,$zero,20`
178	90	ja_rd	`.endif`
179	109	ja_rd
180			`.ifgt 1`
181	90	ja_rd	`li $a0,XRAM_BASE`
182	109	ja_rd	`nop`
183	90	ja_rd	`jalr $a0`
184			`nop`
185	109	ja_rd	`.endif`
186
187			`# If all went well in the SRAM we'll have returned here`
188	90	ja_rd	`.ifgt 0`
189	109	ja_rd	`# FIXME now we should do some strong test on the RAM to see if it's wired`
190	78	ja_rd	`# correctly, using the right timing, etc.`
191	109	ja_rd
192	78	ja_rd	`# Ok, now we know we have some RAM and stack space we can do some further`
193			`# testing.`
194			`# dump the first few words of FLASH`
195	109	ja_rd
196	78	ja_rd	`la $a0,msg2`
197			`jal puts`
198			`nop`
199	109	ja_rd
200	78	ja_rd	`# FIXME flash base address is hardcoded`
201			`li $a0,0xb0000000`
202			`jal put_hex`
203			`ori $a1,$zero,8`
204	109	ja_rd
205	78	ja_rd	`la $a0,crlf`
206			`jal puts`
207			`nop`
208
209			`la $a0,crlf`
210			`jal puts`
211			`nop`
212	109	ja_rd
213	78	ja_rd	`li $a0,0xb0000000`
214			`jal dump_hex`
215	109	ja_rd	`ori $a1,$zero,6`
216	90	ja_rd	`.endif`
217	109	ja_rd
218
219			`# Optionally jump to FLASH. This is only useful in simulation.`
220			`.ifgt 1`
221			`.ifdef EXEC_FLASH`
222			`la $a0,msg8`
223			`jal puts`
224			`nop`
225			`li $a0,0xb0000000`
226			`nop`
227			`jalr $a0`
228			`nop`
229			`.endif`
230			`.endif`
231
232			`la $a0,msg4`
233			`jal puts`
234			`nop`
235
236
237	50	ja_rd	`$DONE:`
238			`j $DONE # ...and freeze here`
239			`nop`
240
241
242	109	ja_rd	`# This short routine will be copied to RAM and then executed there. This`
243			`# will test the behavior of the I-Cache.`
244	90	ja_rd	`test_exec_sram:`
245			`#jr $ra`
246			`#nop`
247			`sw $ra,0($sp)`
248			`addi $sp,$sp,-4`
249			`la $a0,msg3`
250			`la $a1,puts`
251			`jalr $a1`
252			`nop`
253			`lw $ra,4($sp)`
254			`jr $ra`
255			`addi $sp,$sp,4`
256			`test_exec_sram_end:`
257	109	ja_rd	`nop`
258	90	ja_rd
259
260
261	50	ja_rd	`#---- Functions ----------------------------------------------------------------`
262	78	ja_rd
263	109	ja_rd	`# void dump_hex(int *address {a0}, int len {a1})`
264	78	ja_rd	`dump_hex:`
265			`move $t7,$a0`
266	109	ja_rd	`move $t6,$a1`
267	78	ja_rd	`sw $ra,0($sp)`
268			`addi $sp,$sp,-4`
269	109	ja_rd
270			`dump_hex_loop_lines:`
271			`move $a0,$t7`
272			`li $a1,8`
273			`jal put_hex`
274			`nop`
275			`la $a0,msg6`
276			`jal puts`
277			`nop`
278			`li $t9,4`
279
280			`dump_hex_loop_words:`
281	78	ja_rd	`lw $a0,0($t7)`
282			`jal put_hex`
283			`li $a1,8`
284	109	ja_rd
285	78	ja_rd	`la $a0,space`
286			`jal puts`
287			`addi $t7,4`
288	109	ja_rd
289			`addi $t9,$t9,-1`
290			`bnez $t9,dump_hex_loop_words`
291	78	ja_rd	`nop`
292	109	ja_rd
293			`la $a0,crlf`
294			`jal puts`
295			`nop`
296
297			`addi $t6,$t6,-1`
298			`bnez $t6,dump_hex_loop_lines`
299			`nop`
300
301			`la $a0,msg7`
302			`jal puts`
303			`addi $t7,4`
304
305			`.ifgt 0`
306	78	ja_rd	`lw $ra,4($sp)`
307	109	ja_rd	`move $a0,$ra`
308			`li $a1,8`
309			`jal put_hex`
310			`nop`
311			`qqqq:`
312			`j qqqq`
313			`nop`
314			`.endif`
315
316			`nop`
317			`lw $ra,4($sp)`
318	78	ja_rd	`jr $ra`
319			`addi $sp,$sp,4`
320
321
322	109	ja_rd	`#---- Cache-related functions --------------------------------------------------`
323
324			`# void init_cache(void) -- invalidates all I-Cache lines (uses no RAM)`
325			`init_cache:`
326			`li $a0,0x00010000 # Disable cache, enable I-cache line invalidation`
327	152	ja_rd	`mfc0 $a1,$12`
328			`or $a0,$a0,$a1`
329	109	ja_rd	`mtc0 $a0,$12`
330
331			`# In order to invalidate a I-Cache line we have to write its tag number to`
332			`# any address while bits CP0[12].17:16=01. The write will be executed as a`
333			`# regular write too, as a side effect, so we need to choose a harmless`
334			`# target address.`
335
336			`li $a0,XRAM_BASE`
337			`li $a2,0`
338			`li $a1,ICACHE_NUM_LINES-1`
339
340			`inv_i_cache_loop:`
341			`sw $a2,0($a0)`
342			`blt $a2,$a1,inv_i_cache_loop`
343			`addi $a2,1`
344
345			`mfc0 $a0,$12`
346			`li $a1,0x00020000 # Leave cache enabled`
347	152	ja_rd	`or $a0,$a0,$a1`
348	109	ja_rd	`jr $ra`
349			`mtc0 $a0,$12`
350
351
352
353	78	ja_rd	`#--- Special functions that do not use any RAM ---------------------------------`
354	50	ja_rd	`# WARNING: Not for general use!`
355			`# All parameters in $a0..$a4, stack unused. No attempt to comply with any ABI`
356			`# has been made.`
357	109	ja_rd	`# Since we can't use any RAM, registers have been used with no regard for`
358			`# intended usage -- have to share reg bank with calling function.`
359
360	50	ja_rd	`# void puts(char *s) -- print zero-terminated string`
361	109	ja_rd	`puts:`
362	78	ja_rd	`la $a2,UART_BASE # UART base address`
363	50	ja_rd	`puts_loop:`
364			`lb $v0,0($a0)`
365			`beqz $v0,puts_end`
366			`addiu $a0,1`
367	109	ja_rd	`puts_wait_tx_rdy:`
368	78	ja_rd	`lw $v1,UART_STATUS($a2)`
369	50	ja_rd	`andi $v1,$v1,0x02`
370			`beqz $v1,puts_wait_tx_rdy`
371			`nop`
372	78	ja_rd	`sw $v0,UART_TX($a2)`
373	50	ja_rd	`b puts_loop`
374			`nop`
375	109	ja_rd
376	50	ja_rd	`puts_end:`
377			`jr $ra`
378	109	ja_rd	`nop`
379	50	ja_rd
380			`# void put_hex(int n, int d) -- print integer as d-digit hex`
381			`put_hex:`
382	78	ja_rd	`la $a2,UART_BASE`
383			`la $a3,put_hex_table`
384	50	ja_rd	`addi $a1,-1`
385			`add $a1,$a1,$a1`
386			`add $a1,$a1,$a1`
387
388			`put_hex_loop:`
389			`srlv $v0,$a0,$a1`
390			`andi $v0,$v0,0x0f`
391	78	ja_rd	`addu $s2,$a3,$v0`
392	50	ja_rd	`lb $v0,0($s2)`
393			`put_hex_wait_tx_rdy:`
394	78	ja_rd	`lw $v1,UART_STATUS($a2)`
395	50	ja_rd	`andi $v1,$v1,0x02`
396			`beqz $v1,put_hex_wait_tx_rdy`
397			`nop`
398	78	ja_rd	`sw $v0,UART_TX($a2)`
399	109	ja_rd
400	50	ja_rd	`bnez $a1,put_hex_loop`
401			`addi $a1,-4`
402
403			`jr $ra`
404			`nop`
405
406	109	ja_rd
407	50	ja_rd	`#---- Constant data (note we keep it in the text section) ----------------------`
408
409			`put_hex_table:`
410			`.ascii "0123456789abcdef"`
411
412	109	ja_rd	`msg0:`
413	50	ja_rd	`.ascii "\n\r"`
414			`.asciz "Scanning external memory at 0x"`
415			`msg1:`
416			`.asciz "Found XRAM top at 0x"`
417			`crlf:`
418			`.asciz "\n\r"`
419			`space:`
420			`.asciz " "`
421			`msg_mirror:`
422			`.asciz "hit mirror!\n\r"`
423			`msg_bad:`
424			`.asciz "bad readback!\n\r"`
425	78	ja_rd	`msg2:`
426			`.asciz "\n\rDumping the first few words of FLASH at address 0x"`
427	90	ja_rd	`msg3:`
428			`.ascii "\n\rTesting code execution from SRAM... "`
429			`.asciz "if you see this, it worked\n\r"`
430	109	ja_rd	`msg4:`
431			`.ascii "\n\r\n\r"`
432			`.asciz "End of test.\n\r\n\r"`
433			`msg5:`
434			`.asciz "Dump of first few words of XRAM after initialization:\n\r"`
435			`msg6:`
436			`.asciiz ": "`
437			`msg7:`
438			`.asciiz "<end of dump>"`
439			`msg8:`
440			`.ascii "\n\r"`
441			`.asciiz "Testing execution from 8-bit static memory (FLASH)\n\r"`
442
443	50	ja_rd	`.set reorder`
444			`.end entry`
445	109	ja_rd

Browse

Tools

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [memtest/] [memtest.s] - Blame information for rev 190