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1 122 ja_rd
--##############################################################################
2
-- This file was generated automatically from '/src/mips_tb0_template.vhdl'.
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-- 
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--------------------------------------------------------------------------------
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-- Simulation test bench TB0 -- not synthesizable.
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--
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-- Simulates the CPU core connected to a single memory block initialized with
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-- the program object code and (initialized) data. The makefile for the source 
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-- samples include targets to build simulation test benches using this template.
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--
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-- The memory setup is meant to test the 'bare' cpu, without cache and with 
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-- all object code in a single 3-port memory block. 
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-- Address decoding is harcoded to that of Plasma system, for the time being.
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-- 
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-- Console output (at addresses compatible to Plasma's) is logged to text file
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-- "hw_sim_console_log.txt".
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-- IMPORTANT: The code that echoes UART TX data to the simulation console does
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-- line buffering; it will not print anything until it gets a CR (0x0d), and
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-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you 
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-- expect it.
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--
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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--##############################################################################
24 162 ja_rd
-- Copyright (C) 2011 Jose A. Ruiz
25 161 ja_rd
--                                                              
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-- This source file may be used and distributed without         
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-- restriction provided that this copyright statement is not    
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-- removed from the file and that any derivative work contains  
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-- the original copyright notice and the associated disclaimer. 
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--                                                              
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-- This source file is free software; you can redistribute it   
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-- and/or modify it under the terms of the GNU Lesser General   
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-- Public License as published by the Free Software Foundation; 
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-- either version 2.1 of the License, or (at your option) any   
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-- later version.                                               
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--                                                              
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-- This source is distributed in the hope that it will be       
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-- useful, but WITHOUT ANY WARRANTY; without even the implied   
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
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-- PURPOSE.  See the GNU Lesser General Public License for more 
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-- details.                                                     
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--                                                              
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-- You should have received a copy of the GNU Lesser General    
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-- Public License along with this source; if not, download it   
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-- from http://www.opencores.org/lgpl.shtml
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--##############################################################################
47 122 ja_rd
 
48
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.mips_pkg.all;
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use work.mips_tb_pkg.all;
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use work.txt_util.all;
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58
 
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entity @entity_name@ is
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end @entity_name@;
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architecture @arch_name@ of @entity_name@ is
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--------------------------------------------------------------------------------
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-- Simulation parameters
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-- Master clock period
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constant T : time           := 20 ns;
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-- Time the UART is unavailable after writing to the TX register
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-- WARNING: slite does not simulate this. The logs may be different when > 0.0!
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constant SIMULATED_UART_TX_TIME : time := 0.0 us;
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-- Simulation length in clock cycles 
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-- 2000 is enough for 'hello' sample, 22000 enough for 10 digits of pi
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constant SIMULATION_LENGTH : integer := @sim_len@;
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77
 
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--------------------------------------------------------------------------------
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-- UUT & interface signals
80
 
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signal data_addr :          std_logic_vector(31 downto 0);
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signal prev_rd_addr :       std_logic_vector(31 downto 0);
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signal vma_data :           std_logic;
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signal vma_code :           std_logic;
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signal full_rd_addr :       std_logic_vector(31 downto 0);
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signal full_wr_addr :       std_logic_vector(31 downto 0);
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signal byte_we :            std_logic_vector(3 downto 0);
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signal data_r :             std_logic_vector(31 downto 0);
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signal data_ram :           std_logic_vector(31 downto 0);
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signal data_uart :          std_logic_vector(31 downto 0);
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signal data_uart_status :   std_logic_vector(31 downto 0);
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signal uart_tx_rdy :        std_logic := '1';
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signal uart_rx_rdy :        std_logic := '1';
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signal data_w :             std_logic_vector(31 downto 0);
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signal mem_wait :           std_logic := '0';
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signal interrupt :          std_logic := '0';
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signal code_addr :          std_logic_vector(31 downto 2);
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signal full_code_addr :     std_logic_vector(31 downto 0);
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signal code_r :             std_logic_vector(31 downto 0);
100
 
101
--------------------------------------------------------------------------------
102
 
103
signal clk :                std_logic := '0';
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signal reset :              std_logic := '1';
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signal done :               std_logic := '0';
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signal test :               integer := 0;
107
 
108
--------------------------------------------------------------------------------
109
-- Logging signals
110
 
111
-- These are internal CPU signal mirrored using Modelsim's SignalSpy
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--signal rbank :              t_rbank;
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--signal pc, cp0_epc :        std_logic_vector(31 downto 2);
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--signal reg_hi, reg_lo :     t_word;
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--signal negate_reg_lo :      std_logic;
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--signal ld_upper_byte :      std_logic;
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--signal ld_upper_hword :     std_logic;
118
 
119
signal log_info :           t_log_info;
120
 
121
-- Log file
122
file log_file: TEXT open write_mode is "hw_sim_log.txt";
123
 
124
-- Console output log file
125
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
126
 
127
-- Maximum line size of for console output log. Lines longer than this will be
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-- truncated.
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constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
130
 
131
-- Console log line buffer
132
signal con_line_buf :       string(1 to CONSOLE_LOG_LINE_SIZE);
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signal con_line_ix :        integer := 1;
134
 
135
 
136
--------------------------------------------------------------------------------
137
 
138
constant MEM_SIZE : integer := @code_table_size@;
139
constant ADDR_SIZE : integer := @code_addr_size@;
140
 
141
subtype t_address is std_logic_vector(ADDR_SIZE-1 downto 0);
142
 
143
signal addr_rd, addr_wr :   t_address;
144
signal addr_code :          t_address;
145
 
146
type t_code_ram is array(0 to MEM_SIZE-1) of std_logic_vector(7 downto 0);
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148
subtype t_data_address is std_logic_vector(ADDR_SIZE-1 downto 0);
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signal data_addr_rd :       t_data_address;
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signal data_addr_wr :       t_data_address;
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signal code_addr_rd :       t_data_address;
152
 
153
 
154
-- ram0 is LSB, ram3 is MSB
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signal ram3 : t_code_ram := (@code3@);
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signal ram2 : t_code_ram := (@code2@);
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signal ram1 : t_code_ram := (@code1@);
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signal ram0 : t_code_ram := (@code0@);
159
 
160
begin
161
 
162
    cpu: entity work.mips_cpu
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    port map (
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        interrupt   => interrupt,
165
 
166
        data_addr   => data_addr,
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        data_rd_vma => vma_data,
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        data_rd     => data_r,
169
 
170
        code_rd_addr=> code_addr,
171
        code_rd     => code_r,
172
        code_rd_vma => vma_code,
173
 
174
        data_wr     => data_w,
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        byte_we     => byte_we,
176
 
177
        mem_wait    => mem_wait,
178
 
179
        clk         => clk,
180
        reset       => reset
181
    );
182
 
183
    ---------------------------------------------------------------------------
184
    -- Master clock: free running clock used as main module clock
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    run_master_clock:
186
    process(done, clk)
187
    begin
188
        if done = '0' then
189
            clk <= not clk after T/2;
190
        end if;
191
    end process run_master_clock;
192
 
193
    drive_uut:
194
    process
195
    variable l : line;
196
    begin
197
        wait for T*4;
198
        reset <= '0';
199
 
200
        wait for T*SIMULATION_LENGTH;
201
 
202
        -- Flush console output to log console file (in case the end of the
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        -- simulation caugh an unterminated line in the buffer)
204
        if con_line_ix > 1 then
205
            write(l, con_line_buf(1 to con_line_ix));
206
            writeline(con_file, l);
207
        end if;
208
 
209
        print("TB0 finished");
210
        done <= '1';
211
        wait;
212
 
213
    end process drive_uut;
214
 
215
    mem_wait <= '0'; -- memory wait input not simulated in this test bench
216
 
217
 
218
    -- RAM vs. IO data read mux
219
    data_r <= data_ram when prev_rd_addr(31 downto 28)/=X"2" else data_uart;
220
 
221
    -- UART read registers; only status, and hardwired, for the time being
222
    data_uart <= data_uart_status;
223
    data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
224
 
225
 
226
    -- 'full' read address, used for simulation display only
227
    full_rd_addr <= data_addr;
228
    full_wr_addr <= data_addr(31 downto 2) & "00";
229
    full_code_addr <= code_addr & "00";
230
 
231
    data_addr_rd <= full_rd_addr(ADDR_SIZE-1+2 downto 2);
232
    addr_wr <= full_wr_addr(ADDR_SIZE-1+2 downto 2);
233
    code_addr_rd <= full_code_addr(ADDR_SIZE-1+2 downto 2);
234
 
235
 
236
    write_process:
237
    process(clk)
238
    variable i : integer;
239
    variable uart_data : integer;
240
    begin
241
        if clk'event and clk='1' then
242
            if reset='1' then
243
                data_ram <= (others =>'0');
244
            else
245
                prev_rd_addr <= data_addr;
246
 
247
                data_ram <=
248
                  ram3(conv_integer(unsigned(data_addr_rd))) &
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                  ram2(conv_integer(unsigned(data_addr_rd))) &
250
                  ram1(conv_integer(unsigned(data_addr_rd))) &
251
                  ram0(conv_integer(unsigned(data_addr_rd)));
252
 
253
                code_r <=
254
                  ram3(conv_integer(unsigned(code_addr_rd))) &
255
                  ram2(conv_integer(unsigned(code_addr_rd))) &
256
                  ram1(conv_integer(unsigned(code_addr_rd))) &
257
                  ram0(conv_integer(unsigned(code_addr_rd)));
258
            end if;
259
 
260
            if byte_we/="0000" then
261
                if full_wr_addr(31 downto 28)=X"2" then
262
                    -- Write to UART
263
 
264
                    -- If we're simulating the UART TX time, pulse RDY low
265
                    if SIMULATED_UART_TX_TIME > 0 us then
266
                        uart_tx_rdy <= '0', '1' after SIMULATED_UART_TX_TIME;
267
                    end if;
268
 
269
                    -- TX data may come from the high or low byte (opcodes.s
270
                    -- uses high byte, no_op.c uses low)
271
                    if byte_we(0)='1' then
272
                        uart_data := conv_integer(unsigned(data_w(7 downto 0)));
273
                    else
274
                        uart_data := conv_integer(unsigned(data_w(31 downto 24)));
275
                    end if;
276
 
277
                    -- UART TX data goes to output after a bit of line-buffering
278
                    -- and editing
279
                    if uart_data = 10 then
280
                        -- CR received: print output string and clear it
281
                        print(con_file, con_line_buf(1 to con_line_ix));
282
                        con_line_ix <= 1;
283
                        for i in 1 to con_line_buf'high loop
284
                           con_line_buf(i) <= ' ';
285
                        end loop;
286
                    elsif uart_data = 13 then
287
                        -- ignore LF
288
                    else
289
                        -- append char to output string
290
                        if con_line_ix < con_line_buf'high then
291
                            con_line_buf(con_line_ix) <= character'val(uart_data);
292
                            con_line_ix <= con_line_ix + 1;
293
                        end if;
294
                    end if;
295
                else
296
                    -- Write to RAM
297
                    if byte_we(3)='1' then
298
                        ram3(conv_integer(unsigned(addr_wr))) <= data_w(31 downto 24);
299
                    end if;
300
                    if byte_we(2)='1' then
301
                        ram2(conv_integer(unsigned(addr_wr))) <= data_w(23 downto 16);
302
                    end if;
303
                    if byte_we(1)='1' then
304
                        ram1(conv_integer(unsigned(addr_wr))) <= data_w(15 downto  8);
305
                    end if;
306
                    if byte_we(0)='1' then
307
                        ram0(conv_integer(unsigned(addr_wr))) <= data_w( 7 downto  0);
308
                    end if;
309
                end if;
310
            end if;
311
        end if;
312
    end process write_process;
313
 
314
    log_execution:
315
    process
316
    begin
317
        log_cpu_activity(clk, reset, done,
318
                         "@entity_name@/cpu", log_info, "log_info",
319
                         @log_trigger_addr@, log_file);
320
        wait;
321
    end process log_execution;
322
 
323
 
324
end @arch_name@;

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