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--##############################################################################
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-- This file was generated automatically from '/src/mips_tb0_template.vhdl'.
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--
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--------------------------------------------------------------------------------
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-- Simulation test bench TB0 -- not synthesizable.
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--
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-- Simulates the CPU core connected to a single memory block initialized with
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-- the program object code and (initialized) data. The makefile for the source
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-- samples include targets to build simulation test benches using this template.
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--
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-- The memory setup is meant to test the 'bare' cpu, without cache and with
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-- all object code in a single 3-port memory block.
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-- Address decoding is harcoded to that of Plasma system, for the time being.
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--
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-- Console output (at addresses compatible to Plasma's) is logged to text file
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-- "hw_sim_console_log.txt".
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-- IMPORTANT: The code that echoes UART TX data to the simulation console does
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-- line buffering; it will not print anything until it gets a CR (0x0d), and
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-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you
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-- expect it.
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--
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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--##############################################################################
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162 |
ja_rd |
-- Copyright (C) 2011 Jose A. Ruiz
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161 |
ja_rd |
--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--##############################################################################
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ja_rd |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.mips_pkg.all;
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use work.mips_tb_pkg.all;
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use work.txt_util.all;
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entity @entity_name@ is
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end @entity_name@;
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architecture @arch_name@ of @entity_name@ is
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--------------------------------------------------------------------------------
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-- Simulation parameters
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-- Master clock period
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constant T : time := 20 ns;
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-- Time the UART is unavailable after writing to the TX register
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-- WARNING: slite does not simulate this. The logs may be different when > 0.0!
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constant SIMULATED_UART_TX_TIME : time := 0.0 us;
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-- Simulation length in clock cycles
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-- 2000 is enough for 'hello' sample, 22000 enough for 10 digits of pi
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constant SIMULATION_LENGTH : integer := @sim_len@;
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--------------------------------------------------------------------------------
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-- UUT & interface signals
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signal data_addr : std_logic_vector(31 downto 0);
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signal prev_rd_addr : std_logic_vector(31 downto 0);
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signal vma_data : std_logic;
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signal vma_code : std_logic;
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signal full_rd_addr : std_logic_vector(31 downto 0);
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signal full_wr_addr : std_logic_vector(31 downto 0);
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signal byte_we : std_logic_vector(3 downto 0);
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signal data_r : std_logic_vector(31 downto 0);
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signal data_ram : std_logic_vector(31 downto 0);
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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signal data_w : std_logic_vector(31 downto 0);
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signal mem_wait : std_logic := '0';
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signal interrupt : std_logic := '0';
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signal code_addr : std_logic_vector(31 downto 2);
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signal full_code_addr : std_logic_vector(31 downto 0);
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signal code_r : std_logic_vector(31 downto 0);
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--------------------------------------------------------------------------------
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal done : std_logic := '0';
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signal test : integer := 0;
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--------------------------------------------------------------------------------
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-- Logging signals
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-- These are internal CPU signal mirrored using Modelsim's SignalSpy
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--signal rbank : t_rbank;
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--signal pc, cp0_epc : std_logic_vector(31 downto 2);
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--signal reg_hi, reg_lo : t_word;
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--signal negate_reg_lo : std_logic;
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--signal ld_upper_byte : std_logic;
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--signal ld_upper_hword : std_logic;
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signal log_info : t_log_info;
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-- Log file
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file log_file: TEXT open write_mode is "hw_sim_log.txt";
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-- Console output log file
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file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
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-- Maximum line size of for console output log. Lines longer than this will be
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-- truncated.
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constant CONSOLE_LOG_LINE_SIZE : integer := 1024*4;
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-- Console log line buffer
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signal con_line_buf : string(1 to CONSOLE_LOG_LINE_SIZE);
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signal con_line_ix : integer := 1;
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--------------------------------------------------------------------------------
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constant MEM_SIZE : integer := @code_table_size@;
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constant ADDR_SIZE : integer := @code_addr_size@;
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subtype t_address is std_logic_vector(ADDR_SIZE-1 downto 0);
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signal addr_rd, addr_wr : t_address;
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signal addr_code : t_address;
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type t_code_ram is array(0 to MEM_SIZE-1) of std_logic_vector(7 downto 0);
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subtype t_data_address is std_logic_vector(ADDR_SIZE-1 downto 0);
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signal data_addr_rd : t_data_address;
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signal data_addr_wr : t_data_address;
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signal code_addr_rd : t_data_address;
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-- ram0 is LSB, ram3 is MSB
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signal ram3 : t_code_ram := (@code3@);
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signal ram2 : t_code_ram := (@code2@);
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signal ram1 : t_code_ram := (@code1@);
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signal ram0 : t_code_ram := (@code0@);
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begin
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cpu: entity work.mips_cpu
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port map (
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interrupt => interrupt,
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data_addr => data_addr,
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data_rd_vma => vma_data,
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data_rd => data_r,
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code_rd_addr=> code_addr,
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code_rd => code_r,
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code_rd_vma => vma_code,
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data_wr => data_w,
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byte_we => byte_we,
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mem_wait => mem_wait,
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clk => clk,
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reset => reset
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);
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---------------------------------------------------------------------------
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-- Master clock: free running clock used as main module clock
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run_master_clock:
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process(done, clk)
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begin
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if done = '0' then
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clk <= not clk after T/2;
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end if;
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end process run_master_clock;
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drive_uut:
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process
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variable l : line;
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begin
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wait for T*4;
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reset <= '0';
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wait for T*SIMULATION_LENGTH;
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-- Flush console output to log console file (in case the end of the
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-- simulation caugh an unterminated line in the buffer)
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if con_line_ix > 1 then
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write(l, con_line_buf(1 to con_line_ix));
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writeline(con_file, l);
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end if;
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print("TB0 finished");
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done <= '1';
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wait;
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end process drive_uut;
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mem_wait <= '0'; -- memory wait input not simulated in this test bench
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-- RAM vs. IO data read mux
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data_r <= data_ram when prev_rd_addr(31 downto 28)/=X"2" else data_uart;
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-- UART read registers; only status, and hardwired, for the time being
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data_uart <= data_uart_status;
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data_uart_status <= X"0000000" & "00" & uart_tx_rdy & uart_rx_rdy;
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-- 'full' read address, used for simulation display only
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full_rd_addr <= data_addr;
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full_wr_addr <= data_addr(31 downto 2) & "00";
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full_code_addr <= code_addr & "00";
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data_addr_rd <= full_rd_addr(ADDR_SIZE-1+2 downto 2);
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addr_wr <= full_wr_addr(ADDR_SIZE-1+2 downto 2);
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code_addr_rd <= full_code_addr(ADDR_SIZE-1+2 downto 2);
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write_process:
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process(clk)
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variable i : integer;
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variable uart_data : integer;
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begin
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if clk'event and clk='1' then
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if reset='1' then
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data_ram <= (others =>'0');
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else
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prev_rd_addr <= data_addr;
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data_ram <=
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ram3(conv_integer(unsigned(data_addr_rd))) &
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ram2(conv_integer(unsigned(data_addr_rd))) &
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ram1(conv_integer(unsigned(data_addr_rd))) &
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ram0(conv_integer(unsigned(data_addr_rd)));
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code_r <=
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ram3(conv_integer(unsigned(code_addr_rd))) &
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ram2(conv_integer(unsigned(code_addr_rd))) &
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ram1(conv_integer(unsigned(code_addr_rd))) &
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ram0(conv_integer(unsigned(code_addr_rd)));
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end if;
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if byte_we/="0000" then
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if full_wr_addr(31 downto 28)=X"2" then
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-- Write to UART
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-- If we're simulating the UART TX time, pulse RDY low
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if SIMULATED_UART_TX_TIME > 0 us then
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uart_tx_rdy <= '0', '1' after SIMULATED_UART_TX_TIME;
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end if;
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-- TX data may come from the high or low byte (opcodes.s
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-- uses high byte, no_op.c uses low)
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if byte_we(0)='1' then
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uart_data := conv_integer(unsigned(data_w(7 downto 0)));
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else
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uart_data := conv_integer(unsigned(data_w(31 downto 24)));
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end if;
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-- UART TX data goes to output after a bit of line-buffering
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-- and editing
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if uart_data = 10 then
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-- CR received: print output string and clear it
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print(con_file, con_line_buf(1 to con_line_ix));
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con_line_ix <= 1;
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for i in 1 to con_line_buf'high loop
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con_line_buf(i) <= ' ';
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end loop;
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elsif uart_data = 13 then
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-- ignore LF
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else
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-- append char to output string
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if con_line_ix < con_line_buf'high then
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con_line_buf(con_line_ix) <= character'val(uart_data);
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con_line_ix <= con_line_ix + 1;
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end if;
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end if;
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else
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-- Write to RAM
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if byte_we(3)='1' then
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ram3(conv_integer(unsigned(addr_wr))) <= data_w(31 downto 24);
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end if;
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if byte_we(2)='1' then
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ram2(conv_integer(unsigned(addr_wr))) <= data_w(23 downto 16);
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end if;
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if byte_we(1)='1' then
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ram1(conv_integer(unsigned(addr_wr))) <= data_w(15 downto 8);
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end if;
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if byte_we(0)='1' then
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ram0(conv_integer(unsigned(addr_wr))) <= data_w( 7 downto 0);
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end if;
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end if;
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end if;
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end if;
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end process write_process;
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log_execution:
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process
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begin
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log_cpu_activity(clk, reset, done,
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"@entity_name@/cpu", log_info, "log_info",
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@log_trigger_addr@, log_file);
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wait;
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end process log_execution;
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end @arch_name@;
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