OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [readme.txt] - Blame information for rev 212

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 183 ja_rd
Code samples:
2
=============
3
 
4 2 ja_rd
This directory contains a few test applications that can be simulated and run
5 183 ja_rd
on real hardware (except for the opcode test which can only be simulated). See
6 2 ja_rd
the readme file and the makefile for each program.
7
 
8
The makefiles have been tested with the CodeSourcery toolchain for windows (that
9 183 ja_rd
can be downloaded from www.codesourcery.com). They should work with other
10
toolchains and have been occasionally tested with the Buildroot toolchain
11 2 ja_rd
for GNU/Linux.
12
 
13
Most makefiles have two targets, to create a simulation test bench and a
14
synthesizable demo.
15
 
16 197 ja_rd
Target 'sim' will build a the simulation test bench package as vhdl file
17
'/vhdl/tb/sim_params_pkg.vhdl'. This is the default test bench expected by the
18
simulation script '/sim/mips_tb.do'. The template used to build the package is
19
file '/src/sim_params_template.pkg' and the tool used to insert the data into
20
the template is the python script '/src/bin2hdl.py'.
21 2 ja_rd
 
22 197 ja_rd
Target 'demo' will build a package for the synthesizable demo as file
23
'/vhdl/demo/code_rom_pkg.vhdl', from template file '/code_rom_template.vhdl',
24
using the same python script.
25 2 ja_rd
 
26 183 ja_rd
The build process will produce a number of binary files that can be run on the
27
software simulator. A DOS BATCH file has been provided for each sample that
28
runs the simulator with the proper parameters (swsim.bat).
29 2 ja_rd
 
30 197 ja_rd
The simulation log produced by the software simulator can be compared to the log
31
produced by Modelsim (the only hdl simulator supported yet); they should be
32
identical (but see notes on the project doc).
33 2 ja_rd
 
34 197 ja_rd
 
35
 
36 183 ja_rd
Support code library:
37
=====================
38 2 ja_rd
 
39 183 ja_rd
Many of the code samples use support code from an ad-hoc library included with
40
the project (src/common/libsoc). Before making any of the samples you should
41 197 ja_rd
make the library ('make' with no target). That command will build lib file
42 183 ja_rd
'src/common/libsoc/libsoc.a'.
43
 
44
 
45
 
46
Building VHDL code from templates:
47
==================================
48
 
49
The python script 'bin2hdl.py' is used by all the samples to insert binary data
50
on vhdl templates.
51 2 ja_rd
Assuming you have Python 2.5 or later in your machine, call the script with
52
 
53
    python bin2hdl.py --help
54
 
55 197 ja_rd
to get a short description and usage instructions.
56
There's a more detailed description in the project main doc (Well, I hope there
57
is one by the time you read this, documentation has been falling behind lately).

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.