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[/] [ion/] [trunk/] [tools/] [slite/] [src/] [slite.c] - Blame information for rev 13

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1 2 ja_rd
/*------------------------------------------------------------------------------
2
* slite.c -- MIPS-I simulator based on Steve Rhoad's "mlite"
3
*
4
* This is a slightly modified version of Steve Rhoad's "mlite" simulator, which
5
* is part of his PLASMA project (original date: 1/31/01).
6
*
7
*-------------------------------------------------------------------------------
8
* Usage:
9
*     slite <code file name> <data file name>
10
*
11
* The program will allocate a chunk of RAM (MEM_SIZE bytes) and map it to
12
* address 0x00000000 of the simulated CPU.
13
* Then it will read the 'code file' (as a big-endian plain binary) onto address
14
* 0x0 of the simulated CPU memory, and 'data file' on address 0x10000.
15
* Finally, will reset the CPU and enter the interactive debugger.
16
*
17
* (Note that the above is only necessary if the system does not have caches,
18
* because of the Harvard architecture. With caches in place, program loading
19
* would be antirely conventional).
20
*
21
* A simulation log file will be dumped to file "sw_sim_log.txt". This log can be
22
* used to compare with an equivalent log dumped by the hardware simulation, as
23
* a simple way to validate the hardware for a given program. See the project
24
* readme files for details.
25
*
26
*-------------------------------------------------------------------------------
27
* KNOWN BUGS:
28
*
29
* 1.- Load delay slot simulation does not work
30
*
31
* Some programs don't work when load delay slots are simulated (by setting
32
* "s->load_delay_slot = 1" in function main).
33
*
34
* The actual HW core does no longer use load delay slots but load interlocking
35
* so it may be better to just remove this feature.
36
*
37
*-------------------------------------------------------------------------------
38
* @date 2011-jan-16
39
*
40
*-------------------------------------------------------------------------------
41
* COPYRIGHT:    Software placed into the public domain by the author.
42
*               Software 'as is' without warranty.  Author liable for nothing.
43
*
44
* IMPORTANT: Assumes host is little endian.
45
*-----------------------------------------------------------------------------*/
46
 
47
#include <stdio.h>
48 11 ja_rd
#include <stdlib.h>
49
#include <stdint.h>
50 2 ja_rd
#include <string.h>
51
#include <ctype.h>
52
#include <assert.h>
53
 
54
/** Set to !=0 to disable file logging */
55
#define FILE_LOGGING_DISABLED (0)
56
/** Define to enable cache simulation (unimplemented) */
57
//#define ENABLE_CACHE
58
 
59
 
60
#define MEM_SIZE (1024*1024*2)
61
#define ntohs(A) ( ((A)>>8) | (((A)&0xff)<<8) )
62
#define htons(A) ntohs(A)
63
#define ntohl(A) ( ((A)>>24) | (((A)&0xff0000)>>8) | (((A)&0xff00)<<8) | ((A)<<24) )
64
#define htonl(A) ntohl(A)
65
 
66
/*---- OS-dependent support functions and definitions ------------------------*/
67
#ifndef WIN32
68
//Support for Linux
69
#define putch putchar
70
#include <termios.h>
71
#include <unistd.h>
72
 
73
void Sleep(unsigned int value)
74
{
75
   usleep(value * 1000);
76
}
77
 
78
int kbhit(void)
79
{
80
   struct termios oldt, newt;
81
   struct timeval tv;
82
   fd_set read_fd;
83
 
84
   tcgetattr(STDIN_FILENO, &oldt);
85
   newt = oldt;
86
   newt.c_lflag &= ~(ICANON | ECHO);
87
   tcsetattr(STDIN_FILENO, TCSANOW, &newt);
88
   tv.tv_sec=0;
89
   tv.tv_usec=0;
90
   FD_ZERO(&read_fd);
91
   FD_SET(0,&read_fd);
92
   if(select(1, &read_fd, NULL, NULL, &tv) == -1)
93
      return 0;
94
   //tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
95
   if(FD_ISSET(0,&read_fd))
96
      return 1;
97
   return 0;
98
}
99
 
100
int getch(void)
101
{
102
   struct termios oldt, newt;
103
   int ch;
104
 
105
   tcgetattr(STDIN_FILENO, &oldt);
106
   newt = oldt;
107
   newt.c_lflag &= ~(ICANON | ECHO);
108
   tcsetattr(STDIN_FILENO, TCSANOW, &newt);
109
   ch = getchar();
110
   //tcsetattr(STDIN_FILENO, TCSANOW, &oldt);
111
   return ch;
112
}
113
#else
114
//Support for Windows
115
#include <conio.h>
116
extern void __stdcall Sleep(unsigned long value);
117
#endif
118
/*---- End of OS-dependent support functions and definitions -----------------*/
119
 
120
/*---- Hardware system parameters --------------------------------------------*/
121
 
122
/* Much of this is a remnant from Plasma's mlite and is  no longer used. */
123
/* FIXME Refactor HW system params */
124
 
125
 
126
#define UART_WRITE        0x20000000
127
#define UART_READ         0x20000000
128
#define IRQ_MASK          0x20000010
129
#define IRQ_STATUS        0x20000020
130
#define CONFIG_REG        0x20000070
131
#define MMU_PROCESS_ID    0x20000080
132
#define MMU_FAULT_ADDR    0x20000090
133
#define MMU_TLB           0x200000a0
134
 
135
#define IRQ_UART_READ_AVAILABLE  0x001
136
#define IRQ_UART_WRITE_AVAILABLE 0x002
137
#define IRQ_COUNTER18_NOT        0x004
138
#define IRQ_COUNTER18            0x008
139
#define IRQ_MMU                  0x200
140
 
141
#define MMU_ENTRIES 4
142
#define MMU_MASK (1024*4-1)
143 5 ja_rd
/*----------------------------------------------------------------------------*/
144 2 ja_rd
 
145 5 ja_rd
/* These are flags that will be used to notify the main cycle function of any
146
   failed assertions in its subfunctions. */
147
#define ASRT_UNALIGNED_READ         (1<<0)
148
#define ASRT_UNALIGNED_WRITE        (1<<1)
149
 
150
char *assertion_messages[2] = {
151
   "Unaligned read",
152
   "Unaligned write"
153
};
154
 
155
 
156 2 ja_rd
/** Length of debugging jump target queue */
157
#define TRACE_BUFFER_SIZE (32)
158
 
159
typedef struct {
160
   unsigned int buf[TRACE_BUFFER_SIZE];   /**< queue of last jump targets */
161
   unsigned int next;                     /**< internal queue head pointer */
162
   FILE *log;                             /**< text log file or NULL */
163
   int pr[32];                            /**< last value of register bank */
164
   int hi, lo, epc;                       /**< last value of internal regs */
165
} Trace;
166
 
167
typedef struct
168
{
169
   unsigned int virtualAddress;
170
   unsigned int physicalAddress;
171
} MmuEntry;
172
 
173
typedef struct {
174
   int load_delay_slot;
175
   int delay;
176 5 ja_rd
   unsigned delayed_reg;
177
   int delayed_data;
178
 
179
   unsigned failed_assertions;            /**< assertion bitmap */
180
   unsigned faulty_address;               /**< addr that failed assertion */
181
 
182 2 ja_rd
   int r[32];
183
   int opcode;
184
   int pc, pc_next, epc;
185
   unsigned int hi;
186
   unsigned int lo;
187
   int status;
188
   int userMode;
189
   int processId;
190 5 ja_rd
   int exceptionId;        /**< DEPRECATED, to be removed */
191 2 ja_rd
   int faultAddr;
192
   int irqStatus;
193
   int skip;
194
   Trace t;
195
   unsigned char *mem;
196
   int wakeup;
197
   int big_endian;
198
   MmuEntry mmuEntry[MMU_ENTRIES];
199
} State;
200
 
201
static char *opcode_string[]={
202
   "SPECIAL","REGIMM","J","JAL","BEQ","BNE","BLEZ","BGTZ",
203
   "ADDI","ADDIU","SLTI","SLTIU","ANDI","ORI","XORI","LUI",
204
   "COP0","COP1","COP2","COP3","BEQL","BNEL","BLEZL","BGTZL",
205
   "?","?","?","?","?","?","?","?",
206
   "LB","LH","LWL","LW","LBU","LHU","LWR","?",
207
   "SB","SH","SWL","SW","?","?","SWR","CACHE",
208
   "LL","LWC1","LWC2","LWC3","?","LDC1","LDC2","LDC3"
209
   "SC","SWC1","SWC2","SWC3","?","SDC1","SDC2","SDC3"
210
};
211
 
212
static char *special_string[]={
213
   "SLL","?","SRL","SRA","SLLV","?","SRLV","SRAV",
214
   "JR","JALR","MOVZ","MOVN","SYSCALL","BREAK","?","SYNC",
215
   "MFHI","MTHI","MFLO","MTLO","?","?","?","?",
216
   "MULT","MULTU","DIV","DIVU","?","?","?","?",
217
   "ADD","ADDU","SUB","SUBU","AND","OR","XOR","NOR",
218
   "?","?","SLT","SLTU","?","DADDU","?","?",
219
   "TGE","TGEU","TLT","TLTU","TEQ","?","TNE","?",
220
   "?","?","?","?","?","?","?","?"
221
};
222
 
223
static char *regimm_string[]={
224
   "BLTZ","BGEZ","BLTZL","BGEZL","?","?","?","?",
225
   "TGEI","TGEIU","TLTI","TLTIU","TEQI","?","TNEI","?",
226
   "BLTZAL","BEQZAL","BLTZALL","BGEZALL","?","?","?","?",
227
   "?","?","?","?","?","?","?","?"
228
};
229
 
230
static unsigned int HWMemory[8];
231
 
232
/*---- Local function prototypes ---------------------------------------------*/
233
 
234
/* Debug and logging */
235
void init_trace_buffer(State *s, const char *log_file_name);
236
void close_trace_buffer(State *s);
237
void dump_trace_buffer(State *s);
238
void log_cycle(State *s);
239
void log_read(State *s, int full_address, int word_value, int size, int log);
240 5 ja_rd
void log_failed_assertions(State *s);
241 2 ja_rd
 
242
/* Hardware simulation */
243
int mem_read(State *s, int size, unsigned int address, int log);
244
void mem_write(State *s, int size, int unsigned address, unsigned value);
245
void start_load(State *s, int rt, int data);
246
 
247
/*---- Local functions -------------------------------------------------------*/
248
 
249
/** Log to file a memory read operation (not including target reg change) */
250
void log_read(State *s, int full_address, int word_value, int size, int log){
251
   if(s->t.log!=NULL && log!=0){
252
      if(size==4){ size=0x04; }
253
      else if(size==2){ size=0x02; }
254
      else { size=0x01; }
255
      fprintf(s->t.log, "(%08X) [%08X] <**>=%08X RD\n",
256
              s->pc, full_address, /*size,*/ word_value);
257
   }
258
}
259
 
260
/** Read memory, optionally logging */
261
int mem_read(State *s, int size, unsigned int address, int log)
262
{
263
   unsigned int value=0, word_value=0, ptr;
264
   unsigned int full_address = address;
265
 
266
   s->irqStatus |= IRQ_UART_WRITE_AVAILABLE;
267
   switch(address)
268
   {
269
      case UART_READ:
270
         word_value = 0x00000001;
271
         log_read(s, full_address, word_value, size, log);
272
         return word_value;
273
         /* FIXME Take input from text file */
274
         /*
275
         if(kbhit()){
276
            HWMemory[0] = getch();
277
         }
278
         s->irqStatus &= ~IRQ_UART_READ_AVAILABLE; //clear bit
279
         return HWMemory[0];
280
         */
281
      case IRQ_MASK:
282
         return HWMemory[1];
283
      case IRQ_MASK + 4:
284
         Sleep(10);
285
         return 0;
286
      case IRQ_STATUS:
287
         /*if(kbhit())
288
            s->irqStatus |= IRQ_UART_READ_AVAILABLE;
289
         return s->irqStatus;
290
         */
291
         /* FIXME Optionally simulate UART TX delay */
292
         word_value = 0x00000003; /* Ready to TX and RX */
293
         log_read(s, full_address, word_value, size, log);
294
         return word_value;
295
      case MMU_PROCESS_ID:
296
         return s->processId;
297
      case MMU_FAULT_ADDR:
298
         return s->faultAddr;
299
   }
300
 
301
   ptr = (unsigned int)s->mem + (address % MEM_SIZE);
302
 
303
   if(0x10000000 <= address && address < 0x10000000 + 1024*1024)
304
      ptr += 1024*1024;
305
 
306
   word_value = *(int*)(ptr&0xfffffffc);
307
   if(s->big_endian)
308
            word_value = ntohl(word_value);
309
   switch(size)
310
   {
311
      case 4:
312
         if(address & 3){
313
            printf("Unaligned access PC=0x%x address=0x%x\n",
314
                   (int)s->pc, (int)address);
315 5 ja_rd
         }
316
         /* We don't want the program to just quit, we want to log the fault */
317
         /* assert((address & 3) == 0); */
318
         if((address & 3) != 0){
319
            s->failed_assertions |= ASRT_UNALIGNED_READ;
320
            s->faulty_address = address;
321
            address = address & 0xfffffffc;
322 2 ja_rd
         }
323
         value = *(int*)ptr;
324
         if(s->big_endian)
325
            value = ntohl(value);
326
         break;
327 5 ja_rd
      case 2:
328
         /* We don't want the program to just quit, we want to log the fault */
329
         /* assert((address & 1) == 0); */
330
         if((address & 1) != 0){
331
            s->failed_assertions |= ASRT_UNALIGNED_READ;
332
            s->faulty_address = address;
333
            address = address & 0xfffffffe;
334
         }
335 2 ja_rd
         value = *(unsigned short*)ptr;
336
         if(s->big_endian)
337
            value = ntohs((unsigned short)value);
338
         break;
339
      case 1:
340
         value = *(unsigned char*)ptr;
341
         break;
342
      default:
343
         printf("ERROR");
344
   }
345
 
346
   log_read(s, full_address, word_value, size, log);
347
   return(value);
348
}
349
 
350
/** Write memory */
351
void mem_write(State *s, int size, unsigned address, unsigned value)
352
{
353
   unsigned int ptr, mask, dvalue, b0, b1, b2, b3;
354
 
355
   if(s->t.log!=NULL){
356
      b0 = value & 0x000000ff;
357
      b1 = value & 0x0000ff00;
358
      b2 = value & 0x00ff0000;
359
      b3 = value & 0xff000000;
360
 
361
      switch(size){
362
         case 4:  mask = 0x0f;
363
                  dvalue = value;
364
                  break;
365
 
366
         case 2:  if((address&0x2)==0){
367
                     mask = 0xc;
368
                     dvalue = b1<<16 | b0<<16;
369
                  }
370
                  else{
371
                     mask = 0x3;
372
                     dvalue = b1 | b0;
373
                  }
374
                  break;
375
         case 1:  switch(address%4){
376
                  case 0 : mask = 0x8;
377
                           dvalue = b0<<24;
378
                           break;
379
                  case 1 : mask = 0x4;
380
                           dvalue = b0<<16;
381
                           break;
382
                  case 2 : mask = 0x2;
383
                           dvalue = b0<<8;
384
                           break;
385
                  case 3 : mask = 0x1;
386
                           dvalue = b0;
387
                           break;
388
                  }
389
                  break;
390
         default:
391
            printf("BUG: mem write size invalid (%08x)\n", s->pc);
392
            exit(2);
393
 
394
      }
395
      fprintf(s->t.log, "(%08X) [%08X] |%02X|=%08X WR\n", s->pc, address, mask, dvalue);
396
   }
397
 
398
   switch(address)
399
   {
400
      case UART_WRITE:
401
         putch(value);
402
         fflush(stdout);
403
         return;
404
      case IRQ_MASK:
405
         HWMemory[1] = value;
406
         return;
407
      case IRQ_STATUS:
408
         s->irqStatus = value;
409
         return;
410
      case CONFIG_REG:
411
         return;
412
      case MMU_PROCESS_ID:
413
         //printf("processId=%d\n", value);
414
         s->processId = value;
415
         return;
416
   }
417
 
418
   if(MMU_TLB <= address && address <= MMU_TLB+MMU_ENTRIES * 8)
419
   {
420
      //printf("TLB 0x%x 0x%x\n", address - MMU_TLB, value);
421
      ptr = (unsigned int)s->mmuEntry + address - MMU_TLB;
422
      *(int*)ptr = value;
423
      s->irqStatus &= ~IRQ_MMU;
424
      return;
425
   }
426
 
427
   ptr = (unsigned int)s->mem + (address % MEM_SIZE);
428
 
429
   if(0x10000000 <= address && address < 0x10000000 + 1024*1024)
430
      ptr += 1024*1024;
431
 
432
   switch(size)
433
   {
434 5 ja_rd
      case 4:
435
         /* We don't want the program to just quit, we want to log the fault */
436
         /* assert((address & 3) == 0); */
437
         if((address & 3) != 0){
438
            s->failed_assertions |= ASRT_UNALIGNED_WRITE;
439
            s->faulty_address = address;
440
            address = address & (~0x03);
441
         }
442 2 ja_rd
         if(s->big_endian)
443
            value = htonl(value);
444
         *(int*)ptr = value;
445
         break;
446 5 ja_rd
      case 2:
447
         /* We don't want the program to just quit, we want to log the fault */
448
         /* assert((address & 1) == 0); */
449
         if((address & 1) != 0){
450
            s->failed_assertions |= ASRT_UNALIGNED_WRITE;
451
            s->faulty_address = address;
452
            address = address & (~0x01);
453
         }
454 2 ja_rd
         if(s->big_endian)
455
            value = htons((unsigned short)value);
456
         *(short*)ptr = (unsigned short)value;
457
         break;
458
      case 1:
459
         *(char*)ptr = (unsigned char)value;
460
         break;
461
      default:
462
         printf("ERROR");
463
   }
464
}
465
 
466
/*---- Optional MMU and cache implementation ---------------------------------*/
467
 
468
/*
469
   The actual core does not have a cache so all of the original Plasma mlite.c
470
   code for cache simulation has been removed.
471
*/
472
 
473
#ifdef ENABLE_CACHE
474
#error Cache simulation missing!
475
#else
476
static void cache_init(void) {}
477
#endif
478
/*---- End optional cache implementation -------------------------------------*/
479
 
480
 
481
/** Simulates MIPS-I multiplier unsigned behavior*/
482
void mult_big(unsigned int a,
483
              unsigned int b,
484
              unsigned int *hi,
485
              unsigned int *lo)
486
{
487
   unsigned int ahi, alo, bhi, blo;
488
   unsigned int c0, c1, c2;
489
   unsigned int c1_a, c1_b;
490
 
491
   ahi = a >> 16;
492
   alo = a & 0xffff;
493
   bhi = b >> 16;
494
   blo = b & 0xffff;
495
 
496
   c0 = alo * blo;
497
   c1_a = ahi * blo;
498
   c1_b = alo * bhi;
499
   c2 = ahi * bhi;
500
 
501
   c2 += (c1_a >> 16) + (c1_b >> 16);
502
   c1 = (c1_a & 0xffff) + (c1_b & 0xffff) + (c0 >> 16);
503
   c2 += (c1 >> 16);
504
   c0 = (c1 << 16) + (c0 & 0xffff);
505
   *hi = c2;
506
   *lo = c0;
507
}
508
 
509
/** Simulates MIPS-I multiplier signed behavior*/
510
void mult_big_signed(int a,
511
                     int b,
512
                     unsigned int *hi,
513
                     unsigned int *lo)
514 11 ja_rd
{
515
   int64_t xa, xb, xr, temp;
516
   int32_t rh, rl;
517
 
518
   xa = a;
519
   xb = b;
520
   xr = xa * xb;
521
 
522
   temp = (xr >> 32) & 0xffffffff;
523
   rh = temp;
524
   temp = (xr >> 0) & 0xffffffff;
525
   rl = temp;
526
 
527
   *hi = rh;
528
   *lo = rl;
529 2 ja_rd
}
530
 
531
/** Load data from memory (used to simulate load delay slots) */
532
void start_load(State *s, int rt, int data){
533
   if(s->load_delay_slot){
534
      s->delayed_reg = rt;
535
      s->delay = 1;
536
      s->delayed_data = data;
537
   }
538
   else{
539
      /* load delay slot not simulated */
540
      s->r[rt] = data;
541
   }
542
}
543
 
544
/** Execute one cycle of the CPU (including any interlock stall cycles) */
545
void cycle(State *s, int show_mode)
546
{
547
   unsigned int opcode;
548
   unsigned int op, rs, rt, rd, re, func, imm, target;
549
   int imm_sex;
550
   int imm_shift, branch=0, lbranch=2, skip2=0;
551
   int *r=s->r;
552
   unsigned int *u=(unsigned int*)s->r;
553
   unsigned int ptr, epc, rSave;
554
 
555
   if(!show_mode){
556
      log_cycle(s);
557
   }
558
 
559
   opcode = mem_read(s, 4, s->pc, 0);
560
   op = (opcode >> 26) & 0x3f;
561
   rs = (opcode >> 21) & 0x1f;
562
   rt = (opcode >> 16) & 0x1f;
563
   rd = (opcode >> 11) & 0x1f;
564
   re = (opcode >> 6) & 0x1f;
565
   func = opcode & 0x3f;
566
   imm = opcode & 0xffff;
567
   imm_sex = (imm&0x8000)? 0xffff0000 | imm : imm;
568
   imm_shift = (((int)(short)imm) << 2) - 4;
569
   target = (opcode << 6) >> 4;
570
   ptr = (short)imm + r[rs];
571
   r[0] = 0;
572
   if(show_mode)
573
   {
574
      printf("%8.8x %8.8x ", s->pc, opcode);
575
      if(op == 0)
576
         printf("%8s ", special_string[func]);
577
      else if(op == 1)
578
         printf("%8s ", regimm_string[rt]);
579
      else
580
         printf("%8s ", opcode_string[op]);
581
      printf("$%2.2d $%2.2d $%2.2d $%2.2d ", rs, rt, rd, re);
582
      printf("%4.4x", imm);
583
      if(show_mode == 1)
584
         printf(" r[%2.2d]=%8.8x r[%2.2d]=%8.8x", rs, r[rs], rt, r[rt]);
585
      printf("\n");
586
   }
587
   if(show_mode > 5)
588 7 ja_rd
      return;
589
   /* epc will point to the victim instruction, i.e. THIS instruction */
590
   epc = s->pc;
591
   if(s->pc_next != s->pc + 4){
592
      /* FIXME traps in delay slots not supported yet */
593
      //epc = epc - 4;  /* trap in branch delay slot */
594
   }
595 2 ja_rd
 
596
   s->pc = s->pc_next;
597
   s->pc_next = s->pc_next + 4;
598
   if(s->skip)
599
   {
600
      s->skip = 0;
601
      return;
602
   }
603
   rSave = r[rt];
604
   switch(op)
605
   {
606
      case 0x00:/*SPECIAL*/
607
         switch(func)
608
         {
609
            case 0x00:/*SLL*/  r[rd]=r[rt]<<re;          break;
610
            case 0x02:/*SRL*/  r[rd]=u[rt]>>re;          break;
611
            case 0x03:/*SRA*/  r[rd]=r[rt]>>re;          break;
612
            case 0x04:/*SLLV*/ r[rd]=r[rt]<<r[rs];       break;
613
            case 0x06:/*SRLV*/ r[rd]=u[rt]>>r[rs];       break;
614
            case 0x07:/*SRAV*/ r[rd]=r[rt]>>r[rs];       break;
615
            case 0x08:/*JR*/   s->pc_next=r[rs];         break;
616
            case 0x09:/*JALR*/ r[rd]=s->pc_next; s->pc_next=r[rs]; break;
617
            case 0x0a:/*MOVZ*/ if(!r[rt]) r[rd]=r[rs];   break;  /*IV*/
618
            case 0x0b:/*MOVN*/ if(r[rt]) r[rd]=r[rs];    break;  /*IV*/
619
            case 0x0c:/*SYSCALL*/ /* epc|=1; WHY? */
620
                                  s->exceptionId=1; break;
621
            case 0x0d:/*BREAK*/   /* epc|=1; WHY? */
622
                                  s->exceptionId=1; break;
623
            case 0x0f:/*SYNC*/ s->wakeup=1;              break;
624
            case 0x10:/*MFHI*/ r[rd]=s->hi;              break;
625
            case 0x11:/*FTHI*/ s->hi=r[rs];              break;
626
            case 0x12:/*MFLO*/ r[rd]=s->lo;              break;
627
            case 0x13:/*MTLO*/ s->lo=r[rs];              break;
628
            case 0x18:/*MULT*/ mult_big_signed(r[rs],r[rt],&s->hi,&s->lo); break;
629
            case 0x19:/*MULTU*/ mult_big(r[rs],r[rt],&s->hi,&s->lo); break;
630
            case 0x1a:/*DIV*/  s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt]; break;
631
            case 0x1b:/*DIVU*/ s->lo=u[rs]/u[rt]; s->hi=u[rs]%u[rt]; break;
632
            case 0x20:/*ADD*/  r[rd]=r[rs]+r[rt];        break;
633
            case 0x21:/*ADDU*/ r[rd]=r[rs]+r[rt];        break;
634
            case 0x22:/*SUB*/  r[rd]=r[rs]-r[rt];        break;
635
            case 0x23:/*SUBU*/ r[rd]=r[rs]-r[rt];        break;
636
            case 0x24:/*AND*/  r[rd]=r[rs]&r[rt];        break;
637
            case 0x25:/*OR*/   r[rd]=r[rs]|r[rt];        break;
638
            case 0x26:/*XOR*/  r[rd]=r[rs]^r[rt];        break;
639
            case 0x27:/*NOR*/  r[rd]=~(r[rs]|r[rt]);     break;
640
            case 0x2a:/*SLT*/  r[rd]=r[rs]<r[rt];        break;
641
            case 0x2b:/*SLTU*/ r[rd]=u[rs]<u[rt];        break;
642
            case 0x2d:/*DADDU*/r[rd]=r[rs]+u[rt];        break;
643
            case 0x31:/*TGEU*/ break;
644
            case 0x32:/*TLT*/  break;
645
            case 0x33:/*TLTU*/ break;
646
            case 0x34:/*TEQ*/  break;
647
            case 0x36:/*TNE*/  break;
648
            default: printf("ERROR0(*0x%x~0x%x)\n", s->pc, opcode);
649
               s->wakeup=1;
650
         }
651
         break;
652
      case 0x01:/*REGIMM*/
653
         switch(rt) {
654
            case 0x10:/*BLTZAL*/ r[31]=s->pc_next;
655
            case 0x00:/*BLTZ*/   branch=r[rs]<0;    break;
656
            case 0x11:/*BGEZAL*/ r[31]=s->pc_next;
657
            case 0x01:/*BGEZ*/   branch=r[rs]>=0;   break;
658
            case 0x12:/*BLTZALL*/r[31]=s->pc_next;
659
            case 0x02:/*BLTZL*/  lbranch=r[rs]<0;   break;
660
            case 0x13:/*BGEZALL*/r[31]=s->pc_next;
661
            case 0x03:/*BGEZL*/  lbranch=r[rs]>=0;  break;
662
            default: printf("ERROR1\n"); s->wakeup=1;
663
          }
664
         break;
665
      case 0x03:/*JAL*/    r[31]=s->pc_next;
666
      case 0x02:/*J*/      s->pc_next=(s->pc&0xf0000000)|target; break;
667
      case 0x04:/*BEQ*/    branch=r[rs]==r[rt];     break;
668
      case 0x05:/*BNE*/    branch=r[rs]!=r[rt];     break;
669
      case 0x06:/*BLEZ*/   branch=r[rs]<=0;         break;
670
      case 0x07:/*BGTZ*/   branch=r[rs]>0;          break;
671
      case 0x08:/*ADDI*/   r[rt]=r[rs]+(short)imm;  break;
672
      case 0x09:/*ADDIU*/  u[rt]=u[rs]+(short)imm;  break;
673
      case 0x0a:/*SLTI*/   r[rt]=r[rs]<(short)imm;  break;
674
      case 0x0b:/*SLTIU*/  u[rt]=u[rs]<(unsigned int)(short)imm; break;
675
      case 0x0c:/*ANDI*/   r[rt]=r[rs]&imm;         break;
676
      case 0x0d:/*ORI*/    r[rt]=r[rs]|imm;         break;
677
      case 0x0e:/*XORI*/   r[rt]=r[rs]^imm;         break;
678
      case 0x0f:/*LUI*/    r[rt]=(imm<<16);         break;
679
      case 0x10:/*COP0*/
680
         if((opcode & (1<<23)) == 0)  //move from CP0
681
         {
682
            if(rd == 12)
683
               r[rt]=s->status;
684
            else
685
               r[rt]=s->epc;
686
         }
687
         else                         //move to CP0
688
         {
689
            s->status=r[rt]&1;
690
            if(s->processId && (r[rt]&2))
691
            {
692
               s->userMode|=r[rt]&2;
693
               //printf("CpuStatus=%d %d %d\n", r[rt], s->status, s->userMode);
694
               //s->wakeup = 1;
695
               //printf("pc=0x%x\n", epc);
696
            }
697
         }
698
         break;
699
//      case 0x11:/*COP1*/ break;
700
//      case 0x12:/*COP2*/ break;
701
//      case 0x13:/*COP3*/ break;
702
      case 0x14:/*BEQL*/   lbranch=r[rs]==r[rt];    break;
703
      case 0x15:/*BNEL*/   lbranch=r[rs]!=r[rt];    break;
704
      case 0x16:/*BLEZL*/  lbranch=r[rs]<=0;        break;
705
      case 0x17:/*BGTZL*/  lbranch=r[rs]>0;         break;
706
//      case 0x1c:/*MAD*/  break;   /*IV*/
707
      case 0x20:/*LB*/     //r[rt]=(signed char)mem_read(s,1,ptr,1);  break;
708
                           start_load(s, rt,(signed char)mem_read(s,1,ptr,1));
709
                           break;
710
 
711
      case 0x21:/*LH*/     //r[rt]=(signed short)mem_read(s,2,ptr,1); break;
712
                           start_load(s, rt, (signed short)mem_read(s,2,ptr,1));
713
                           break;
714
      case 0x22:/*LWL*/    //target=8*(ptr&3);
715
                           //r[rt]=(r[rt]&~(0xffffffff<<target))|
716
                           //      (mem_read(s,4,ptr&~3)<<target); break;
717
                           break;
718
      case 0x23:/*LW*/     //r[rt]=mem_read(s,4,ptr,1);   break;
719
                           start_load(s, rt, mem_read(s,4,ptr,1));
720
                           break;
721
      case 0x24:/*LBU*/    //r[rt]=(unsigned char)mem_read(s,1,ptr,1); break;
722
                           start_load(s, rt, (unsigned char)mem_read(s,1,ptr,1));
723
                           break;
724
      case 0x25:/*LHU*/    //r[rt]= (unsigned short)mem_read(s,2,ptr,1);
725
                           start_load(s, rt, (unsigned short)mem_read(s,2,ptr,1));
726
                           break;
727
      case 0x26:/*LWR*/
728
                           //target=32-8*(ptr&3);
729
                           //r[rt]=(r[rt]&~((unsigned int)0xffffffff>>target))|
730
                           //((unsigned int)mem_read(s,4,ptr&~3)>>target);
731
                           break;
732
      case 0x28:/*SB*/     mem_write(s,1,ptr,r[rt]);  break;
733
      case 0x29:/*SH*/     mem_write(s,2,ptr,r[rt]);  break;
734
      case 0x2a:/*SWL*/
735
                           //mem_write(s,1,ptr,r[rt]>>24);
736
                           //mem_write(s,1,ptr+1,r[rt]>>16);
737
                           //mem_write(s,1,ptr+2,r[rt]>>8);
738
                           //mem_write(s,1,ptr+3,r[rt]); break;
739
      case 0x2b:/*SW*/     mem_write(s,4,ptr,r[rt]);  break;
740
      case 0x2e:/*SWR*/    break; //fixme
741
      case 0x2f:/*CACHE*/  break;
742
      case 0x30:/*LL*/     //r[rt]=mem_read(s,4,ptr);   break;
743
                           start_load(s, rt, mem_read(s,4,ptr,1));
744
                           break;
745
 
746
//      case 0x31:/*LWC1*/ break;
747
//      case 0x32:/*LWC2*/ break;
748
//      case 0x33:/*LWC3*/ break;
749
//      case 0x35:/*LDC1*/ break;
750
//      case 0x36:/*LDC2*/ break;
751
//      case 0x37:/*LDC3*/ break;
752
//      case 0x38:/*SC*/     *(int*)ptr=r[rt]; r[rt]=1; break;
753
      case 0x38:/*SC*/     mem_write(s,4,ptr,r[rt]); r[rt]=1; break;
754
//      case 0x39:/*SWC1*/ break;
755
//      case 0x3a:/*SWC2*/ break;
756
//      case 0x3b:/*SWC3*/ break;
757
//      case 0x3d:/*SDC1*/ break;
758
//      case 0x3e:/*SDC2*/ break;
759
//      case 0x3f:/*SDC3*/ break;
760
      default: printf("ERROR2 address=0x%x opcode=0x%x\n", s->pc, opcode);
761
         s->wakeup=1;
762
   }
763
   s->pc_next += (branch || lbranch == 1) ? imm_shift : 0;
764
   s->pc_next &= ~3;
765
   s->skip = (lbranch == 0) | skip2;
766
 
767 5 ja_rd
   /* If there was trouble, log it */
768
   if(s->failed_assertions!=0){
769
      log_failed_assertions(s);
770
      s->failed_assertions=0;
771
   }
772
 
773
 
774 2 ja_rd
   /* if there's a delayed load pending, do it now: load reg with memory data */
775
   if(s->load_delay_slot){
776
      /*--- simulate real core's load interlock ---*/
777
      if(s->delay<=0){
778
         if(s->delayed_reg>0){
779
            s->r[s->delayed_reg] = s->delayed_data;
780
         }
781
         s->delayed_reg = 0;
782
      }
783
      else{
784
         s->delay = s->delay - 1;
785
      }
786
   }
787
   else{
788
      /*--- delay slot or interlocking not simulated ---*/
789
      /*
790
      if(s->delay){
791
         r[s->delayed_reg] = s->delayed_data;
792
         s->delay=0;
793
      }
794
      */
795
   }
796
 
797 7 ja_rd
   /* Handle exceptions */
798 2 ja_rd
   if(s->exceptionId)
799
   {
800
      r[rt] = rSave;
801
      s->epc = epc;
802
      s->pc_next = 0x3c;
803
      s->skip = 1;
804
      s->exceptionId = 0;
805
      s->userMode = 0;
806
      //s->wakeup = 1;
807
      return;
808
   }
809
}
810
 
811
/** Dump CPU state to console */
812
void show_state(State *s)
813
{
814
   int i,j;
815
   printf("pid=%d userMode=%d, epc=0x%x\n", s->processId, s->userMode, s->epc);
816
   for(i = 0; i < 4; ++i)
817
   {
818
      printf("%2.2d ", i * 8);
819
      for(j = 0; j < 8; ++j)
820
      {
821
         printf("%8.8x ", s->r[i*8+j]);
822
      }
823
      printf("\n");
824
   }
825
   //printf("%8.8lx %8.8lx %8.8lx %8.8lx\n", s->pc, s->pc_next, s->hi, s->lo);
826
   j = s->pc;
827
   for(i = -4; i <= 8; ++i)
828
   {
829
      printf("%c", i==0 ? '*' : ' ');
830
      s->pc = j + i * 4;
831
      cycle(s, 10);
832
   }
833
   s->pc = j;
834
}
835
 
836
/** Show debug monitor prompt and execute user command */
837
void do_debug(State *s)
838
{
839
   int ch;
840
   int i, j=0, watch=0, addr;
841
   s->pc_next = s->pc + 4;
842
   s->skip = 0;
843
   s->delayed_reg = 0;
844
   s->wakeup = 0;
845
   show_state(s);
846
   ch = ' ';
847
   for(;;)
848
   {
849
      if(ch != 'n')
850
      {
851
         if(watch)
852
            printf("0x%8.8x=0x%8.8x\n", watch, mem_read(s, 4, watch,0));
853
         printf("1=Debug 2=Trace 3=Step 4=BreakPt 5=Go 6=Memory ");
854
         printf("7=Watch 8=Jump 9=Quit A=dump > ");
855
      }
856
      ch = getch();
857
      if(ch != 'n')
858
         printf("\n");
859
      switch(ch)
860
      {
861
      case 'a': case 'A':
862
         dump_trace_buffer(s); break;
863
      case '1': case 'd': case ' ':
864
         cycle(s, 0); show_state(s); break;
865
      case 'n':
866
         cycle(s, 1); break;
867
      case '2': case 't':
868
         cycle(s, 0); printf("*"); cycle(s, 10); break;
869
      case '3': case 's':
870
         printf("Count> ");
871
         scanf("%d", &j);
872
         for(i = 0; i < j; ++i)
873
            cycle(s, 1);
874
         show_state(s);
875
         break;
876
      case '4': case 'b':
877
         printf("Line> ");
878
         scanf("%x", &j);
879
         printf("break point=0x%x\n", j);
880
         break;
881
      case '5': case 'g':
882
         s->wakeup = 0;
883
         cycle(s, 0);
884
         while(s->wakeup == 0)
885
         {
886
            if(s->pc == j){
887
               printf("\n\nStop: pc = 0x%08x\n\n", j);
888
               break;
889
            }
890
            cycle(s, 0);
891
         }
892
         show_state(s);
893
         break;
894
      case 'G':
895
         s->wakeup = 0;
896
         cycle(s, 1);
897
         while(s->wakeup == 0)
898
         {
899
            if(s->pc == j)
900
               break;
901
            cycle(s, 1);
902
         }
903
         show_state(s);
904
         break;
905
      case '6': case 'm':
906
         printf("Memory> ");
907
         scanf("%x", &j);
908
         for(i = 0; i < 8; ++i)
909
         {
910
            printf("%8.8x ", mem_read(s, 4, j+i*4, 0));
911
         }
912
         printf("\n");
913
         break;
914
      case '7': case 'w':
915
         printf("Watch> ");
916
         scanf("%x", &watch);
917
         break;
918
      case '8': case 'j':
919
         printf("Jump> ");
920
         scanf("%x", &addr);
921
         s->pc = addr;
922
         s->pc_next = addr + 4;
923
         show_state(s);
924
         break;
925
      case '9': case 'q':
926
         return;
927
      }
928
   }
929
}
930
 
931
/** Read binary code and data files */
932
int read_program(State *s, char *code_name, char *data_name){
933
   FILE *in;
934
   int bytes, i;
935
   unsigned char *buffer;
936
 
937
   /* Read code file (.text + .reginfo + .rodata) */
938
   in = fopen(code_name, "rb");
939
   if(in == NULL)
940
   {
941
      printf("Can't open file %s!\n",code_name);
942
      getch();
943
      return(0);
944
   }
945
   bytes = fread(s->mem, 1, MEM_SIZE, in);
946
   fclose(in);
947
   in = NULL;
948
   printf("Code [size= %6d, start= 0x%08x]\n", bytes, 0);
949
 
950
   /* Read data file (.data + .bss) if necessary */
951
   if(data_name!=NULL){
952
      in = fopen(data_name, "rb");
953
      if(in == NULL)
954
      {
955
         printf("Can't open file %s!\n",data_name);
956
         getch();
957
         return(0);
958
      }
959
      /* FIXME Section '.data' start hardcoded to 0x10000 */
960
      buffer = (unsigned char*)malloc(MEM_SIZE);
961
 
962
      bytes = fread(buffer, 1, MEM_SIZE, in);
963
      fclose(in);
964
      printf("Data [size= %6d, start= 0x%08x]\n", bytes, 0x10000);
965
 
966
      for(i=0;i<bytes;i++){
967
         s->mem[0x10000+i] = buffer[i];
968
      }
969
      free(buffer);
970
   }
971
 
972
   return 1;
973
}
974
 
975
/*----------------------------------------------------------------------------*/
976
 
977
int main(int argc,char *argv[])
978
{
979
   State state, *s=&state;
980
   int index;
981
   char *code_filename;
982
   char *data_filename;
983
 
984
   printf("MIPS-I emulator\n");
985
   memset(s, 0, sizeof(State));
986
   s->big_endian = 1;
987
   s->load_delay_slot = 0;
988
   s->mem = (unsigned char*)malloc(MEM_SIZE);
989
   memset(s->mem, 0, MEM_SIZE);
990
 
991
 
992
   if(argc==3){
993
      code_filename = argv[1];
994
      data_filename = argv[2];
995
   }
996
   else if(argc==2){
997
      code_filename = argv[1];
998
      data_filename = NULL;
999
   }
1000
   else{
1001
      printf("Usage:");
1002
      printf("    slite file.exe <bin code file> [<bin data file>]\n");
1003
      return 0;
1004
   }
1005
 
1006
   if(!read_program(s, code_filename, data_filename)) return 0;
1007
 
1008
   init_trace_buffer(s, "sw_sim_log.txt");
1009
   memcpy(s->mem + 1024*1024, s->mem, 1024*1024);  //internal 8KB SRAM
1010
   cache_init(); /* stub */
1011
 
1012
   /* NOTE: Original mlite supported loading little-endian code, which this
1013
      program doesn't. The endianess-conversion code has been removed.
1014
   */
1015
 
1016 5 ja_rd
   /* Simulate a CPU reset */
1017
   /* FIXME cpu reset function needed */
1018
   s->pc = 0x0;      /* reset start vector */
1019
   s->failed_assertions = 0; /* no failed assertions pending */
1020
 
1021 2 ja_rd
   /* FIXME PC fixup at address zero has to be removed */
1022
   index = mem_read(s, 4, 0, 0);
1023
   if((index & 0xffffff00) == 0x3c1c1000){
1024
      s->pc = 0x10000000;
1025
   }
1026
 
1027
   /* Enter debug command interface; will only exit clean with user command */
1028
   do_debug(s);
1029
 
1030
   /* Close and deallocate everything and quit */
1031
   close_trace_buffer(s);
1032
   free(s->mem);
1033
   return(0);
1034
}
1035
 
1036
/*----------------------------------------------------------------------------*/
1037
 
1038
 
1039
void init_trace_buffer(State *s, const char *log_file_name){
1040
   int i;
1041
 
1042
#if FILE_LOGGING_DISABLED
1043
   s->t.log = NULL;
1044
   return;
1045
#else
1046
   for(i=0;i<TRACE_BUFFER_SIZE;i++){
1047
      s->t.buf[i]=0xffffffff;
1048
   }
1049
   s->t.next = 0;
1050
 
1051
   /* if file logging is enabled, open log file */
1052
   if(log_file_name!=NULL){
1053
      s->t.log = fopen(log_file_name, "w");
1054
      if(s->t.log==NULL){
1055
         printf("Error opening log file '%s', file logging disabled\n", log_file_name);
1056
      }
1057
   }
1058
   else{
1059
      s->t.log = NULL;
1060
   }
1061
#endif
1062
}
1063
 
1064
/** Dumps last jump targets as a chunk of hex numbers (older is left top) */
1065
void dump_trace_buffer(State *s){
1066
   int i, col;
1067
 
1068
   for(i=0, col=0;i<TRACE_BUFFER_SIZE;i++, col++){
1069
      printf("%08x ", s->t.buf[s->t.next + i]);
1070
      if((col % 8)==7){
1071
         printf("\n");
1072
      }
1073
   }
1074
}
1075
 
1076
/** Logs last cycle's activity (changes in state and/or loads/stores) */
1077
void log_cycle(State *s){
1078
   static unsigned int last_pc = 0;
1079
   int i;
1080
 
1081
   /* store PC in trace buffer only if there was a jump */
1082
   if(s->pc != (last_pc+4)){
1083
      s->t.buf[s->t.next] = s->pc;
1084
      s->t.next = (s->t.next + 1) % TRACE_BUFFER_SIZE;
1085
   }
1086
   last_pc = s->pc;
1087
 
1088
   /* if file logging is enabled, dump a trace log to file */
1089
   if(s->t.log!=NULL){
1090
      for(i=0;i<32;i++){
1091
         if(s->t.pr[i] != s->r[i]){
1092
            fprintf(s->t.log, "(%08X) [%02X]=%08X\n", s->pc, i, s->r[i]);
1093
         }
1094
         s->t.pr[i] = s->r[i];
1095
      }
1096
      if(s->lo != s->t.lo){
1097
         fprintf(s->t.log, "(%08X) [LO]=%08X\n", s->pc, s->lo);
1098
      }
1099
      s->t.lo = s->lo;
1100
 
1101
      if(s->hi != s->t.hi){
1102
         fprintf(s->t.log, "(%08X) [HI]=%08X\n", s->pc, s->hi);
1103
      }
1104
      s->t.hi = s->hi;
1105
 
1106
      if(s->epc != s->t.epc){
1107
         fprintf(s->t.log, "(%08X) [EP]=%08X\n", s->pc, s->epc);
1108
      }
1109
      s->t.epc = s->epc;
1110
   }
1111
}
1112
 
1113
/** Frees debug buffers and closes log file */
1114
void close_trace_buffer(State *s){
1115
   if(s->t.log){
1116
      fclose(s->t.log);
1117
   }
1118
}
1119 5 ja_rd
 
1120
/** Logs a message for each failed assertion, each in a line */
1121
void log_failed_assertions(State *s){
1122
   unsigned bitmap = s->failed_assertions;
1123
   int i = 0;
1124
 
1125
   /* This loop will crash the program if the message table is too short...*/
1126
   if(s->t.log != NULL){
1127
      for(i=0;i<32;i++){
1128
         if(bitmap & 0x1){
1129
            fprintf(s->t.log, "ASSERTION FAILED: [%08x] %s\n",
1130
                    s->faulty_address,
1131
                    assertion_messages[i]);
1132
         }
1133
         bitmap = bitmap >> 1;
1134
      }
1135
   }
1136
}

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