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/*------------------------------------------------------------------------------

* slite.c -- MIPS-I simulator based on Steve Rhoad's "mlite"

*

* This is a slightly modified version of Steve Rhoad's "mlite" simulator, which

* is part of his PLASMA project (original date: 1/31/01).

*

*-------------------------------------------------------------------------------

* Usage:

*     slite <code file name> <data file name>

*

* The program will allocate a chunk of RAM (MEM_SIZE bytes) and map it to

* address 0x00000000 of the simulated CPU.

* Then it will read the 'code file' (as a big-endian plain binary) onto address

* 0x0 of the simulated CPU memory, and 'data file' on address 0x10000.

* Finally, will reset the CPU and enter the interactive debugger.

*

* (Note that the above is only necessary if the system does not have caches,

* because of the Harvard architecture. With caches in place, program loading

* would be antirely conventional).

*

* A simulation log file will be dumped to file "sw_sim_log.txt". This log can be

* used to compare with an equivalent log dumped by the hardware simulation, as

* a simple way to validate the hardware for a given program. See the project

* readme files for details.

*

*-------------------------------------------------------------------------------

* KNOWN BUGS:

*

* 1.- Load delay slot simulation does not work

*

* Some programs don't work when load delay slots are simulated (by setting

* "s->load_delay_slot = 1" in function main).

*

* The actual HW core does no longer use load delay slots but load interlocking

* so it may be better to just remove this feature.

*

*-------------------------------------------------------------------------------

* @date 2011-jan-16

*

*-------------------------------------------------------------------------------

* COPYRIGHT:    Software placed into the public domain by the author.

*               Software 'as is' without warranty.  Author liable for nothing.

*

* IMPORTANT: Assumes host is little endian.

*-----------------------------------------------------------------------------*/

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include <ctype.h>

#include <assert.h>

/** Set to !=0 to disable file logging */

#define FILE_LOGGING_DISABLED (0)

/** Define to enable cache simulation (unimplemented) */

//#define ENABLE_CACHE

#define MEM_SIZE (1024*1024*2)

#define ntohs(A) ( ((A)>>8) | (((A)&0xff)<<8) )

#define htons(A) ntohs(A)

#define ntohl(A) ( ((A)>>24) | (((A)&0xff0000)>>8) | (((A)&0xff00)<<8) | ((A)<<24) )

#define htonl(A) ntohl(A)

/*---- OS-dependent support functions and definitions ------------------------*/

#ifndef WIN32

//Support for Linux

#define putch putchar

#include <termios.h>

#include <unistd.h>

void Sleep(unsigned int value)

{

   usleep(value * 1000);

}

int kbhit(void)

{

   struct termios oldt, newt;

   struct timeval tv;

   fd_set read_fd;

   tcgetattr(STDIN_FILENO, &oldt);

   newt = oldt;

   newt.c_lflag &= ~(ICANON | ECHO);

   tcsetattr(STDIN_FILENO, TCSANOW, &newt);

   tv.tv_sec=0;

   tv.tv_usec=0;

   FD_ZERO(&read_fd);

   FD_SET(0,&read_fd);

   if(select(1, &read_fd, NULL, NULL, &tv) == -1)

      return 0;

   //tcsetattr(STDIN_FILENO, TCSANOW, &oldt);

   if(FD_ISSET(0,&read_fd))

      return 1;

   return 0;

}

int getch(void)

{

   struct termios oldt, newt;

   int ch;

   tcgetattr(STDIN_FILENO, &oldt);

   newt = oldt;

   newt.c_lflag &= ~(ICANON | ECHO);

   tcsetattr(STDIN_FILENO, TCSANOW, &newt);

   ch = getchar();

   //tcsetattr(STDIN_FILENO, TCSANOW, &oldt);

   return ch;

}

#else

//Support for Windows

#include <conio.h>

extern void __stdcall Sleep(unsigned long value);

#endif

/*---- End of OS-dependent support functions and definitions -----------------*/

/*---- Hardware system parameters --------------------------------------------*/

/* Much of this is a remnant from Plasma's mlite and is  no longer used. */

/* FIXME Refactor HW system params */

#define UART_WRITE        0x20000000

#define UART_READ         0x20000000

#define IRQ_MASK          0x20000010

#define IRQ_STATUS        0x20000020

#define CONFIG_REG        0x20000070

#define MMU_PROCESS_ID    0x20000080

#define MMU_FAULT_ADDR    0x20000090

#define MMU_TLB           0x200000a0

#define IRQ_UART_READ_AVAILABLE  0x001

#define IRQ_UART_WRITE_AVAILABLE 0x002

#define IRQ_COUNTER18_NOT        0x004

#define IRQ_COUNTER18            0x008

#define IRQ_MMU                  0x200

#define MMU_ENTRIES 4

#define MMU_MASK (1024*4-1)

/** Length of debugging jump target queue */

#define TRACE_BUFFER_SIZE (32)

typedef struct {

   unsigned int buf[TRACE_BUFFER_SIZE];   /**< queue of last jump targets */

   unsigned int next;                     /**< internal queue head pointer */

   FILE *log;                             /**< text log file or NULL */

   int pr[32];                            /**< last value of register bank */

   int hi, lo, epc;                       /**< last value of internal regs */

} Trace;

typedef struct

{

   unsigned int virtualAddress;

   unsigned int physicalAddress;

} MmuEntry;

typedef struct {

   int load_delay_slot;

   int delay;

   unsigned int delayed_reg;

   int delayed_data;

   int r[32];

   int opcode;

   int pc, pc_next, epc;

   unsigned int hi;

   unsigned int lo;

   int status;

   int userMode;

   int processId;

   int exceptionId;

   int faultAddr;

   int irqStatus;

   int skip;

   Trace t;

   unsigned char *mem;

   int wakeup;

   int big_endian;

   MmuEntry mmuEntry[MMU_ENTRIES];

} State;

static char *opcode_string[]={

   "SPECIAL","REGIMM","J","JAL","BEQ","BNE","BLEZ","BGTZ",

   "ADDI","ADDIU","SLTI","SLTIU","ANDI","ORI","XORI","LUI",

   "COP0","COP1","COP2","COP3","BEQL","BNEL","BLEZL","BGTZL",

   "?","?","?","?","?","?","?","?",

   "LB","LH","LWL","LW","LBU","LHU","LWR","?",

   "SB","SH","SWL","SW","?","?","SWR","CACHE",

   "LL","LWC1","LWC2","LWC3","?","LDC1","LDC2","LDC3"

   "SC","SWC1","SWC2","SWC3","?","SDC1","SDC2","SDC3"

};

static char *special_string[]={

   "SLL","?","SRL","SRA","SLLV","?","SRLV","SRAV",

   "JR","JALR","MOVZ","MOVN","SYSCALL","BREAK","?","SYNC",

   "MFHI","MTHI","MFLO","MTLO","?","?","?","?",

   "MULT","MULTU","DIV","DIVU","?","?","?","?",

   "ADD","ADDU","SUB","SUBU","AND","OR","XOR","NOR",

   "?","?","SLT","SLTU","?","DADDU","?","?",

   "TGE","TGEU","TLT","TLTU","TEQ","?","TNE","?",

   "?","?","?","?","?","?","?","?"

};

static char *regimm_string[]={

   "BLTZ","BGEZ","BLTZL","BGEZL","?","?","?","?",

   "TGEI","TGEIU","TLTI","TLTIU","TEQI","?","TNEI","?",

   "BLTZAL","BEQZAL","BLTZALL","BGEZALL","?","?","?","?",

   "?","?","?","?","?","?","?","?"

};

static unsigned int HWMemory[8];

/*---- Local function prototypes ---------------------------------------------*/

/* Debug and logging */

void init_trace_buffer(State *s, const char *log_file_name);

void close_trace_buffer(State *s);

void dump_trace_buffer(State *s);

void log_cycle(State *s);

void log_read(State *s, int full_address, int word_value, int size, int log);

/* Hardware simulation */

int mem_read(State *s, int size, unsigned int address, int log);

void mem_write(State *s, int size, int unsigned address, unsigned value);

void start_load(State *s, int rt, int data);

/*---- Local functions -------------------------------------------------------*/

/** Log to file a memory read operation (not including target reg change) */

void log_read(State *s, int full_address, int word_value, int size, int log){

   if(s->t.log!=NULL && log!=0){

      if(size==4){ size=0x04; }

      else if(size==2){ size=0x02; }

      else { size=0x01; }

      fprintf(s->t.log, "(%08X) [%08X] <**>=%08X RD\n",

              s->pc, full_address, /*size,*/ word_value);

   }

}

/** Read memory, optionally logging */

int mem_read(State *s, int size, unsigned int address, int log)

{

   unsigned int value=0, word_value=0, ptr;

   unsigned int full_address = address;

   s->irqStatus |= IRQ_UART_WRITE_AVAILABLE;

   switch(address)

   {

      case UART_READ:

         word_value = 0x00000001;

         log_read(s, full_address, word_value, size, log);

         return word_value;

         /* FIXME Take input from text file */

         /*

         if(kbhit()){

            HWMemory[0] = getch();

         }

         s->irqStatus &= ~IRQ_UART_READ_AVAILABLE; //clear bit

         return HWMemory[0];

         */

      case IRQ_MASK:

         return HWMemory[1];

      case IRQ_MASK + 4:

         Sleep(10);

         return 0;

      case IRQ_STATUS:

         /*if(kbhit())

            s->irqStatus |= IRQ_UART_READ_AVAILABLE;

         return s->irqStatus;

         */

         /* FIXME Optionally simulate UART TX delay */

         word_value = 0x00000003; /* Ready to TX and RX */

         log_read(s, full_address, word_value, size, log);

         return word_value;

      case MMU_PROCESS_ID:

         return s->processId;

      case MMU_FAULT_ADDR:

         return s->faultAddr;

   }

   ptr = (unsigned int)s->mem + (address % MEM_SIZE);

   if(0x10000000 <= address && address < 0x10000000 + 1024*1024)

      ptr += 1024*1024;

   word_value = *(int*)(ptr&0xfffffffc);

   if(s->big_endian)

            word_value = ntohl(word_value);

   switch(size)

   {

      case 4:

         if(address & 3){

            printf("Unaligned access PC=0x%x address=0x%x\n",

                   (int)s->pc, (int)address);

         }

         assert((address & 3) == 0);

         value = *(int*)ptr;

         if(s->big_endian)

            value = ntohl(value);

         break;

      case 2:

         assert((address & 1) == 0);

         value = *(unsigned short*)ptr;

         if(s->big_endian)

            value = ntohs((unsigned short)value);

         break;

      case 1:

         value = *(unsigned char*)ptr;

         break;

      default:

         printf("ERROR");

   }

   log_read(s, full_address, word_value, size, log);

   return(value);

}

/** Write memory */

void mem_write(State *s, int size, unsigned address, unsigned value)

{

   unsigned int ptr, mask, dvalue, b0, b1, b2, b3;

   if(s->t.log!=NULL){

      b0 = value & 0x000000ff;

      b1 = value & 0x0000ff00;

      b2 = value & 0x00ff0000;

      b3 = value & 0xff000000;

      switch(size){

         case 4:  mask = 0x0f;

                  dvalue = value;

                  break;

         case 2:  if((address&0x2)==0){

                     mask = 0xc;

                     dvalue = b1<<16 | b0<<16;

                  }

                  else{

                     mask = 0x3;

                     dvalue = b1 | b0;

                  }

                  break;

         case 1:  switch(address%4){

                  case 0 : mask = 0x8;

                           dvalue = b0<<24;

                           break;

                  case 1 : mask = 0x4;

                           dvalue = b0<<16;

                           break;

                  case 2 : mask = 0x2;

                           dvalue = b0<<8;

                           break;

                  case 3 : mask = 0x1;

                           dvalue = b0;

                           break;

                  }

                  break;

         default:

            printf("BUG: mem write size invalid (%08x)\n", s->pc);

            exit(2);

      }

      fprintf(s->t.log, "(%08X) [%08X] |%02X|=%08X WR\n", s->pc, address, mask, dvalue);

   }

   switch(address)

   {

      case UART_WRITE:

         putch(value);

         fflush(stdout);

         return;

      case IRQ_MASK:

         HWMemory[1] = value;

         return;

      case IRQ_STATUS:

         s->irqStatus = value;

         return;

      case CONFIG_REG:

         return;

      case MMU_PROCESS_ID:

         //printf("processId=%d\n", value);

         s->processId = value;

         return;

   }

   if(MMU_TLB <= address && address <= MMU_TLB+MMU_ENTRIES * 8)

   {

      //printf("TLB 0x%x 0x%x\n", address - MMU_TLB, value);

      ptr = (unsigned int)s->mmuEntry + address - MMU_TLB;

      *(int*)ptr = value;

      s->irqStatus &= ~IRQ_MMU;

      return;

   }

   ptr = (unsigned int)s->mem + (address % MEM_SIZE);

   if(0x10000000 <= address && address < 0x10000000 + 1024*1024)

      ptr += 1024*1024;

   switch(size)

   {

      case 4:

         assert((address & 3) == 0);

         if(s->big_endian)

            value = htonl(value);

         *(int*)ptr = value;

         break;

      case 2:

         assert((address & 1) == 0);

         if(s->big_endian)

            value = htons((unsigned short)value);

         *(short*)ptr = (unsigned short)value;

         break;

      case 1:

         *(char*)ptr = (unsigned char)value;

         break;

      default:

         printf("ERROR");

   }

}

/*---- Optional MMU and cache implementation ---------------------------------*/

/*

   The actual core does not have a cache so all of the original Plasma mlite.c

   code for cache simulation has been removed.

*/

#ifdef ENABLE_CACHE

#error Cache simulation missing!

#else

static void cache_init(void) {}

#endif

/*---- End optional cache implementation -------------------------------------*/

/** Simulates MIPS-I multiplier unsigned behavior*/

void mult_big(unsigned int a,

              unsigned int b,

              unsigned int *hi,

              unsigned int *lo)

{

   unsigned int ahi, alo, bhi, blo;

   unsigned int c0, c1, c2;

   unsigned int c1_a, c1_b;

   ahi = a >> 16;

   alo = a & 0xffff;

   bhi = b >> 16;

   blo = b & 0xffff;

   c0 = alo * blo;

   c1_a = ahi * blo;

   c1_b = alo * bhi;

   c2 = ahi * bhi;

   c2 += (c1_a >> 16) + (c1_b >> 16);

   c1 = (c1_a & 0xffff) + (c1_b & 0xffff) + (c0 >> 16);

   c2 += (c1 >> 16);

   c0 = (c1 << 16) + (c0 & 0xffff);

   *hi = c2;

   *lo = c0;

}

/** Simulates MIPS-I multiplier signed behavior*/

void mult_big_signed(int a,

                     int b,

                     unsigned int *hi,

                     unsigned int *lo)

{

   unsigned int ahi, alo, bhi, blo;

   unsigned int c0, c1, c2;

   unsigned int c1_a, c1_b;

   ahi = a >> 16;

   alo = a & 0xffff;

   bhi = b >> 16;

   blo = b & 0xffff;

   c0 = alo * blo;

   c1_a = ahi * blo;

   c1_b = alo * bhi;

   c2 = ahi * bhi;

   c2 += (c1_a >> 16) + (c1_b >> 16);

   c1 = (c1_a & 0xffff) + (c1_b & 0xffff) + (c0 >> 16);

   c2 += (c1 >> 16);

   c0 = (c1 << 16) + (c0 & 0xffff);

   *hi = c2;

   *lo = c0;

}

/** Load data from memory (used to simulate load delay slots) */

void start_load(State *s, int rt, int data){

   if(s->load_delay_slot){

      s->delayed_reg = rt;

      s->delay = 1;

      s->delayed_data = data;

   }

   else{

      /* load delay slot not simulated */

      s->r[rt] = data;

   }

}

/** Execute one cycle of the CPU (including any interlock stall cycles) */

void cycle(State *s, int show_mode)

{

   unsigned int opcode;

   unsigned int op, rs, rt, rd, re, func, imm, target;

   int imm_sex;

   int imm_shift, branch=0, lbranch=2, skip2=0;

   int *r=s->r;

   unsigned int *u=(unsigned int*)s->r;

   unsigned int ptr, epc, rSave;

   if(!show_mode){

      log_cycle(s);

   }

   opcode = mem_read(s, 4, s->pc, 0);

   op = (opcode >> 26) & 0x3f;

   rs = (opcode >> 21) & 0x1f;

   rt = (opcode >> 16) & 0x1f;

   rd = (opcode >> 11) & 0x1f;

   re = (opcode >> 6) & 0x1f;

   func = opcode & 0x3f;

   imm = opcode & 0xffff;

   imm_sex = (imm&0x8000)? 0xffff0000 | imm : imm;

   imm_shift = (((int)(short)imm) << 2) - 4;

   target = (opcode << 6) >> 4;

   ptr = (short)imm + r[rs];

   r[0] = 0;

   if(show_mode)

   {

      printf("%8.8x %8.8x ", s->pc, opcode);

      if(op == 0)

         printf("%8s ", special_string[func]);

      else if(op == 1)

         printf("%8s ", regimm_string[rt]);

      else

         printf("%8s ", opcode_string[op]);

      printf("$%2.2d $%2.2d $%2.2d $%2.2d ", rs, rt, rd, re);

      printf("%4.4x", imm);

      if(show_mode == 1)

         printf(" r[%2.2d]=%8.8x r[%2.2d]=%8.8x", rs, r[rs], rt, r[rt]);

      printf("\n");

   }

   if(show_mode > 5)

      return;

   epc = s->pc + 4;

   if(s->pc_next != s->pc + 4)

      epc |= 2;  //branch delay slot

   s->pc = s->pc_next;

   s->pc_next = s->pc_next + 4;

   if(s->skip)

   {

      s->skip = 0;

      return;

   }

   rSave = r[rt];

   switch(op)

   {

      case 0x00:/*SPECIAL*/

         switch(func)

         {

            case 0x00:/*SLL*/  r[rd]=r[rt]<<re;          break;

            case 0x02:/*SRL*/  r[rd]=u[rt]>>re;          break;

            case 0x03:/*SRA*/  r[rd]=r[rt]>>re;          break;

            case 0x04:/*SLLV*/ r[rd]=r[rt]<<r[rs];       break;

            case 0x06:/*SRLV*/ r[rd]=u[rt]>>r[rs];       break;

            case 0x07:/*SRAV*/ r[rd]=r[rt]>>r[rs];       break;

            case 0x08:/*JR*/   s->pc_next=r[rs];         break;

            case 0x09:/*JALR*/ r[rd]=s->pc_next; s->pc_next=r[rs]; break;

            case 0x0a:/*MOVZ*/ if(!r[rt]) r[rd]=r[rs];   break;  /*IV*/

            case 0x0b:/*MOVN*/ if(r[rt]) r[rd]=r[rs];    break;  /*IV*/

            case 0x0c:/*SYSCALL*/ /* epc|=1; WHY? */

                                  s->exceptionId=1; break;

            case 0x0d:/*BREAK*/   /* epc|=1; WHY? */

                                  s->exceptionId=1; break;

            case 0x0f:/*SYNC*/ s->wakeup=1;              break;

            case 0x10:/*MFHI*/ r[rd]=s->hi;              break;

            case 0x11:/*FTHI*/ s->hi=r[rs];              break;

            case 0x12:/*MFLO*/ r[rd]=s->lo;              break;

            case 0x13:/*MTLO*/ s->lo=r[rs];              break;

            case 0x18:/*MULT*/ mult_big_signed(r[rs],r[rt],&s->hi,&s->lo); break;

            case 0x19:/*MULTU*/ mult_big(r[rs],r[rt],&s->hi,&s->lo); break;

            case 0x1a:/*DIV*/  s->lo=r[rs]/r[rt]; s->hi=r[rs]%r[rt]; break;

            case 0x1b:/*DIVU*/ s->lo=u[rs]/u[rt]; s->hi=u[rs]%u[rt]; break;

            case 0x20:/*ADD*/  r[rd]=r[rs]+r[rt];        break;

            case 0x21:/*ADDU*/ r[rd]=r[rs]+r[rt];        break;

            case 0x22:/*SUB*/  r[rd]=r[rs]-r[rt];        break;

            case 0x23:/*SUBU*/ r[rd]=r[rs]-r[rt];        break;

            case 0x24:/*AND*/  r[rd]=r[rs]&r[rt];        break;