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[/] [ion/] [trunk/] [vhdl/] [demo/] [c2sb_demo.vhdl] - Blame information for rev 87

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1 46 ja_rd
--##############################################################################
2 2 ja_rd
-- ION MIPS-compatible CPU demo on Terasic DE-1 Cyclone-II starter board
3 46 ja_rd
--##############################################################################
4 2 ja_rd
-- This module is little more than a wrapper around the CPU and its memories.
5 46 ja_rd
--##############################################################################
6 2 ja_rd
 
7
library ieee;
8
use ieee.std_logic_1164.all;
9
use ieee.std_logic_arith.all;
10
use ieee.std_logic_unsigned.all;
11
 
12
-- FPGA i/o for Terasic DE-1 board
13
-- (Many of the board's i/o devices will go unused in this demo)
14
entity c2sb_demo is
15 59 ja_rd
    port (
16 2 ja_rd
        -- ***** Clocks
17
        clk_50MHz     : in std_logic;
18
 
19
        -- ***** Flash 4MB
20
        flash_addr    : out std_logic_vector(21 downto 0);
21
        flash_data    : in std_logic_vector(7 downto 0);
22
        flash_oe_n    : out std_logic;
23
        flash_we_n    : out std_logic;
24
        flash_reset_n : out std_logic;
25
 
26
        -- ***** SRAM 256K x 16
27
        sram_addr     : out std_logic_vector(17 downto 0);
28
        sram_data     : inout std_logic_vector(15 downto 0);
29
        sram_oe_n     : out std_logic;
30
        sram_ub_n     : out std_logic;
31 59 ja_rd
        sram_lb_n     : out std_logic;
32 2 ja_rd
        sram_ce_n     : out std_logic;
33 59 ja_rd
        sram_we_n     : out std_logic;
34 2 ja_rd
 
35
        -- ***** RS-232
36
        rxd           : in std_logic;
37
        txd           : out std_logic;
38
 
39
        -- ***** Switches and buttons
40
        switches      : in std_logic_vector(9 downto 0);
41
        buttons       : in std_logic_vector(3 downto 0);
42
 
43
        -- ***** Quad 7-seg displays
44
        hex0          : out std_logic_vector(0 to 6);
45
        hex1          : out std_logic_vector(0 to 6);
46
        hex2          : out std_logic_vector(0 to 6);
47
        hex3          : out std_logic_vector(0 to 6);
48
 
49
        -- ***** Leds
50
        red_leds      : out std_logic_vector(9 downto 0);
51
        green_leds    : out std_logic_vector(7 downto 0);
52
 
53
        -- ***** SD Card
54
        sd_data       : in  std_logic;
55
        sd_cs         : out std_logic;
56
        sd_cmd        : out std_logic;
57 59 ja_rd
        sd_clk        : out std_logic
58 2 ja_rd
    );
59
end c2sb_demo;
60
 
61
architecture minimal of c2sb_demo is
62
 
63
 
64
--##############################################################################
65 59 ja_rd
--
66 2 ja_rd
 
67 75 ja_rd
constant SRAM_ADDR_SIZE : integer := 32;
68 46 ja_rd
 
69 2 ja_rd
--##############################################################################
70
-- RS232 interface signals
71
 
72
signal rx_rdy :             std_logic;
73
signal tx_rdy :             std_logic;
74
signal rs232_data_rx :      std_logic_vector(7 downto 0);
75
signal rs232_status :       std_logic_vector(7 downto 0);
76
signal data_io_out :        std_logic_vector(7 downto 0);
77
signal io_port :            std_logic_vector(7 downto 0);
78
signal read_rx :            std_logic;
79
signal write_tx :           std_logic;
80
 
81
 
82
--##############################################################################
83 63 ja_rd
-- I/O registers
84 2 ja_rd
 
85
 
86 63 ja_rd
signal sd_clk_reg :         std_logic;
87
signal sd_cs_reg :          std_logic;
88
signal sd_cmd_reg :         std_logic;
89
signal sd_do_reg :          std_logic;
90
 
91
 
92 59 ja_rd
-- CPU access to hex display
93 2 ja_rd
signal reg_display :        std_logic_vector(15 downto 0);
94
 
95
 
96
 
97
--##############################################################################
98
-- DE-1 board interface signals
99
 
100 59 ja_rd
-- Synchronization FF chain for asynchronous reset input
101
signal reset_sync :         std_logic_vector(2 downto 0);
102
 
103 2 ja_rd
-- Quad 7-segment display (non multiplexed) & LEDS
104
signal display_data :       std_logic_vector(15 downto 0);
105 59 ja_rd
signal reg_gleds :          std_logic_vector(7 downto 0);
106 2 ja_rd
 
107
-- Clock & reset signals
108
signal clk_1hz :            std_logic;
109
signal clk_master :         std_logic;
110
signal counter_1hz :        std_logic_vector(25 downto 0);
111
signal reset :              std_logic;
112
signal clk :                std_logic;
113
 
114
-- SD control signals
115
signal sd_in :              std_logic;
116
signal reg_sd_dout :        std_logic;
117
signal reg_sd_clk :         std_logic;
118
signal reg_sd_cs :          std_logic;
119
 
120 46 ja_rd
-- MPU interface signals
121 2 ja_rd
signal data_uart :          std_logic_vector(31 downto 0);
122
signal data_uart_status :   std_logic_vector(31 downto 0);
123
signal uart_tx_rdy :        std_logic := '1';
124
signal uart_rx_rdy :        std_logic := '1';
125
 
126 46 ja_rd
signal io_rd_data :         std_logic_vector(31 downto 0);
127
signal io_rd_addr :         std_logic_vector(31 downto 2);
128
signal io_wr_addr :         std_logic_vector(31 downto 2);
129
signal io_wr_data :         std_logic_vector(31 downto 0);
130
signal io_rd_vma :          std_logic;
131
signal io_byte_we :         std_logic_vector(3 downto 0);
132 2 ja_rd
 
133 75 ja_rd
signal mpu_sram_address :   std_logic_vector(SRAM_ADDR_SIZE-1 downto 0);
134
signal mpu_sram_data_rd :   std_logic_vector(15 downto 0);
135
signal mpu_sram_data_wr :   std_logic_vector(15 downto 0);
136 46 ja_rd
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
137
signal mpu_sram_oe_n :      std_logic;
138
 
139 59 ja_rd
-- Converts hex nibble to 7-segment
140
-- Segments ordered as "GFEDCBA"; '0' is ON, '1' is OFF
141
function nibble_to_7seg(nibble : std_logic_vector(3 downto 0))
142
                        return std_logic_vector is
143
begin
144
    case nibble is
145
    when X"0"       => return "0000001";
146
    when X"1"       => return "1001111";
147
    when X"2"       => return "0010010";
148
    when X"3"       => return "0000110";
149
    when X"4"       => return "1001100";
150
    when X"5"       => return "0100100";
151
    when X"6"       => return "0100000";
152
    when X"7"       => return "0001111";
153
    when X"8"       => return "0000000";
154
    when X"9"       => return "0000100";
155
    when X"a"       => return "0001000";
156
    when X"b"       => return "1100000";
157
    when X"c"       => return "0110001";
158
    when X"d"       => return "1000010";
159
    when X"e"       => return "0110000";
160
    when X"f"       => return "0111000";
161
    when others     => return "0111111"; -- can't happen
162
    end case;
163
end function nibble_to_7seg;
164 46 ja_rd
 
165
 
166 2 ja_rd
begin
167
 
168
    mpu: entity work.mips_mpu
169 46 ja_rd
    generic map (
170
        SRAM_ADDR_SIZE => SRAM_ADDR_SIZE
171
    )
172 2 ja_rd
    port map (
173
        interrupt   => '0',
174 59 ja_rd
 
175 46 ja_rd
        -- interface to FPGA i/o devices
176
        io_rd_data  => io_rd_data,
177
        io_rd_addr  => io_rd_addr,
178
        io_wr_addr  => io_wr_addr,
179
        io_wr_data  => io_wr_data,
180
        io_rd_vma   => io_rd_vma,
181
        io_byte_we  => io_byte_we,
182 59 ja_rd
 
183 46 ja_rd
        -- interface to asynchronous 16-bit-wide EXTERNAL SRAM
184
        sram_address    => mpu_sram_address,
185 75 ja_rd
        sram_data_rd    => mpu_sram_data_rd,
186
        sram_data_wr    => mpu_sram_data_wr,
187 46 ja_rd
        sram_byte_we_n  => mpu_sram_byte_we_n,
188
        sram_oe_n       => mpu_sram_oe_n,
189 2 ja_rd
 
190
        uart_rxd    => rxd,
191
        uart_txd    => txd,
192 59 ja_rd
 
193 2 ja_rd
        clk         => clk,
194
        reset       => reset
195
    );
196
 
197
 
198 63 ja_rd
--##############################################################################
199
-- I/O registers
200
--##############################################################################
201 2 ja_rd
 
202 63 ja_rd
hex_display_register:
203
process(clk)
204
begin
205
    if clk'event and clk='1' then
206
        if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
207
            reg_display <= io_wr_data(15 downto 0);
208
        end if;
209
    end if;
210
end process hex_display_register;
211
 
212
sd_control_register:
213
process(clk)
214
begin
215
    if clk'event and clk='1' then
216
        if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"1" then
217
            if io_wr_addr(5)='1' then
218
                sd_clk_reg <= io_wr_addr(4);
219
            end if;
220
            if io_wr_addr(7)='1' then
221
                sd_cs_reg <= io_wr_addr(6);
222
            end if;
223
            if io_wr_addr(11)='1' then
224
                sd_do_reg <= io_wr_data(0);
225
            end if;
226
        end if;
227
    end if;
228
end process sd_control_register;
229
 
230
 
231
-- Show the SD interface signals on the green leds for debug
232
reg_gleds <= sd_clk_reg & sd_in & sd_do_reg & "000" & sd_cmd_reg & sd_cs_reg;
233
 
234
io_rd_data(0) <= sd_in;
235
io_rd_data(31 downto 22) <= switches;
236
 
237
 
238
 
239 59 ja_rd
-- red leds (light with '1') -- some CPU control signals
240 2 ja_rd
red_leds(0) <= '0';
241
red_leds(1) <= '0';
242
red_leds(2) <= '0';
243
red_leds(3) <= '0';
244
red_leds(4) <= '0';
245
red_leds(5) <= '0';
246
red_leds(6) <= '0';
247
red_leds(7) <= '0';
248
red_leds(8) <= '0';
249
red_leds(9) <= clk_1hz;
250
 
251
 
252
--##############################################################################
253
-- terasIC Cyclone II STARTER KIT BOARD -- interface to on-board devices
254
--##############################################################################
255
 
256
--##############################################################################
257 75 ja_rd
-- FLASH (connected to the same mup bus as the sram)
258 2 ja_rd
--##############################################################################
259
 
260 75 ja_rd
flash_we_n <= '1'; -- all write control signals inactive
261 2 ja_rd
flash_reset_n <= '1';
262
 
263 75 ja_rd
flash_addr(21 downto 18) <= (others => '0');
264
flash_addr(17 downto  0) <= mpu_sram_address(17 downto 0); -- FIXME
265 2 ja_rd
 
266 75 ja_rd
-- Flash is decoded at 0xb0000000
267
flash_oe_n <= '0'
268
    when mpu_sram_address(31 downto 27)="10110" and mpu_sram_oe_n='0'
269
    else '1';
270
 
271
 
272
 
273 2 ja_rd
--##############################################################################
274 75 ja_rd
-- SRAM
275 2 ja_rd
--##############################################################################
276
 
277 75 ja_rd
sram_addr <= mpu_sram_address(sram_addr'high+1 downto 1);
278
sram_oe_n <= '0'
279
    when mpu_sram_address(31 downto 27)="00000" and mpu_sram_oe_n='0'
280
    else '1';
281
 
282 46 ja_rd
sram_ub_n <= mpu_sram_byte_we_n(1) and mpu_sram_oe_n;
283
sram_lb_n <= mpu_sram_byte_we_n(0) and mpu_sram_oe_n;
284
sram_ce_n <= '0';
285
sram_we_n <= mpu_sram_byte_we_n(1) and mpu_sram_byte_we_n(0);
286 2 ja_rd
 
287 75 ja_rd
sram_data <= mpu_sram_data_wr when mpu_sram_byte_we_n/="11" else (others => 'Z');
288 2 ja_rd
 
289 75 ja_rd
-- The only reason we need this mux is because we have the static RAM and the
290
-- static flash in separate FPGA pins, whereas in a real world application they
291
-- would be on the same data+address bus
292
mpu_sram_data_rd <=
293
    -- SRAM is decoded at 0x00000000
294
    sram_data when mpu_sram_address(31 downto 27)="00000" else
295
    X"00" & flash_data;
296
 
297
 
298
 
299 2 ja_rd
--##############################################################################
300
-- RESET, CLOCK
301
--##############################################################################
302
 
303
-- Use button 3 as reset
304 75 ja_rd
-- This FF chain only prevents metastability trouble, it does not help with
305
-- switching bounces.
306 59 ja_rd
reset_synchronization:
307
process(clk)
308
begin
309
    if clk'event and clk='1' then
310
        reset_sync(2) <= not buttons(3);
311
        reset_sync(1) <= reset_sync(2);
312
        reset_sync(0) <= reset_sync(1);
313
    end if;
314
end process reset_synchronization;
315 2 ja_rd
 
316 59 ja_rd
reset <= reset_sync(0);
317 2 ja_rd
 
318 59 ja_rd
 
319 2 ja_rd
-- Generate a 1-Hz 'clock' to flash a LED for visual reference.
320
process(clk_50MHz)
321
begin
322
  if clk_50MHz'event and clk_50MHz='1' then
323
    if reset = '1' then
324
      clk_1hz <= '0';
325
      counter_1hz <= (others => '0');
326
    else
327
      if conv_integer(counter_1hz) = 50000000 then
328
        counter_1hz <= (others => '0');
329
        clk_1hz <= not clk_1hz;
330
      else
331
        counter_1hz <= counter_1hz + 1;
332
      end if;
333
    end if;
334
  end if;
335
end process;
336
 
337
-- Master clock is external 50MHz oscillator
338
clk <= clk_50MHz;
339
 
340
 
341
--##############################################################################
342
-- LEDS, SWITCHES
343
--##############################################################################
344
 
345
-- Display the contents of a debug register at the green leds bar
346 59 ja_rd
green_leds <= reg_gleds;
347 2 ja_rd
 
348
 
349
--##############################################################################
350
-- QUAD 7-SEGMENT DISPLAYS
351
--##############################################################################
352
 
353 59 ja_rd
-- Show contents of debug register in hex display
354 2 ja_rd
display_data <= reg_display;
355
 
356 59 ja_rd
 
357 2 ja_rd
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
358 59 ja_rd
hex3 <= nibble_to_7seg(display_data(15 downto 12));
359
hex2 <= nibble_to_7seg(display_data(11 downto  8));
360
hex1 <= nibble_to_7seg(display_data( 7 downto  4));
361
hex0 <= nibble_to_7seg(display_data( 3 downto  0));
362 2 ja_rd
 
363
--##############################################################################
364
-- SD card interface
365
--##############################################################################
366
 
367 75 ja_rd
-- Connect to FFs for use in bit-banged interface (still unused)
368 63 ja_rd
sd_cs       <= sd_cs_reg;
369
sd_cmd      <= sd_do_reg;
370
sd_clk      <= sd_clk_reg;
371
sd_in       <= sd_data;
372 2 ja_rd
 
373 63 ja_rd
 
374 2 ja_rd
--##############################################################################
375
-- SERIAL
376
--##############################################################################
377
 
378
--  Embedded in the MPU entity
379
 
380
end minimal;

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