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1 42 ja_rd
--------------------------------------------------------------------------------
2 46 ja_rd
-- mips_cache_stub.vhdl -- 1-word cache module
3 42 ja_rd
--
4 46 ja_rd
-- This module has the same interface and logic as a real cache but the cache
5
-- memory is just 1 word for each of code and data.
6 43 ja_rd
--
7 46 ja_rd
-- It interfaces the CPU to the following:
8 42 ja_rd
--
9 46 ja_rd
--  1.- Internal 32-bit-wide BRAM for read only
10 42 ja_rd
--  2.- Internal 32-bit I/O bus
11
--  3.- External 16-bit wide SRAM
12
--
13 46 ja_rd
-- The SRAM memory interface signals are meant to connect directly to FPGA pins
14
-- and all outputs are registered (tco should be minimal).
15
-- SRAM data inputs are NOT registered, though. They go through a couple muxes
16
-- before reaching the first register so watch out for tsetup.
17
-- The SRAM is assumed to be fast enough to read or write in a clock cycle.
18 42 ja_rd
--
19 46 ja_rd
-- Obviously this module provides no performance gain; on the contrary, by
20
-- coupling the CPU to slow external memory (16 bit bus) it actually slows it
21
-- down. The purpose of this module is just to test the SRAM interface and the
22
-- cache logic and timing.
23
--
24 42 ja_rd
--------------------------------------------------------------------------------
25 58 ja_rd
-- External FPGA signals
26
--
27
-- This module has signals meant to connect directly to FPGA pins: the SRAM
28
-- interface. They are either direct register outputs or at most with an 
29
-- intervening 2-mux, in order to minimize the Tco (clock-to-output).
30
--
31
-- The Tco of these signals has to be accounted for in the real SRAM interface.
32
-- For example, under Quartus-2 and with a Cyclone-2 grade -7 device, the
33
-- worst Tco for the SRAM data pins is below 5 ns, enough to use a 10ns SRAM
34
-- with a 20 ns clock cycle.
35
-- Anyway, you need to take care of this yourself.
36
--
37
--------------------------------------------------------------------------------
38
-- Interface to CPU
39
--
40
-- 1.- All signals coming from the CPU are registered.
41
-- 2.- All CPU inputs come directly from a register, or at most have a 2-mux in
42
--     between.
43
-- 
44
-- This means this block will not degrade the timing performance of the system, 
45
-- as long as its logic is shallower than the current bottleneck (the ALU).
46
--
47
--------------------------------------------------------------------------------
48 46 ja_rd
-- KNOWN TROUBLE:
49
-- 
50 58 ja_rd
-- Apart from the very rough looks of the code, there's a few known problems:
51 46 ja_rd
--
52 72 ja_rd
-- 1.- Write address setup and hold wrt. WE\ not guaranteed
53
--      WE\ needs to be asserted later and deasserted earlier. The easy way 
54
--      would be using two extra cycles. Must find some less cosly way.
55
--      So far, in my particular test conditions, this is not giving me trouble
56
--      so this will have to wait.
57
-- 
58
-- 2.- Access to unmapped areas will crash the CPU
59 46 ja_rd
--      A couple states are missing in the state machine for handling accesses 
60
--      to unmapped areas. I haven't yet decided how to handle that (return 
61 72 ja_rd
--      zero, trigger trap, mirror another mapped area...).
62
--
63
-- 3.- Code refills from SRAM is unimplemented yet
64 58 ja_rd
--      To be done for sheer lack of time.
65 72 ja_rd
--
66 58 ja_rd
-- 4.- Does not work as a real 1-word cache yet
67 46 ja_rd
--      That functionality is still missing, all accesses 'miss'. It should be
68
--      implemented, as a way to test the real cache logic on a small scale.
69
--
70
--------------------------------------------------------------------------------
71 42 ja_rd
 
72
library ieee;
73
use ieee.std_logic_1164.all;
74
use ieee.std_logic_arith.all;
75
use ieee.std_logic_unsigned.all;
76
use work.mips_pkg.all;
77
 
78 58 ja_rd
 
79 42 ja_rd
entity mips_cache_stub is
80
    generic (
81
        BRAM_ADDR_SIZE : integer := 10;
82
        SRAM_ADDR_SIZE : integer := 17
83
    );
84
    port(
85
        clk             : in std_logic;
86
        reset           : in std_logic;
87 46 ja_rd
 
88 42 ja_rd
        -- Interface to CPU core
89
        data_rd_addr    : in std_logic_vector(31 downto 0);
90
        data_rd         : out std_logic_vector(31 downto 0);
91
        data_rd_vma     : in std_logic;
92 46 ja_rd
 
93 42 ja_rd
        code_rd_addr    : in std_logic_vector(31 downto 2);
94
        code_rd         : out std_logic_vector(31 downto 0);
95
        code_rd_vma     : in std_logic;
96 46 ja_rd
 
97 42 ja_rd
        data_wr_addr    : in std_logic_vector(31 downto 2);
98
        byte_we         : in std_logic_vector(3 downto 0);
99
        data_wr         : in std_logic_vector(31 downto 0);
100 46 ja_rd
 
101 42 ja_rd
        mem_wait        : out std_logic;
102 46 ja_rd
        cache_enable    : in std_logic;
103
 
104 42 ja_rd
        -- interface to FPGA i/o devices
105
        io_rd_data      : in std_logic_vector(31 downto 0);
106
        io_rd_addr      : out std_logic_vector(31 downto 2);
107
        io_wr_addr      : out std_logic_vector(31 downto 2);
108
        io_wr_data      : out std_logic_vector(31 downto 0);
109
        io_rd_vma       : out std_logic;
110
        io_byte_we      : out std_logic_vector(3 downto 0);
111 46 ja_rd
 
112 42 ja_rd
        -- interface to synchronous 32-bit-wide FPGA BRAM (possibly used as ROM)
113
        bram_rd_data    : in std_logic_vector(31 downto 0);
114
        bram_wr_data    : out std_logic_vector(31 downto 0);
115
        bram_rd_addr    : out std_logic_vector(BRAM_ADDR_SIZE+1 downto 2);
116
        bram_wr_addr    : out std_logic_vector(BRAM_ADDR_SIZE+1 downto 2);
117 46 ja_rd
        bram_byte_we    : out std_logic_vector(3 downto 0);
118
        bram_data_rd_vma: out std_logic;
119
 
120 42 ja_rd
        -- interface to asynchronous 16-bit-wide EXTERNAL SRAM
121 46 ja_rd
        sram_address    : out std_logic_vector(SRAM_ADDR_SIZE downto 1);
122 42 ja_rd
        sram_databus    : inout std_logic_vector(15 downto 0);
123
        sram_byte_we_n  : out std_logic_vector(1 downto 0);
124
        sram_oe_n       : out std_logic
125
    );
126
end entity mips_cache_stub;
127
 
128
 
129
 
130
architecture stub of mips_cache_stub is
131
 
132 72 ja_rd
-- Wait state counter -- we're supporting static memory from 10 to >100 ns
133
subtype t_wait_state_counter is std_logic_vector(2 downto 0);
134
 
135 58 ja_rd
-- state machines: definition of states -----------------------------
136
 
137 46 ja_rd
type t_code_cache_state is (
138 58 ja_rd
    code_normal,                -- 
139
    code_wait_for_dcache,       -- wait for D-cache to stop using the buses
140 46 ja_rd
 
141
    code_refill_bram_0,         -- pc in bram_rd_addr
142
    code_refill_bram_1,         -- op in bram_rd
143 58 ja_rd
    code_refill_bram_2,         -- op in code_rd 
144 46 ja_rd
 
145 58 ja_rd
    code_refill_sram_0,         -- FIXME code refill from SRAM unimplemented
146 46 ja_rd
    code_refill_sram_1,
147
    code_refill_sram_2,
148
 
149 58 ja_rd
    code_bug                    -- caught an error in the state machine
150 46 ja_rd
   );
151
 
152 58 ja_rd
-- I-cache state machine state register & next state
153 46 ja_rd
signal cps, cns :           t_code_cache_state;
154 72 ja_rd
-- Wait state counter, formally part of the state machine register
155
signal code_wait_ctr :      t_wait_state_counter;
156 46 ja_rd
 
157
 
158
type t_data_cache_state is (
159
    data_normal,
160
 
161 58 ja_rd
    data_refill_sram_0,         -- rd addr in SRAM addr bus (low hword)
162
    data_refill_sram_1,         -- rd addr in SRAM addr bus (high hword)
163 46 ja_rd
 
164
    data_refill_bram_0,         -- rd addr in bram_rd_addr
165
    data_refill_bram_1,         -- rd data in bram_rd_data
166 42 ja_rd
 
167 46 ja_rd
    data_read_io_0,             -- rd addr on io_rd_addr, io_vma active
168
    data_read_io_1,             -- rd data on io_rd_data
169 58 ja_rd
 
170
    data_write_io_0,            -- wr addr & data in io_wr_*, io_byte_we active
171 46 ja_rd
 
172 72 ja_rd
    data_writethrough_sram_0a,  -- wr addr & data in SRAM buses (low hword)
173
    data_writethrough_sram_0b,  -- WE asserted
174
    data_writethrough_sram_0c,  -- WE deasserted
175
    data_writethrough_sram_1a,  -- wr addr & data in SRAM buses (high hword)
176
    data_writethrough_sram_1b,  -- WE asserted
177
    data_writethrough_sram_1c,  -- WE deasserted
178 42 ja_rd
 
179 58 ja_rd
    data_ignore_write,          -- hook for raising error flag FIXME untested
180 72 ja_rd
    data_ignore_read,           -- hook for raising error flag FIXME untested
181 42 ja_rd
 
182 58 ja_rd
    data_bug                    -- caught an error in the state machine
183 42 ja_rd
   );
184
 
185
 
186 58 ja_rd
-- D-cache state machine state register & next state
187 46 ja_rd
signal dps, dns :           t_data_cache_state;
188 72 ja_rd
-- Wait state counter, formally part of the state machine register
189
signal dws_ctr, dws :       t_wait_state_counter;
190
signal load_dws_ctr :       std_logic;
191
signal dws_wait_done :      std_logic;
192 42 ja_rd
 
193 72 ja_rd
 
194
 
195 58 ja_rd
-- CPU interface registers ------------------------------------------
196
signal data_rd_addr_reg :   t_pc;
197
signal data_wr_addr_reg :   t_pc;
198
signal code_rd_addr_reg :   t_pc;
199 46 ja_rd
 
200 42 ja_rd
signal data_wr_reg :        std_logic_vector(31 downto 0);
201
signal byte_we_reg :        std_logic_vector(3 downto 0);
202
 
203 58 ja_rd
-- SRAM interface ---------------------------------------------------
204
-- Stores first (high) HW read from SRAM
205
signal sram_rd_data_reg :   std_logic_vector(31 downto 16);
206
-- Data read from SRAM, valid in refill_1
207
signal sram_rd_data :       t_word;
208 46 ja_rd
 
209
 
210 58 ja_rd
 
211
-- I-cache -- most of this is unimplemented -------------------------
212
 
213 46 ja_rd
subtype t_code_tag is std_logic_vector(23 downto 2);
214
signal code_cache_tag :     t_code_tag;
215
signal code_cache_tag_store : t_code_tag;
216
signal code_cache_store :   t_word;
217 58 ja_rd
-- code word read from cache
218 46 ja_rd
signal code_cache_rd :      t_word;
219 58 ja_rd
-- raised whel code_cache_rd is not valid due to a cache miss
220 46 ja_rd
signal code_miss :          std_logic;
221
 
222 58 ja_rd
-- '1' when the I-cache state machine stalls the pipeline (mem_wait)
223
signal code_wait :          std_logic;
224 46 ja_rd
 
225 58 ja_rd
-- D-cache -- most of this is unimplemented -------------------------
226 46 ja_rd
subtype t_data_tag is std_logic_vector(23 downto 2);
227
signal data_cache_tag :     t_data_tag;
228
signal data_cache_tag_store : t_data_tag;
229
signal data_cache_store :   t_word;
230 58 ja_rd
-- active when there's a write waiting to be done
231 46 ja_rd
signal write_pending :      std_logic;
232 58 ja_rd
-- active when there's a read waiting to be done
233 46 ja_rd
signal read_pending :       std_logic;
234 58 ja_rd
-- data word read from cache
235 46 ja_rd
signal data_cache_rd :      t_word;
236 58 ja_rd
-- '1' when data_cache_rd is not valid due to a cache miss
237 46 ja_rd
signal data_miss :          std_logic;
238
 
239 58 ja_rd
-- '1' when the D-cache state machine stalls the pipeline (mem_wait)
240 46 ja_rd
signal data_wait :          std_logic;
241
 
242
 
243 58 ja_rd
-- Address decoding -------------------------------------------------
244
 
245
-- Address slices used to decode
246 46 ja_rd
signal code_rd_addr_mask :  t_addr_decode;
247
signal data_rd_addr_mask :  t_addr_decode;
248
signal data_wr_addr_mask :  t_addr_decode;
249
 
250 58 ja_rd
-- Memory map area being accessed for each of the 3 buses:
251 64 ja_rd
signal code_rd_attr :       t_range_attr;
252
signal data_rd_attr :       t_range_attr;
253
signal data_wr_attr :       t_range_attr;
254 58 ja_rd
 
255 42 ja_rd
begin
256
 
257 58 ja_rd
--------------------------------------------------------------------------------
258
-- Cache control state machines 
259 42 ja_rd
 
260 46 ja_rd
cache_state_machine_regs:
261 42 ja_rd
process(clk)
262
begin
263
   if clk'event and clk='1' then
264
        if reset='1' then
265 46 ja_rd
            cps <= code_normal;
266
            dps <= data_normal;
267 42 ja_rd
        else
268 46 ja_rd
            cps <= cns;
269
            dps <= dns;
270 42 ja_rd
        end if;
271
    end if;
272 46 ja_rd
end process cache_state_machine_regs;
273 42 ja_rd
 
274 64 ja_rd
-- (The code state machine occasionally 'waits' for the D-cache)
275 46 ja_rd
code_state_machine_transitions:
276 72 ja_rd
process(cps, dps, code_rd_vma, code_miss, code_rd_attr,
277 58 ja_rd
        write_pending, read_pending)
278 42 ja_rd
begin
279 46 ja_rd
    case cps is
280
    when code_normal =>
281 64 ja_rd
        -- FIXME wrong logic, these signals are not active in the same cycle
282 58 ja_rd
        if code_rd_vma='1' and code_miss='1' and
283
           read_pending='0' and write_pending='0' then
284
            cns <= code_refill_bram_0; -- FIXME check memory area, SRAM!
285 42 ja_rd
        else
286 46 ja_rd
            cns <= cps;
287 42 ja_rd
        end if;
288
 
289 46 ja_rd
    when code_refill_bram_0 =>
290
        cns <= code_refill_bram_1;
291 42 ja_rd
 
292 46 ja_rd
    when code_refill_bram_1 =>
293
        cns <= code_refill_bram_2;
294 42 ja_rd
 
295 46 ja_rd
    when code_refill_bram_2 =>
296
        if dps/=data_normal and read_pending='0' and write_pending='0' then
297
            cns <= code_wait_for_dcache;
298 42 ja_rd
        else
299 46 ja_rd
            cns <= code_normal;
300 42 ja_rd
        end if;
301
 
302 46 ja_rd
    when code_wait_for_dcache =>
303
        -- if D-cache is busy, wait for it to become idle
304
        if dps/=data_normal then
305
            cns <= cps;
306
        elsif code_miss='1' then
307
            cns <= code_refill_bram_1; -- FIXME check memory area
308 42 ja_rd
        else
309 46 ja_rd
            cns <= code_normal;
310 42 ja_rd
        end if;
311
 
312 58 ja_rd
    when code_bug =>
313
        -- Something weird happened, we have 1 cycle to do something like raise
314
        -- an error flag, etc. After 1 cycle, back to normal.
315 46 ja_rd
        cns <= code_normal;
316
 
317 42 ja_rd
    when others =>
318 58 ja_rd
        -- We should never arrive here. If we do we handle it in state code_bug.
319 46 ja_rd
        cns <= code_bug;
320 42 ja_rd
    end case;
321 46 ja_rd
end process code_state_machine_transitions;
322 42 ja_rd
 
323
 
324 58 ja_rd
-- This state machine does not overlap IO/BRAM/SRAM accesses for simplicity.
325
 
326 46 ja_rd
data_state_machine_transitions:
327 72 ja_rd
process(dps, write_pending, read_pending,
328
        data_rd_attr, data_wr_attr, dws_wait_done)
329 46 ja_rd
begin
330
    case dps is
331
    when data_normal =>
332
        if write_pending='1' then
333 72 ja_rd
            case data_wr_attr.mem_type is
334 64 ja_rd
            when MT_BRAM        => dns <= data_ignore_write;
335 72 ja_rd
            when MT_SRAM_16B    => dns <= data_writethrough_sram_0a;
336 64 ja_rd
            when MT_IO_SYNC     => dns <= data_write_io_0;
337 72 ja_rd
            -- FIXME ignore write to undecoded area (clear pending flag)                        
338
            when others         => dns <= dps;
339 46 ja_rd
            end case;
340
 
341
        elsif read_pending='1' then
342 72 ja_rd
            case data_rd_attr.mem_type is
343 64 ja_rd
            when MT_BRAM        => dns <= data_refill_bram_0;
344
            when MT_SRAM_16B    => dns <= data_refill_sram_0;
345
            when MT_IO_SYNC     => dns <= data_read_io_0;
346 72 ja_rd
            -- FIXME ignore read from undecoded area (clear pending flag) 
347
            when others         => dns <= data_ignore_read;
348 46 ja_rd
            end case;
349
        else
350
            dns <= dps;
351
        end if;
352 42 ja_rd
 
353 46 ja_rd
    when data_write_io_0 =>
354
        dns <= data_normal;
355
 
356
    when data_read_io_0 =>
357
        dns <= data_read_io_1;
358
 
359
    when data_read_io_1 =>
360
        dns <= data_normal;
361 42 ja_rd
 
362 46 ja_rd
    when data_refill_sram_0 =>
363 72 ja_rd
        if dws_wait_done='1' then
364
            dns <= data_refill_sram_1;
365
        else
366
            dns <= dps;
367
        end if;
368 42 ja_rd
 
369 46 ja_rd
    when data_refill_sram_1 =>
370 72 ja_rd
        if dws_wait_done='1' then
371
            dns <= data_normal;
372
        else
373
            dns <= dps;
374
        end if;
375 42 ja_rd
 
376 46 ja_rd
    when data_refill_bram_0 =>
377
        dns <= data_refill_bram_1;
378
 
379
    when data_refill_bram_1 =>
380
        dns <= data_normal;
381
 
382 72 ja_rd
    when data_writethrough_sram_0a =>
383
        dns <= data_writethrough_sram_0b;
384
 
385
    when data_writethrough_sram_0b =>
386
        if dws_wait_done='1' then
387
            dns <= data_writethrough_sram_0c;
388
        else
389
            dns <= dps;
390
        end if;
391
 
392
    when data_writethrough_sram_0c =>
393
        dns <= data_writethrough_sram_1a;
394
 
395
    when data_writethrough_sram_1a =>
396
        dns <= data_writethrough_sram_1b;
397
 
398
    when data_writethrough_sram_1b =>
399
        if dws_wait_done='1' then
400
            dns <= data_writethrough_sram_1c;
401
        else
402
            dns <= dps;
403
        end if;
404 46 ja_rd
 
405 72 ja_rd
    when data_writethrough_sram_1c =>
406 46 ja_rd
        dns <= data_normal;
407 72 ja_rd
 
408 46 ja_rd
 
409
    when data_ignore_write =>
410
        dns <= data_normal;
411
 
412 72 ja_rd
    when data_ignore_read =>
413
        dns <= data_normal;
414
 
415 46 ja_rd
    when data_bug =>
416 58 ja_rd
        -- Something weird happened, we have 1 cycle to do something like raise
417
        -- an error flag, etc. After 1 cycle, back to normal.    
418 46 ja_rd
        dns <= data_normal;
419
 
420
    when others =>
421 58 ja_rd
        -- Should never arrive here. If we do, we handle it in state data_bug.
422 46 ja_rd
        dns <= data_bug;
423
    end case;
424
end process data_state_machine_transitions;
425
 
426 72 ja_rd
load_dws_ctr <= '1' when
427
    (dns=data_refill_sram_0 and dps/=data_refill_sram_0) or
428
    (dns=data_refill_sram_1 and dps/=data_refill_sram_1) or
429
    (dns=data_writethrough_sram_0a) or
430
    (dns=data_writethrough_sram_1a)
431
    else '0';
432 46 ja_rd
 
433 72 ja_rd
with dns select dws <=
434
    data_rd_attr.wait_states    when data_refill_sram_0,
435
    data_wr_attr.wait_states    when data_writethrough_sram_0a,
436
    data_wr_attr.wait_states    when data_writethrough_sram_1a,
437
    data_wr_attr.wait_states    when others;
438
 
439
data_wait_state_counter:
440
process(clk)
441
begin
442
    if clk'event and clk='1' then
443
        if reset='1' then
444
            dws_ctr <= (others => '0');
445
        else
446
            if load_dws_ctr='1' then
447
                dws_ctr <= dws;
448
            elsif dws_wait_done='0' then
449
                dws_ctr <= dws_ctr - 1;
450
            end if;
451
        end if;
452
    end if;
453
end process data_wait_state_counter;
454
 
455
dws_wait_done <= '1' when dws_ctr="000" else '0';
456
 
457
 
458 46 ja_rd
--------------------------------------------------------------------------------
459
-- CPU interface registers and address decoding --------------------------------
460
 
461
 
462
-- Everything coming and going to the CPU is registered, so that the CPU has
463
-- some timing marging.
464
 
465 58 ja_rd
cpu_data_interface_registers:
466 42 ja_rd
process(clk)
467
begin
468
    if clk'event and clk='1' then
469
        if reset='1' then
470 46 ja_rd
            write_pending <= '0';
471
            read_pending <= '0';
472
            byte_we_reg <= "0000";
473 42 ja_rd
        else
474 46 ja_rd
            -- Raise 'read_pending' at the 1st cycle of a read, clear it when
475
            -- the read (and/or refill) operation has been done.
476
            -- data_rd_addr_reg always has the addr of any pending read
477 42 ja_rd
            if data_rd_vma='1' then
478 46 ja_rd
                read_pending <= '1';
479
                data_rd_addr_reg <= data_rd_addr(31 downto 2);
480
            elsif dps=data_refill_sram_1 or
481
                  dps=data_refill_bram_1 or
482 72 ja_rd
                  dps=data_read_io_0 or
483
                  dps=data_ignore_read then
484 46 ja_rd
                read_pending <= '0';
485 42 ja_rd
            end if;
486 46 ja_rd
 
487
            -- Raise 'write_pending' at the 1st cycle of a read, clear it when
488
            -- the write (writethrough actually) operation has been done.
489
            -- data_wr_addr_reg always has the addr of any pending write
490
            if byte_we/="0000" and dps=data_normal then
491
                byte_we_reg <= byte_we;
492
                data_wr_reg <= data_wr;
493
                data_wr_addr_reg <= data_wr_addr;
494
                write_pending <= '1';
495 72 ja_rd
            elsif dps=data_writethrough_sram_1b or
496 46 ja_rd
                  dps=data_write_io_0 or
497
                  dps=data_ignore_write then
498
                write_pending <= '0';
499
                byte_we_reg <= "0000";
500
            end if;
501 58 ja_rd
 
502
        end if;
503
    end if;
504
end process cpu_data_interface_registers;
505 46 ja_rd
 
506 58 ja_rd
cpu_code_interface_registers:
507
process(clk)
508
begin
509
    if clk'event and clk='1' then
510
        -- Register code fetch addresses only when they are valid; so that
511
        -- code_rd_addr_reg always holds the last fetch address.
512
        if (cps=code_normal and code_rd_vma='1') or
513
            cps=code_refill_bram_2 then -- FIXME explain this term
514
            code_rd_addr_reg <= code_rd_addr;
515 42 ja_rd
        end if;
516
    end if;
517 58 ja_rd
end process cpu_code_interface_registers;
518 42 ja_rd
 
519 58 ja_rd
 
520 46 ja_rd
-- Address decoding ------------------------------------------------------------
521 42 ja_rd
 
522 46 ja_rd
-- Decoding is done on the high bits of the address only, there'll be mirroring.
523
-- Write to areas not explicitly decoded will be silently ignored. Reads will
524
-- get undefined data.
525
 
526
code_rd_addr_mask <= code_rd_addr_reg(31 downto t_addr_decode'low);
527
data_rd_addr_mask <= data_rd_addr_reg(31 downto t_addr_decode'low);
528
data_wr_addr_mask <= data_wr_addr_reg(31 downto t_addr_decode'low);
529
 
530
 
531 64 ja_rd
code_rd_attr <= decode_addr(code_rd_addr_mask);
532
data_rd_attr <= decode_addr(data_rd_addr_mask);
533
data_wr_attr <= decode_addr(data_wr_addr_mask);
534 46 ja_rd
 
535 64 ja_rd
 
536 46 ja_rd
--------------------------------------------------------------------------------
537 58 ja_rd
-- BRAM interface
538 46 ja_rd
 
539 58 ja_rd
 
540
-- BRAMm address can come from code or data buses
541
-- (note both inputs to this mux are register outputs)
542
bram_rd_addr <=
543
    data_rd_addr_reg(bram_rd_addr'high downto 2) when dps=data_refill_bram_0
544 46 ja_rd
    else code_rd_addr_reg(bram_rd_addr'high downto 2) ;
545
 
546 58 ja_rd
bram_data_rd_vma <= '1' when dps=data_refill_bram_1 else '0';
547
 
548
 
549
 
550
--------------------------------------------------------------------------------
551
-- Code cache 
552
 
553
-- All the tag match logic is unfinished and will be simplified away in synth.
554
 
555
-- CPU is wired directly to cache output, no muxes
556 46 ja_rd
code_rd <= code_cache_rd;
557
 
558
-- FIXME Actual 1-word cache functionality is unimplemented yet
559 58 ja_rd
code_miss <= '1'; -- always miss
560 46 ja_rd
 
561
-- Read cache code and tag from code store
562
code_cache_rd <= code_cache_store;
563
code_cache_tag <= code_cache_tag_store;
564
 
565
code_cache_memory:
566 42 ja_rd
process(clk)
567
begin
568
    if clk'event and clk='1' then
569 46 ja_rd
 
570
 
571 42 ja_rd
        if reset='1' then
572 46 ja_rd
            -- in the real hardware the tag store can't be reset and it's up
573
            -- to the SW to initialize the cache.
574
            code_cache_tag_store <= (others => '0');
575
            code_cache_store <= (others => '0');
576 42 ja_rd
        else
577 46 ja_rd
            -- Refill cache if necessary
578
            if cps=code_refill_bram_1 then
579
                code_cache_tag_store <=
580
                    "01" & code_rd_addr_reg(t_code_tag'high-2 downto t_code_tag'low);
581
                code_cache_store <= bram_rd_data;
582
            --elsif cps=code_refill_sram_2 then
583
            --    code_cache_tag_store <=
584
            --        "01" & code_rd_addr_reg(t_code_tag'high-2 downto t_code_tag'low);
585
            --    code_cache_store <= sram_rd_data;
586 42 ja_rd
            end if;
587 46 ja_rd
        end if;
588
    end if;
589
end process code_cache_memory;
590
 
591
 
592
--------------------------------------------------------------------------------
593
-- Data cache
594
 
595 58 ja_rd
-- CPU data input mux: direct cache output OR uncached io input
596 46 ja_rd
with dps select data_rd <=
597
    io_rd_data      when data_read_io_1,
598
    data_cache_rd   when others;
599
 
600 58 ja_rd
-- All the tag match logic is unfinished and will be simplified away in synth.
601
-- The 'cache' is really a single register.
602 46 ja_rd
data_cache_rd <= data_cache_store;
603
data_cache_tag <= data_cache_tag_store;
604
 
605
data_cache_memory:
606
process(clk)
607
begin
608
    if clk'event and clk='1' then
609
        if reset='1' then
610
            -- in the real hardware the tag store can't be reset and it's up
611
            -- to the SW to initialize the cache.
612
            data_cache_tag_store <= (others => '0');
613
            data_cache_store <= (others => '0');
614
        else
615
            -- Refill data cache if necessary
616
            if dps=data_refill_sram_1 then
617
                data_cache_tag_store <=
618
                    "01" & data_rd_addr_reg(t_data_tag'high-2 downto t_data_tag'low);
619
                data_cache_store <= sram_rd_data;
620
            elsif dps=data_refill_bram_1 then
621
                data_cache_tag_store <=
622
                    "01" & data_rd_addr_reg(t_data_tag'high-2 downto t_data_tag'low);
623
                data_cache_store <= bram_rd_data;
624 42 ja_rd
            end if;
625
        end if;
626
    end if;
627 46 ja_rd
end process data_cache_memory;
628 42 ja_rd
 
629 58 ja_rd
 
630
--------------------------------------------------------------------------------
631
-- SRAM interface
632
 
633
-- Note this signals are meantto be connected directly to FPGA pins (and then
634
-- to a SRAM, of course). They are the only signals whose tco we care about.
635
 
636
-- FIXME should add a SRAM CE\ signal
637
 
638
-- SRAM address bus (except for LSB) comes from cpu code or data addr registers
639 46 ja_rd
with dps select sram_address(sram_address'high downto 2) <=
640
    data_rd_addr_reg(sram_address'high downto 2)    when data_refill_sram_0,
641
    data_rd_addr_reg(sram_address'high downto 2)    when data_refill_sram_1,
642
    data_wr_addr_reg(sram_address'high downto 2)    when others;
643 42 ja_rd
 
644 58 ja_rd
-- SRAM addr bus LSB depends on the D-cache state because we read/write the
645
-- halfwords sequentially in successive cycles.
646 46 ja_rd
with dps select sram_address(1) <=
647 72 ja_rd
    '0'     when data_writethrough_sram_0a,
648
    '0'     when data_writethrough_sram_0b,
649
    '0'     when data_writethrough_sram_0c,
650
    '1'     when data_writethrough_sram_1a,
651
    '1'     when data_writethrough_sram_1b,
652
    '1'     when data_writethrough_sram_1c,
653 46 ja_rd
    '0'     when data_refill_sram_0,
654
    '1'     when data_refill_sram_1,
655
    '0'     when others;
656 42 ja_rd
 
657 58 ja_rd
-- SRAM databus i(when used for output) comes from either hword of the data
658
-- write register.
659 46 ja_rd
with dps select sram_databus <=
660 72 ja_rd
    data_wr_reg(31 downto 16)   when data_writethrough_sram_0a,
661
    data_wr_reg(31 downto 16)   when data_writethrough_sram_0b,
662
    data_wr_reg(31 downto 16)   when data_writethrough_sram_0c,
663
    data_wr_reg(15 downto  0)   when data_writethrough_sram_1a,
664
    data_wr_reg(15 downto  0)   when data_writethrough_sram_1b,
665
    data_wr_reg(15 downto  0)   when data_writethrough_sram_1c,
666 46 ja_rd
    (others => 'Z')             when others;
667 42 ja_rd
 
668 58 ja_rd
-- The byte_we is split in two similarly.
669 46 ja_rd
with dps select sram_byte_we_n <=
670 72 ja_rd
    not byte_we_reg(3 downto 2) when data_writethrough_sram_0b,
671
    not byte_we_reg(1 downto 0) when data_writethrough_sram_1b,
672 46 ja_rd
    "11"                        when others;
673 42 ja_rd
 
674 58 ja_rd
-- SRAM OE\ is only asserted low for read cycles
675 46 ja_rd
with dps select sram_oe_n <=
676
    '0' when data_refill_sram_0,
677
    '0' when data_refill_sram_1,
678
    '1' when others;
679 42 ja_rd
 
680 58 ja_rd
-- When eading from the SRAM, read word comes from read hword register and 
681
-- SRAM bus (read register is loaded in previous cycle).
682 46 ja_rd
sram_rd_data <= sram_rd_data_reg & sram_databus;
683 42 ja_rd
 
684 58 ja_rd
sram_input_halfword_register:
685 46 ja_rd
process(clk)
686
begin
687
    if clk'event and clk='1' then
688 72 ja_rd
        if dps=data_refill_sram_0 then
689
            sram_rd_data_reg <= sram_databus;
690
        end if;
691 46 ja_rd
    end if;
692 58 ja_rd
end process sram_input_halfword_register;
693 42 ja_rd
 
694
 
695
--------------------------------------------------------------------------------
696 58 ja_rd
-- I/O interface -- IO is assumed to behave like synchronous memory
697 42 ja_rd
 
698 46 ja_rd
io_byte_we <= byte_we_reg when dps=data_write_io_0 else "0000";
699
io_rd_addr <= data_rd_addr_reg;
700
io_wr_addr <= data_wr_addr_reg;
701
io_wr_data <= data_wr_reg;
702
io_rd_vma <= '1' when dps=data_read_io_0 else '0';
703 42 ja_rd
 
704 58 ja_rd
 
705 46 ja_rd
--------------------------------------------------------------------------------
706 58 ja_rd
-- CPU stall control
707 42 ja_rd
 
708 58 ja_rd
-- Stall the CPU when either state machine needs it
709 46 ja_rd
mem_wait <= (code_wait or data_wait) and not reset;
710 42 ja_rd
 
711 58 ja_rd
-- Assert code_wait until the cycle where the CPU has valid code word on its
712
-- code bus
713 46 ja_rd
with cps select code_wait <=
714
    '1' when code_refill_bram_0,
715
    '1' when code_refill_bram_1,
716
    '1' when code_refill_bram_2,
717
    '1' when code_wait_for_dcache,
718
    '0' when others;
719 42 ja_rd
 
720 58 ja_rd
-- Assert code_wait until the cycle where the CPU has valid data word on its
721
-- code bus AND no other operations are ongoing that may use the external buses.
722 46 ja_rd
with dps select data_wait <=
723 72 ja_rd
    '1' when data_writethrough_sram_0a,
724
    '1' when data_writethrough_sram_0b,
725
    '1' when data_writethrough_sram_0c,
726
    '1' when data_writethrough_sram_1a,
727
    '1' when data_writethrough_sram_1b,
728
    '1' when data_writethrough_sram_1c,
729 46 ja_rd
    '1' when data_refill_sram_0,
730
    '1' when data_refill_sram_1,
731
    '1' when data_refill_bram_0,
732
    '1' when data_refill_bram_1,
733
    '1' when data_read_io_0,
734
    '0' when others;
735
 
736 42 ja_rd
end architecture stub;

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