OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Blame information for rev 193

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ja_rd
--------------------------------------------------------------------------------
2
-- ion_cpu.vhdl -- MIPS-I(tm) compatible CPU core
3
--------------------------------------------------------------------------------
4
-- project:       ION (http://www.opencores.org/project,ion_cpu)
5
-- author:        Jose A. Ruiz (ja_rd@hotmail.com)
6
-- created:       Jan/11/2011
7 153 ja_rd
-- last modified: Jun/05/2011 (ja_rd@hotmail.com)
8 2 ja_rd
--------------------------------------------------------------------------------
9 153 ja_rd
-- Please read file /doc/ion_project.txt for usage instructions.
10
--------------------------------------------------------------------------------
11 2 ja_rd
--### MIPS-I things not implemented
12
--
13 159 ja_rd
-- 1.- Most of the R3000 CP0 registers and of course all of the CP1.
14
-- 2.- External interrupts missing, with CP0.SR IR, NMI and IM7..0 flags.
15 2 ja_rd
--
16
--### Things with provisional implementation
17
-- 
18
-- 1.- Load interlocks: the pipeline is stalled for every load instruction, even
19
--     if the target register is not used in the following instruction. So that
20
--     every load takes two cycles.
21 121 ja_rd
--     The interlock logic should check register indices (@note2)
22 153 ja_rd
-- 2.- CP0 SR (status register) bits KUo/IEo & KUP/IEp are missing.
23
--     This means that EXCEPTIONS CAN'T BE NESTED in this version of the CPU.
24
-- 3.- Invalid instruction side effects:
25
--     Invalid opcodes do trap but the logic that prevents bad opcodes from
26
--     having side affects has not been tested yet.
27
-- 4.- Kernel/user status.
28
--     When in user mode, COP* instructions will trigger a 'CpU' exception.
29
--     BUT there's no address checking and user code can still access kernel 
30
--     space in this version.
31
--     Besides, see point 2 above about the missing SR bits.
32 2 ja_rd
--
33
--------------------------------------------------------------------------------
34 159 ja_rd
-- KNOWN BUGS:
35
--
36 161 ja_rd
-- 1.- The instruction executed right after entering user mode (i.e. the 
37
--     instruction after the MTC0 or RFE that clears the KU flag) is executed 
38
--     in kernel mode (instead of user mode). This is a gapping security hole,
39
--     in case it makes any sense to speak of security in this project at this
40
--     stage. 
41 159 ja_rd
--     This can be easily fixed but is not very urgent.
42
--------------------------------------------------------------------------------
43 162 ja_rd
-- Copyright (C) 2011 Jose A. Ruiz
44 161 ja_rd
--                                                              
45
-- This source file may be used and distributed without         
46
-- restriction provided that this copyright statement is not    
47
-- removed from the file and that any derivative work contains  
48
-- the original copyright notice and the associated disclaimer. 
49
--                                                              
50
-- This source file is free software; you can redistribute it   
51
-- and/or modify it under the terms of the GNU Lesser General   
52
-- Public License as published by the Free Software Foundation; 
53
-- either version 2.1 of the License, or (at your option) any   
54
-- later version.                                               
55
--                                                              
56
-- This source is distributed in the hope that it will be       
57
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
58
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
59
-- PURPOSE.  See the GNU Lesser General Public License for more 
60
-- details.                                                     
61
--                                                              
62
-- You should have received a copy of the GNU Lesser General    
63
-- Public License along with this source; if not, download it   
64
-- from http://www.opencores.org/lgpl.shtml
65
--------------------------------------------------------------------------------
66 2 ja_rd
 
67
library ieee;
68
use ieee.std_logic_1164.all;
69
use ieee.std_logic_arith.all;
70
use ieee.std_logic_unsigned.all;
71
use work.mips_pkg.all;
72
 
73
entity mips_cpu is
74
    generic(
75 62 ja_rd
        -- Reset vector address minus 4
76
        RESET_VECTOR_M4 : t_word    := RESET_VECTOR_M4;
77
        -- Trap vector address
78
        TRAP_VECTOR : t_word        := TRAP_VECTOR;
79
        -- Type of memory to be used for register bank in xilinx HW
80
        XILINX_REGBANK  : string    := "distributed" -- {distributed|block}
81 2 ja_rd
    );
82
    port(
83
        clk             : in std_logic;
84
        reset           : in std_logic;
85
        interrupt       : in std_logic;
86
 
87 96 ja_rd
        data_addr       : out std_logic_vector(31 downto 0);
88
 
89 2 ja_rd
        data_rd         : in std_logic_vector(31 downto 0);
90
        data_rd_vma     : out std_logic;
91 96 ja_rd
 
92
        byte_we         : out std_logic_vector(3 downto 0);
93
        data_wr         : out std_logic_vector(31 downto 0);
94 2 ja_rd
 
95
        code_rd_addr    : out std_logic_vector(31 downto 2);
96
        code_rd         : in std_logic_vector(31 downto 0);
97
        code_rd_vma     : out std_logic;
98 101 ja_rd
 
99
        cache_enable    : out std_logic;
100
        ic_invalidate   : out std_logic;
101 96 ja_rd
 
102 2 ja_rd
        mem_wait        : in std_logic
103
    );
104
end; --entity mips_cpu
105
 
106
architecture rtl of mips_cpu is
107
 
108
--------------------------------------------------------------------------------
109
-- Pipeline stage 0
110
 
111
signal p0_pc_reg :          t_pc;
112 8 ja_rd
signal p0_pc_restart :      t_pc;
113 2 ja_rd
signal p0_pc_incremented :  t_pc;
114
signal p0_pc_jump :         t_pc;
115
signal p0_pc_branch :       t_pc;
116
signal p0_pc_target :       t_pc;
117
signal p0_pc_next :         t_pc;
118
signal p0_rs_num :          t_regnum;
119
signal p0_rt_num :          t_regnum;
120
signal p0_jump_cond_value : std_logic;
121
signal p0_rbank_rs_hazard : std_logic;
122
signal p0_rbank_rt_hazard : std_logic;
123 28 ja_rd
signal p0_uses_rs1 :        std_logic;
124
signal p0_uses_rs2 :        std_logic;
125 2 ja_rd
 
126 28 ja_rd
signal p1_rs1_hazard :      std_logic;
127
signal p1_rs2_hazard :      std_logic;
128
 
129 2 ja_rd
--------------------------------------------------------------------------------
130
-- Pipeline stage 1
131
 
132
 
133
signal p1_rbank :           t_rbank := (others => X"00000000");
134
 
135
-- IMPORTANT: This attribute is used by Xilinx tools to select how to implement
136
-- the register bank. If we don't use it, by default XST would infer 2 BRAMs for
137
-- the 1024-bit 3-port reg bank, which you probably don't want.
138
-- This can take the values {distributed|block}.
139
attribute ram_style :       string;
140 30 ja_rd
attribute ram_style of p1_rbank : signal is XILINX_REGBANK;
141 2 ja_rd
 
142
signal p1_rs, p1_rt :       t_word;
143
signal p1_rs_rbank :        t_word;
144
signal p1_rt_rbank :        t_word;
145
signal p1_rbank_forward :   t_word;
146
signal p1_rd_num :          t_regnum;
147 28 ja_rd
signal p1_c0_rs_num :       t_regnum;
148 2 ja_rd
signal p1_rbank_wr_addr :   t_regnum;
149
signal p1_rbank_we :        std_logic;
150
signal p1_rbank_wr_data :   t_word;
151
signal p1_alu_inp1 :        t_word;
152
signal p1_alu_inp2 :        t_word;
153
signal p1_alu_outp :        t_word;
154
-- ALU control inputs (shortened name for brevity in expressions)
155
signal p1_ac :              t_alu_control;
156
-- ALU flag outputs (comparison results)
157
signal p1_alu_flags :       t_alu_flags;
158
-- immediate data, sign- or zero-extended as required by IR
159
signal p1_data_imm :        t_word;
160
signal p1_branch_offset :   t_pc;
161
signal p1_branch_offset_sex:std_logic_vector(31 downto 18);
162
signal p1_rbank_rs_hazard : std_logic;
163
signal p1_rbank_rt_hazard : std_logic;
164
signal p1_jump_type_set0 :  std_logic_vector(1 downto 0);
165
signal p1_jump_type_set1 :  std_logic_vector(1 downto 0);
166
signal p1_ir_reg :          std_logic_vector(31 downto 0);
167
signal p1_ir_op :           std_logic_vector(31 downto 26);
168
signal p1_ir_fn :           std_logic_vector(5 downto 0);
169
signal p1_op_special :      std_logic;
170
signal p1_exception :       std_logic;
171
signal p1_do_reg_jump :     std_logic;
172
signal p1_do_zero_ext_imm : std_logic;
173 153 ja_rd
signal p1_set_cp :          std_logic;
174
signal p1_get_cp :          std_logic;
175 2 ja_rd
signal p1_set_cp0 :         std_logic;
176
signal p1_get_cp0 :         std_logic;
177 153 ja_rd
signal p1_rfe :             std_logic;
178 2 ja_rd
signal p1_alu_op2_sel :     std_logic_vector(1 downto 0);
179
signal p1_alu_op2_sel_set0: std_logic_vector(1 downto 0);
180
signal p1_alu_op2_sel_set1: std_logic_vector(1 downto 0);
181
signal p1_do_load :         std_logic;
182
signal p1_do_store :        std_logic;
183
signal p1_store_size :      std_logic_vector(1 downto 0);
184
signal p1_we_control :      std_logic_vector(5 downto 0);
185
signal p1_load_alu :        std_logic;
186
signal p1_load_alu_set0 :   std_logic;
187
signal p1_load_alu_set1 :   std_logic;
188
signal p1_ld_upper_hword :  std_logic;
189
signal p1_ld_upper_byte :   std_logic;
190
signal p1_ld_unsigned :     std_logic;
191
signal p1_jump_type :       std_logic_vector(1 downto 0);
192
signal p1_link :            std_logic;
193
signal p1_jump_cond_sel :   std_logic_vector(2 downto 0);
194
signal p1_data_addr :       t_addr;
195
signal p1_data_offset :     t_addr;
196
 
197 12 ja_rd
signal p1_muldiv_result :   t_word;
198
signal p1_muldiv_func :     t_mult_function;
199
signal p1_muldiv_running :  std_logic;
200
signal p1_muldiv_started :  std_logic;
201
signal p1_muldiv_stall :    std_logic;
202
 
203 23 ja_rd
signal p1_unknown_opcode :  std_logic;
204 153 ja_rd
signal p1_cp_unavailable :  std_logic;
205 12 ja_rd
 
206 2 ja_rd
--------------------------------------------------------------------------------
207
-- Pipeline stage 2
208
 
209 12 ja_rd
signal p2_muldiv_started :  std_logic;
210 2 ja_rd
signal p2_exception :       std_logic;
211
signal p2_rd_addr :         std_logic_vector(1 downto 0);
212
signal p2_rd_mux_control :  std_logic_vector(3 downto 0);
213
signal p2_load_target :     t_regnum;
214
signal p2_do_load :         std_logic;
215 132 ja_rd
signal p2_do_store :        std_logic;
216 2 ja_rd
signal p2_ld_upper_hword :  std_logic;
217
signal p2_ld_upper_byte :   std_logic;
218
signal p2_ld_unsigned :     std_logic;
219
signal p2_wback_mux_sel :   std_logic_vector(1 downto 0);
220
signal p2_data_word_rd :    t_word;
221
signal p2_data_word_ext :   std_logic;
222
 
223
--------------------------------------------------------------------------------
224
-- Global control signals 
225
 
226
signal load_interlock :     std_logic;
227
signal stall_pipeline :     std_logic;
228
-- pipeline is stalled for any reason
229
signal pipeline_stalled :   std_logic;
230 46 ja_rd
 
231
signal stalled_memwait :    std_logic;
232
signal stalled_muldiv :     std_logic;
233 2 ja_rd
-- pipeline is stalled because of a load instruction interlock
234 46 ja_rd
signal stalled_interlock :  std_logic;
235 2 ja_rd
 
236 101 ja_rd
signal reset_done :         std_logic;
237 46 ja_rd
 
238 2 ja_rd
--------------------------------------------------------------------------------
239
-- CP0 registers and signals
240
 
241 153 ja_rd
-- CP0[12]: status register, KUo/IEo & KUP/IEp & KU/IE  bits
242
signal cp0_status :         std_logic_vector(5 downto 0);
243 157 ja_rd
signal cp0_sr_ku_reg :      std_logic;
244 101 ja_rd
-- CP0[12]: status register, cache control
245
signal cp0_cache_control :  std_logic_vector(17 downto 16);
246 2 ja_rd
-- Output of CP0 register bank (only a few regs are implemented)
247
signal cp0_reg_read :       t_word;
248
-- CP0[14]: EPC register (PC value saved at exceptions)
249
signal cp0_epc :            t_pc;
250 28 ja_rd
-- CP0[13]: 'Cause' register (cause and attributes of exception)
251
signal cp0_cause :          t_word;
252
signal cp0_in_delay_slot :  std_logic;
253
signal cp0_cause_bd :       std_logic;
254
signal cp0_cause_ce :       std_logic_vector(1 downto 0);
255
signal cp0_cause_exc_code : std_logic_vector(4 downto 0);
256 2 ja_rd
 
257
begin
258
 
259
--##############################################################################
260
-- Register bank & datapath
261
 
262
-- Register indices are 'decoded' out of the instruction word BEFORE loading IR
263
p0_rs_num <= std_logic_vector(code_rd(25 downto 21));
264
with p1_ir_reg(31 downto 26) select p1_rd_num <=
265
    p1_ir_reg(15 downto 11)    when "000000",
266
    p1_ir_reg(20 downto 16)    when others;
267
 
268
p0_rt_num <= std_logic_vector(code_rd(20 downto 16)); -- also called rs2 in the docs
269
 
270
--------------------------------------------------------------------------------
271
-- Data input shifter & masker (LB,LBU,LH,LHU,LW)
272
 
273
p2_rd_mux_control <= p2_ld_upper_hword & p2_ld_upper_byte & p2_rd_addr;
274
 
275
-- Extension for unused bits will be zero or the sign (bit 7 or bit 15)
276 35 ja_rd
p2_data_word_ext <= '0'          when p2_ld_unsigned='1' else
277 83 ja_rd
                    -- LH
278
                    data_rd(31)  when p2_ld_upper_byte='1' and p2_rd_addr="00" else
279
                    data_rd(15)  when p2_ld_upper_byte='1' and p2_rd_addr="10" else
280
                    -- LB
281
                    data_rd(7)  when p2_rd_addr="11" else
282 2 ja_rd
                    data_rd(15)  when p2_rd_addr="10" else
283 83 ja_rd
                    data_rd(23)  when p2_rd_addr="01" else
284
                    data_rd(31);
285 2 ja_rd
 
286
-- byte 0 may come from any of the 4 bytes of the input word
287
with p2_rd_mux_control select p2_data_word_rd(7 downto 0) <=
288
    data_rd(31 downto 24)        when "0000",
289
    data_rd(23 downto 16)        when "0001",
290
    data_rd(23 downto 16)        when "0100",
291
    data_rd(15 downto  8)        when "0010",
292
    data_rd( 7 downto  0)        when others;
293
 
294
-- byte 1 may come from input bytes 1 or 3 or may be extended for LB, LBU
295
with p2_rd_mux_control select p2_data_word_rd(15 downto 8) <=
296
    data_rd(31 downto 24)        when "0100",
297
    data_rd(15 downto  8)        when "0110",
298
    data_rd(15 downto  8)        when "1100",
299
    data_rd(15 downto  8)        when "1101",
300
    data_rd(15 downto  8)        when "1110",
301
    data_rd(15 downto  8)        when "1111",
302
    (others => p2_data_word_ext) when others;
303
 
304
-- bytes 2,3 come straight from input or are extended for LH,LHU
305
with p2_ld_upper_hword select p2_data_word_rd(31 downto 16) <=
306 46 ja_rd
    (others => p2_data_word_ext) when '0',
307
    data_rd(31 downto 16)        when others;
308 2 ja_rd
 
309 121 ja_rd
--------------------------------------------------------------------------------
310
-- Reg bank input multiplexor
311
 
312 2 ja_rd
-- Select which data is to be written back to the reg bank and where
313
p1_rbank_wr_addr <= p1_rd_num   when p2_do_load='0' and p1_link='0' else
314
                    "11111"     when p2_do_load='0' and p1_link='1' else
315
                    p2_load_target;
316
 
317
p2_wback_mux_sel <=
318
    "00" when p2_do_load='0' and p1_get_cp0='0' and p1_link='0' else
319
    "01" when p2_do_load='1' and p1_get_cp0='0' and p1_link='0' else
320
    "10" when p2_do_load='0' and p1_get_cp0='1' and p1_link='0' else
321
    "11";
322
 
323
with (p2_wback_mux_sel) select p1_rbank_wr_data <=
324
    p1_alu_outp                when "00",
325
    p2_data_word_rd            when "01",
326
    p0_pc_incremented & "00"   when "11",
327
    cp0_reg_read               when others;
328
 
329 121 ja_rd
--------------------------------------------------------------------------------
330
-- Register bank RAM & Rbank WE logic
331
 
332 171 ja_rd
p1_rbank_we <= '1' when (p2_do_load='1' or p1_load_alu='1' or p1_link='1' or
333
                        -- if mfc0 triggers privilege trap, don't load reg
334
                        (p1_get_cp0='1' and p1_cp_unavailable='0')) and
335 35 ja_rd
                        -- If target register is $zero, ignore write
336 2 ja_rd
                        p1_rbank_wr_addr/="00000" and
337 35 ja_rd
                        -- if the cache controller keeps the cpu stopped, do
338
                        -- not writeback
339
                        mem_wait='0' and
340 46 ja_rd
                        -- if stalled because of muldiv, block writeback
341
                        stalled_muldiv='0' and --@note1
342 2 ja_rd
                        -- on exception, abort next instruction (by preventing 
343
                        -- regbank writeback).
344
                        p2_exception='0'
345
                else '0';
346
 
347
-- Register bank as triple-port RAM. Should synth to 2 BRAMs unless you use
348
-- synth attributes to prevent it (see 'ram_style' attribute above) or your
349
-- FPGA has 3-port BRAMS, or has none.
350
synchronous_reg_bank:
351
process(clk)
352
begin
353
    if clk'event and clk='1' then
354 46 ja_rd
        if p1_rbank_we='1' then
355 2 ja_rd
            p1_rbank(conv_integer(p1_rbank_wr_addr)) <= p1_rbank_wr_data;
356
        end if;
357 46 ja_rd
        -- the rbank read port loads in the same conditions as the IR: don't
358
        -- update Rs or Rt if the pipeline is frozen
359
        if stall_pipeline='0' then
360
            p1_rt_rbank <= p1_rbank(conv_integer(p0_rt_num));
361
            p1_rs_rbank <= p1_rbank(conv_integer(p0_rs_num));
362
        end if;
363 2 ja_rd
    end if;
364
end process synchronous_reg_bank;
365
 
366 121 ja_rd
--------------------------------------------------------------------------------
367
-- Reg bank 'writeback' data forwarding
368
 
369
-- Register writeback data in a DFF in case it needs to be forwarded.
370 2 ja_rd
data_forward_register:
371
process(clk)
372
begin
373
    if clk'event and clk='1' then
374
        if p1_rbank_we='1' then -- no need to check for stall cycles
375
            p1_rbank_forward <= p1_rbank_wr_data;
376
        end if;
377
    end if;
378
end process data_forward_register;
379
 
380
-- Bypass sync RAM if we're reading and writing to the same address. This saves
381
-- 1 stall cycle and fixes the data hazard.
382
p0_rbank_rs_hazard <= '1' when p1_rbank_wr_addr=p0_rs_num and p1_rbank_we='1'
383
                      else '0';
384
p0_rbank_rt_hazard <= '1' when p1_rbank_wr_addr=p0_rt_num and p1_rbank_we='1'
385
                      else '0';
386
 
387
p1_rs <= p1_rs_rbank when p1_rbank_rs_hazard='0' else p1_rbank_forward;
388
p1_rt <= p1_rt_rbank when p1_rbank_rt_hazard='0' else p1_rbank_forward;
389
 
390
 
391
--------------------------------------------------------------------------------
392
-- ALU & ALU input multiplexors
393
 
394
p1_alu_inp1 <= p1_rs;
395
 
396
with p1_alu_op2_sel select p1_alu_inp2 <=
397 12 ja_rd
    p1_data_imm         when "11",
398 23 ja_rd
    p1_muldiv_result    when "01",
399
    --p1_muldiv_result    when "10", -- FIXME mux input wasted!
400 12 ja_rd
    p1_rt               when others;
401 2 ja_rd
 
402
alu_inst : entity work.mips_alu
403
    port map (
404
        clk             => clk,
405
        reset           => reset,
406
        ac              => p1_ac,
407
        flags           => p1_alu_flags,
408
 
409
        inp1            => p1_alu_inp1,
410
        inp2            => p1_alu_inp2,
411
        outp            => p1_alu_outp
412
    );
413
 
414
 
415
--------------------------------------------------------------------------------
416
-- Mul/Div block interface
417
 
418 12 ja_rd
-- Compute the mdiv block function word. If p1_muldiv_func has any value other
419
-- than MULT_NOTHING a new mdiv operation will start, truncating whatever other
420
-- operation that may have been in course.
421
-- So we encode here the function to be performed and make sure the value stays
422
-- there for only one cycle (the first ALU cycle of the mul/div instruction).
423 2 ja_rd
 
424 12 ja_rd
-- This will be '1' for all mul/div operations other than NOP...
425
p1_muldiv_func(3) <= '1' when p1_op_special='1' and
426
                              p1_ir_fn(5 downto 4)="01" and
427
                              -- ...but only if the mdiv is not already running
428
                              p2_muldiv_started = '0' and
429
                              p1_muldiv_running ='0'
430
                      else '0';
431 2 ja_rd
 
432 12 ja_rd
-- When bit(3) is zero, the rest are zeroed too. Otherwise, they come from IR
433
p1_muldiv_func(2 downto 0) <=
434
    p1_ir_fn(3) & p1_ir_fn(1 downto 0) when p1_muldiv_func(3)='1'
435
    else "000";
436 2 ja_rd
 
437 12 ja_rd
mult_div: entity work.mips_mult
438
    port map (
439
        a           => p1_rs,
440
        b           => p1_rt,
441
        c_mult      => p1_muldiv_result,
442
        pause_out   => p1_muldiv_running,
443
        mult_func   => p1_muldiv_func,
444
        clk         => clk,
445
        reset_in    => reset
446
    );
447
 
448
-- Active only for the 1st ALU cycle of any mul/div instruction
449
p1_muldiv_started <= '1' when p1_op_special='1' and
450
                              p1_ir_fn(5 downto 3)="011" and
451
                              -- 
452
                              p1_muldiv_running='0'
453
                      else '0';
454
 
455
-- Stall the pipeline to enable mdiv operation completion.
456
-- We need p2_muldiv_started to distinguish the cycle before p1_muldiv_running
457
-- is asserted and the cycle after it deasserts.
458
-- Otherwise we would reexecute the same muldiv endlessly instruction after 
459
-- deassertion of p1_muldiv_running, since the IR was stalled and still contains 
460
-- the mul opcode...
461
p1_muldiv_stall <= '1' when
462
        -- Active for the cycle immediately before p1_muldiv_running asserts
463
        -- and NOT for the cycle after it deasserts
464
        (p1_muldiv_started='1' and p2_muldiv_started='0') or
465
        -- Active until operation is complete
466
        p1_muldiv_running = '1'
467
        else '0';
468
 
469
 
470 2 ja_rd
--##############################################################################
471
-- PC register and branch logic
472
 
473
-- p0_pc_reg will not be incremented on stall cycles
474
p0_pc_incremented <= p0_pc_reg + (not stall_pipeline);
475
 
476
-- main pc mux: jump or continue
477
p0_pc_next <=
478
    p0_pc_target when
479
        -- We jump on jump instructions whose condition is met...
480 6 ja_rd
        ((p1_jump_type(1)='1' and p0_jump_cond_value='1' and
481
        -- ...except we abort any jump that follows the victim of an exception
482
          p2_exception='0') or
483
        -- We jump on exceptions too...
484 2 ja_rd
        p1_exception='1')
485 6 ja_rd
        -- ... but we only jump at all if the pipeline is not stalled
486 2 ja_rd
        and stall_pipeline='0'
487
    else p0_pc_incremented;
488
 
489
pc_register:
490
process(clk)
491
begin
492
    if clk'event and clk='1' then
493
        if reset='1' then
494 62 ja_rd
            -- reset to <vector>-4 so that 1st fetch addr is <vector>
495
            p0_pc_reg <= RESET_VECTOR_M4(31 downto 2);
496 2 ja_rd
        else
497 101 ja_rd
            if reset_done='1' then
498 2 ja_rd
            -- p0_pc_reg holds the same value as external sync ram addr register
499
            p0_pc_reg <= p0_pc_next;
500 8 ja_rd
            -- p0_pc_restart = addr saved to EPC on interrupts (@note2)
501 28 ja_rd
            -- It's the addr of the instruction triggering the exception,
502
            -- except when the triggering instruction is in a delay slot. In 
503
            -- that case, this is the previous jump instruction address.
504
            -- I.e. all as per the mips-1 specs.
505 8 ja_rd
            if (p1_jump_type="00" or p0_jump_cond_value='0') then
506
                p0_pc_restart <= p0_pc_reg;
507 28 ja_rd
                -- remember if we are in a delay slot, in case there's a trap
508
                cp0_in_delay_slot <= '0'; -- NOT in a delay slot
509
            else
510
                cp0_in_delay_slot <= '1'; -- in a delay slot
511 8 ja_rd
            end if;
512 101 ja_rd
            end if;
513 2 ja_rd
        end if;
514
    end if;
515
end process pc_register;
516
 
517 96 ja_rd
-- Common rd/wr address; lowest 2 bits are output as debugging aid only
518
data_addr <= p1_data_addr(31 downto 0);
519 2 ja_rd
 
520 121 ja_rd
-- 'Memory enable' signals for both memory interfaces
521
data_rd_vma <= p1_do_load and not pipeline_stalled;
522
code_rd_vma <= (not stall_pipeline) and reset_done;
523 2 ja_rd
 
524 101 ja_rd
-- reset_done will be asserted after the reset process is finished, when the
525
-- CPU can start operating normally.
526
-- We only use it to make sure code_rd_vma is not asserted prematurely.
527
wait_for_end_of_reset:
528
process(clk)
529
begin
530
    if clk'event and clk='1' then
531
        if reset='1' then
532
            reset_done <= '0';
533
        else
534
            reset_done <= '1';
535
        end if;
536
    end if;
537
end process wait_for_end_of_reset;
538
 
539 121 ja_rd
-- The final value used to access code memory
540 2 ja_rd
code_rd_addr <= p0_pc_next;
541
 
542
-- compute target of J/JR instructions
543
p0_pc_jump <=   p1_rs(31 downto 2) when p1_do_reg_jump='1' else
544
                p0_pc_reg(31 downto 28) & p1_ir_reg(25 downto 0);
545
 
546
-- compute target of relative branch instructions
547
p1_branch_offset_sex <= (others => p1_ir_reg(15));
548
p1_branch_offset <= p1_branch_offset_sex & p1_ir_reg(15 downto 0);
549
-- p0_pc_reg is the addr of the instruction in delay slot
550
p0_pc_branch <= p0_pc_reg + p1_branch_offset;
551
 
552
-- decide which jump target is to be used
553 62 ja_rd
p0_pc_target <=
554
    TRAP_VECTOR(31 downto 2)    when p1_exception='1' else
555
    p0_pc_jump                  when p1_jump_type(0)='1' else
556
    p0_pc_branch;
557 2 ja_rd
 
558
 
559
--##############################################################################
560
-- Instruction decoding and IR
561
 
562
instruction_register:
563
process(clk)
564
begin
565
    if clk'event and clk='1' then
566
        if reset='1' then
567
            p1_ir_reg <= (others => '0');
568
        elsif stall_pipeline='0' then
569
            p1_ir_reg <= code_rd;
570
        end if;
571
    end if;
572
end process instruction_register;
573
 
574 121 ja_rd
-- Zero extension/Sign extension of instruction immediate data
575
p1_data_imm(15 downto 0)  <= p1_ir_reg(15 downto 0);
576
 
577
with p1_do_zero_ext_imm select p1_data_imm(31 downto 16) <=
578
    (others => '0')             when '1',
579
    (others => p1_ir_reg(15))   when others;
580
 
581
 
582 2 ja_rd
-- 'Extract' main fields from IR, for convenience
583
p1_ir_op <= p1_ir_reg(31 downto 26);
584
p1_ir_fn <= p1_ir_reg(5 downto 0);
585
 
586
-- Decode jump type, if any, for instructions with op/=0
587
with p1_ir_op select p1_jump_type_set0 <=
588 121 ja_rd
    -- FIXME verify that we actually weed out ALL invalid instructions
589 2 ja_rd
    "10" when "000001", -- BLTZ, BGEZ, BLTZAL, BGTZAL
590
    "11" when "000010", -- J
591
    "11" when "000011", -- JAL
592
    "10" when "000100", -- BEQ
593
    "10" when "000101", -- BNE
594
    "10" when "000110", -- BLEZ
595
    "10" when "000111", -- BGTZ
596
    "00" when others;   -- no jump
597
 
598
-- Decode jump type, if any, for instructions with op=0
599
p1_jump_type_set1 <= "11" when p1_op_special='1' and
600
                               p1_ir_reg(5 downto 1)="00100"
601
                     else "00";
602
 
603
-- Decode jump type for the instruction in IR (composite of two formats)
604
p1_jump_type <= p1_jump_type_set0 or p1_jump_type_set1;
605
 
606
p1_link <= '1' when (p1_ir_op="000000" and p1_ir_reg(5 downto 0)="001001") or
607
                    (p1_ir_op="000001" and p1_ir_reg(20)='1') or
608
                    (p1_ir_op="000011")
609
           else '0';
610
 
611
-- Decode jump condition: encode a mux control signal from IR...
612
p1_jump_cond_sel <=
613
    "001" when p1_ir_op="000001" and p1_ir_reg(16)='0' else --   op1 < 0   BLTZ*
614
    "101" when p1_ir_op="000001" and p1_ir_reg(16)='1' else -- !(op1 < 0) BNLTZ*
615
    "010" when p1_ir_op="000100" else                       --   op1 == op2  BEQ
616
    "110" when p1_ir_op="000101" else                       -- !(op1 == op2) BNE
617
    "011" when p1_ir_op="000110" else                       --   op1 <= 0   BLEZ
618
    "111" when p1_ir_op="000111" else                       -- !(op1 <= 0)  BGTZ
619
    "000";                                                  -- always
620
 
621
-- ... and use mux control signal to select the condition value
622
with p1_jump_cond_sel select p0_jump_cond_value <=
623
        p1_alu_flags.inp1_lt_zero       when "001",
624
    not p1_alu_flags.inp1_lt_zero       when "101",
625
        p1_alu_flags.inp1_eq_inp2       when "010",
626
    not p1_alu_flags.inp1_eq_inp2       when "110",
627
        (p1_alu_flags.inp1_lt_inp2 or
628
         p1_alu_flags.inp1_eq_inp2)     when "011",
629
    not (p1_alu_flags.inp1_lt_inp2 or
630
         p1_alu_flags.inp1_eq_inp2)     when "111",
631
    '1'                                 when others;
632
 
633
-- Decode instructions that launch exceptions
634 23 ja_rd
p1_exception <= '1' when
635 153 ja_rd
    (p1_op_special='1' and p1_ir_reg(5 downto 1)="00110") or -- syscall/break
636
    p1_unknown_opcode='1' or
637
    p1_cp_unavailable='1'
638 23 ja_rd
    else '0';
639 2 ja_rd
 
640 153 ja_rd
-- Decode MTC0/MFC0 instructions (see @note3)
641
p1_set_cp  <= '1' when p1_ir_reg(31 downto 28)="0100" and
642
                       p1_ir_reg(25 downto 21)="00100" else '0';
643
p1_get_cp  <= '1' when p1_ir_reg(31 downto 28)="0100" and
644
                       p1_ir_reg(25 downto 21)="00000" else '0';
645 2 ja_rd
 
646 153 ja_rd
p1_set_cp0 <= '1' when p1_ir_reg(27 downto 26)="00" and p1_set_cp='1' else '0';
647
p1_get_cp0 <= '1' when p1_ir_reg(27 downto 26)="00" and p1_get_cp='1' else '0';
648
 
649
-- Decode RFE instruction (see @note3)
650
p1_rfe <= '1' when p1_ir_reg(31 downto 21)="01000010000" and
651
                   p1_ir_reg(5 downto 0)="010000"
652
          else '0';
653
 
654 121 ja_rd
-- Raise some signals for some particular group of opcodes
655
p1_op_special <= '1' when p1_ir_op="000000" else '0'; -- group '0' opcodes
656 2 ja_rd
p1_do_reg_jump <= '1' when p1_op_special='1' and p1_ir_fn(5 downto 1)="00100" else '0';
657
p1_do_zero_ext_imm <= '1' when (p1_ir_op(31 downto 28)="0011") else '0';
658
 
659
-- Decode input data mux control (LW, LH, LB, LBU, LHU) and load enable
660 30 ja_rd
p1_do_load <= '1' when
661
    p1_ir_op(31 downto 29)="100" and
662
    p1_ir_op(28 downto 26)/="010" and -- LWL
663
    p1_ir_op(28 downto 26)/="110" and -- LWR
664
    p1_ir_op(28 downto 26)/="111" and -- LWR
665
    p2_exception='0'  -- abort load if previous instruction triggered trap
666
    else '0';
667 2 ja_rd
 
668
p1_load_alu_set0 <= '1'
669
    when p1_op_special='1' and
670
        ((p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
671
         (p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="10") or
672
         (p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="11") or
673
         (p1_ir_op(31 downto 29)="000" and p1_ir_op(27 downto 26)="00") or
674
         (p1_ir_op(31 downto 28)="0100" and p1_ir_op(27 downto 26)="00") or
675
         (p1_ir_op(31 downto 28)="0100" and p1_ir_op(27 downto 26)="10") or
676
         (p1_ir_op(31 downto 28)="1000") or
677
         (p1_ir_op(31 downto 28)="1001") or
678
         (p1_ir_op(31 downto 28)="1010" and p1_ir_op(27 downto 26)="10") or
679
         (p1_ir_op(31 downto 28)="1010" and p1_ir_op(27 downto 26)="11") or
680
         (p1_ir_op(31 downto 28)="0010" and p1_ir_op(27 downto 26)="01"))
681
    else '0';
682
 
683
with p1_ir_op select p1_load_alu_set1 <=
684 28 ja_rd
    '1' when "001000",  -- addi
685
    '1' when "001001",  -- addiu
686
    '1' when "001010",  -- slti
687
    '1' when "001011",  -- sltiu
688
    '1' when "001100",  -- andi
689
    '1' when "001101",  -- ori
690
    '1' when "001110",  -- xori
691
    '1' when "001111",  -- lui
692 2 ja_rd
    '0' when others;
693 28 ja_rd
p1_load_alu <= (p1_load_alu_set0 or p1_load_alu_set1) and
694
                not p1_unknown_opcode;
695 2 ja_rd
 
696
p1_ld_upper_hword <= p1_ir_op(27); -- use input upper hword vs. sign extend/zero
697
p1_ld_upper_byte <= p1_ir_op(26);  -- use input upper byte vs. sign extend/zero
698
p1_ld_unsigned <= p1_ir_op(28);    -- sign extend vs. zero extend
699
 
700
-- ALU input-2 selection: use external data for 2x opcodes (loads)
701
p1_alu_op2_sel_set0 <=
702
    "11" when    p1_ir_op(31 downto 30)="10" or p1_ir_op(29)='1' else
703
    "00";
704
 
705
-- ALU input-2 selection: use registers Hi and Lo for MFHI, MFLO
706 22 ja_rd
p1_alu_op2_sel_set1 <=
707
    "01" when p1_op_special='1' and (p1_ir_fn="010000" or p1_ir_fn="010010")
708
    else "00";
709 2 ja_rd
 
710
-- ALU input-2 final selection
711
p1_alu_op2_sel <= p1_alu_op2_sel_set0 or p1_alu_op2_sel_set1;
712
 
713
-- Decode store operations
714 30 ja_rd
p1_do_store <= '1' when
715
    p1_ir_op(31 downto 29)="101" and
716
    (p1_ir_op(28 downto 26)="000" or -- SB
717
     p1_ir_op(28 downto 26)="001" or -- SH
718
     p1_ir_op(28 downto 26)="011") and -- SWH
719 28 ja_rd
    p2_exception='0'    -- abort when previous instruction triggered exception
720
    else '0';
721 2 ja_rd
p1_store_size <= p1_ir_op(27 downto 26);
722
 
723
 
724 28 ja_rd
-- Extract source and destination C0 register indices
725
p1_c0_rs_num <= p1_ir_reg(15 downto 11);
726 2 ja_rd
 
727 121 ja_rd
-- Decode ALU control signals
728 2 ja_rd
 
729
p1_ac.use_slt <= '1' when (p1_ir_op="000001" and p1_ir_reg(20 downto 17)="01000") or
730
                        (p1_ir_op="000000" and p1_ir_reg(5 downto 1)="10101") or
731
                        p1_ir_op="001010" or p1_ir_op="001011"
732
               else '0';
733 83 ja_rd
p1_ac.arith_unsigned <= p1_ac.use_slt and (p1_ir_reg(0) or p1_ir_op(26));
734 2 ja_rd
 
735
p1_ac.use_logic(0) <= '1' when (p1_op_special='1' and p1_ir_fn(5 downto 3)/="000") or
736
                    -- all immediate arith and logic
737
                    p1_ir_op(31 downto 29)="001"
738
                 else '0';
739
p1_ac.use_logic(1) <= '1' when (p1_op_special='1' and p1_ir_fn="100111") else '0';
740
 
741
p1_ac.use_arith <= '1' when p1_ir_op(31 downto 28)="0010" or
742
                            (p1_op_special='1' and
743
                                (p1_ir_fn(5 downto 2)="1000" or
744
                                p1_ir_fn(5 downto 2)="1010"))
745
                 else '0';
746
 
747
-- selection of 2nd internal alu operand: {i2, /i2, i2<<16, 0x0}
748
p1_ac.neg_sel(1)<= '1' when p1_ir_op(29 downto 26) = "1111" else '0';
749
p1_ac.neg_sel(0)<= '1' when   p1_ir_op="001010" or
750
                            p1_ir_op="001011" or
751
                            p1_ir_op(31 downto 28)="0001" or
752
                            (p1_op_special='1' and
753
                                (p1_ir_fn="100010" or
754
                                 p1_ir_fn="100011" or
755
                                 p1_ir_fn(5 downto 2)="1010"))
756
                 else '0';
757
p1_ac.cy_in <= p1_ac.neg_sel(0);
758
 
759
p1_ac.shift_sel <= p1_ir_fn(1 downto 0);
760
 
761
p1_ac.logic_sel <= "00" when (p1_op_special='1' and p1_ir_fn="100100") else
762
                 "01" when (p1_op_special='1' and p1_ir_fn="100101") else
763
                 "10" when (p1_op_special='1' and p1_ir_fn="100110") else
764
                 "01" when (p1_op_special='1' and p1_ir_fn="100111") else
765
                 "00" when (p1_ir_op="001100") else
766
                 "01" when (p1_ir_op="001101") else
767
                 "10" when (p1_ir_op="001110") else
768
                 "11";
769
 
770
p1_ac.shift_amount <= p1_ir_reg(10 downto 6) when p1_ir_fn(2)='0' else p1_rs(4 downto 0);
771
 
772 23 ja_rd
 
773 2 ja_rd
--------------------------------------------------------------------------------
774 23 ja_rd
-- Decoding of unimplemented and privileged instructions
775 2 ja_rd
 
776 23 ja_rd
-- Unimplemented instructions include:
777
--  1.- All instructions above architecture MIPS-I except:
778
--      1.1.- eret
779
--  2.- Unaligned stores and loads (LWL,LWR,SWL,SWR)
780
--  3.- All CP0 instructions other than mfc0 and mtc0
781
--  4.- All CPi instructions
782
--  5.- All cache instructions
783
-- For the time being, we'll decode them all together.
784
 
785
-- FIXME: some of these should trap but others should just NOP (e.g. EHB)
786
 
787
p1_unknown_opcode <= '1' when
788
    -- decode by 'opcode' field
789
    p1_ir_op(31 downto 29)="011" or
790
    p1_ir_op(31 downto 29)="110" or
791
    p1_ir_op(31 downto 29)="111" or
792
    (p1_ir_op(31 downto 29)="010" and p1_ir_op(28 downto 26)/="000") or
793
    p1_ir_op="101111" or    -- CACHE
794
    p1_ir_op="100010" or    -- LWL
795
    p1_ir_op="100110" or    -- LWR
796
    p1_ir_op="101010" or    -- SWL
797
    p1_ir_op="101110" or    -- SWR
798
    p1_ir_op="100111" or
799
    p1_ir_op="101100" or
800
    p1_ir_op="101101" or
801
    -- decode instructions in the 'special' opcode group
802
    (p1_ir_op="000000" and
803
                (p1_ir_fn(5 downto 4)="11" or
804
                 p1_ir_fn="000001" or
805
                 p1_ir_fn="000101" or
806
                 p1_ir_fn="001010" or
807
                 p1_ir_fn="001011" or
808
                 p1_ir_fn="001110" or
809
                 p1_ir_fn(5 downto 2)="0101" or
810
                 p1_ir_fn(5 downto 2)="0111" or
811
                 p1_ir_fn(5 downto 2)="1011")) or
812
    -- decode instructions in the 'regimm' opcode group
813
    (p1_ir_op="000001" and
814
                (p1_ir_reg(20 downto 16)/="00000" and -- BLTZ is valid
815
                 p1_ir_reg(20 downto 16)/="00001" and -- BGEZ is valid
816
                 p1_ir_reg(20 downto 16)/="10000" and -- BLTZAL is valid 
817
                 p1_ir_reg(20 downto 16)/="10001")) -- BGEZAL is valid
818
 
819
    else '0';
820
 
821 153 ja_rd
p1_cp_unavailable <= '1' when
822
    (p1_set_cp='1' and p1_set_cp0='0') or   -- mtc1..3
823
    (p1_get_cp='1' and p1_get_cp0='0') or   -- mfc1..3
824
    ((p1_get_cp0='1' or p1_set_cp0='1' or p1_rfe='1')
825 157 ja_rd
                     and cp0_sr_ku_reg='0')
826
                     --and cp0_status(1)='0') -- COP0 user mode
827
    -- FIXME CP1..3 logic missing
828 153 ja_rd
    else '0';
829
 
830 121 ja_rd
--##############################################################################
831
-- Pipeline registers & pipeline control logic
832 23 ja_rd
 
833 2 ja_rd
-- Stage 1 pipeline register. Involved in ALU control.
834
pipeline_stage1_register:
835
process(clk)
836
begin
837
    if clk'event and clk='1' then
838
        if reset='1' then
839
            p1_rbank_rs_hazard <= '0';
840
            p1_rbank_rt_hazard <= '0';
841
        elsif stall_pipeline='0' then
842
            p1_rbank_rs_hazard <= p0_rbank_rs_hazard;
843
            p1_rbank_rt_hazard <= p0_rbank_rt_hazard;
844
        end if;
845
    end if;
846
end process pipeline_stage1_register;
847
 
848 12 ja_rd
pipeline_stage1_register2:
849
process(clk)
850
begin
851
    if clk'event and clk='1' then
852
        if reset='1' then
853
            p2_muldiv_started <= '0';
854
        else
855
            p2_muldiv_started <= p1_muldiv_running;
856
        end if;
857
    end if;
858
end process pipeline_stage1_register2;
859 6 ja_rd
 
860 12 ja_rd
 
861 6 ja_rd
-- Stage 2 pipeline register. Split in two for convenience.
862 2 ja_rd
-- This register deals with two kinds of stalls:
863
-- * When the pipeline stalls because of a load interlock, this register is 
864
--   allowed to update so that the load operation can complete while the rest of
865
--   the pipeline is frozen.
866
-- * When the stall is caused by any other reason, this register freezes with 
867
--   the rest of the machine.
868 6 ja_rd
 
869
-- Part of stage 2 register that controls load operation
870
pipeline_stage2_register_load_control:
871 2 ja_rd
process(clk)
872
begin
873
    if clk'event and clk='1' then
874 6 ja_rd
        -- Clear load control, effectively preventing load, at reset or if
875
        -- the previous instruction raised an exception.
876
        if reset='1' or p2_exception='1' then
877 132 ja_rd
            p2_do_store <= '0';
878 2 ja_rd
            p2_do_load <= '0';
879
            p2_ld_upper_hword <= '0';
880
            p2_ld_upper_byte <= '0';
881
            p2_ld_unsigned <= '0';
882
            p2_load_target <= "00000";
883 6 ja_rd
 
884
        -- Load signals from previous stage only if there is no pipeline stall
885
        -- unless the stall is caused by interlock (@note1).
886
        elsif (stall_pipeline='0' or load_interlock='1') then
887
            -- Disable reg bank writeback if pipeline is stalled; this prevents
888
            -- duplicate writes in case the stall is a mem_wait.
889 2 ja_rd
            if pipeline_stalled='0' then
890
                p2_do_load <= p1_do_load;
891
            else
892
                p2_do_load <= '0';
893
            end if;
894 132 ja_rd
            p2_do_store <= p1_do_store;
895 2 ja_rd
            p2_load_target <= p1_rd_num;
896
            p2_ld_upper_hword <= p1_ld_upper_hword;
897
            p2_ld_upper_byte <= p1_ld_upper_byte;
898
            p2_ld_unsigned <= p1_ld_unsigned;
899 6 ja_rd
        end if;
900
    end if;
901
end process pipeline_stage2_register_load_control;
902
 
903
-- All the rest of the stage 2 register
904
pipeline_stage2_register_others:
905
process(clk)
906
begin
907
    if clk'event and clk='1' then
908
        if reset='1' then
909
            p2_exception <= '0';
910
 
911
        -- Load signals from previous stage only if there is no pipeline stall
912
        -- unless the stall is caused by interlock (@note1).
913
        elsif (stall_pipeline='0' or load_interlock='1') then
914 2 ja_rd
            p2_rd_addr <= p1_data_addr(1 downto 0);
915 6 ja_rd
            p2_exception <= p1_exception;
916 2 ja_rd
        end if;
917
    end if;
918 6 ja_rd
end process pipeline_stage2_register_others;
919 2 ja_rd
 
920
--------------------------------------------------------------------------------
921 121 ja_rd
-- Pipeline control logic (stall control)
922 2 ja_rd
 
923 121 ja_rd
-- FIXME demonstrate that this combinational will not have bad glitches
924 46 ja_rd
stall_pipeline <= mem_wait or load_interlock or p1_muldiv_stall;
925
 
926
-- FIXME load interlock should happen only if the instruction following 
927
-- the load actually uses the load target register. Something like this:
928
-- (p1_do_load='1' and (p1_rd_num=p0_rs_num or p1_rd_num=p0_rt_num))
929
load_interlock <= '1' when
930
    p1_do_load='1' and      -- this is a load instruction
931
    pipeline_stalled='0' and -- not already stalled (i.e. assert for 1 cycle)
932
    (p1_rs1_hazard='1' or p1_rs2_hazard='1')
933
    else '0';
934
 
935
 
936
pipeline_stalled <= stalled_interlock or stalled_memwait or stalled_muldiv;
937
 
938 2 ja_rd
pipeline_stall_registers:
939
process(clk)
940
begin
941
    if clk'event and clk='1' then
942
        if reset='1' then
943 46 ja_rd
            stalled_interlock <= '0';
944
            stalled_memwait <= '0';
945
            stalled_muldiv <= '0';
946 2 ja_rd
        else
947 46 ja_rd
            if mem_wait='1' then
948
                stalled_memwait <= '1';
949 2 ja_rd
            else
950 46 ja_rd
                stalled_memwait <= '0';
951 2 ja_rd
            end if;
952 35 ja_rd
 
953 46 ja_rd
            if p1_muldiv_stall='1' then
954
                stalled_muldiv <= '1';
955
            else
956
                stalled_muldiv <= '0';
957
            end if;
958
 
959 35 ja_rd
            -- stalls caused by mem_wait and load_interlock are independent and
960
            -- must not overlap; so when mem_wait='1' the cache stall takes
961
            -- precedence and the loa interlock must wait.
962
            if mem_wait='0' then
963
                if load_interlock='1' then
964 46 ja_rd
                    stalled_interlock <= '1';
965 35 ja_rd
                else
966 46 ja_rd
                    stalled_interlock <= '0';
967 35 ja_rd
                end if;
968 2 ja_rd
            end if;
969
        end if;
970
    end if;
971
end process pipeline_stall_registers;
972
 
973 121 ja_rd
-- Here's where we stall the pipeline upon load reg bank hazards
974
-- FIXME (@note2) for the time being we stall the pipeline for ALL loads
975 28 ja_rd
p1_rs1_hazard <= '1'; --'1' when p0_uses_rs1='1' and p1_rd_num=p0_rs_num else '0';
976
p1_rs2_hazard <= '1'; --'1' when p0_uses_rs2='1' and p1_rd_num=p0_rt_num else '0';
977
 
978
with p1_ir_op select p0_uses_rs1 <=
979
    '0' when "000010",
980
    '0' when "000011",
981
    '0' when "001111",
982
    '0' when "001000",
983
    '1' when others;
984
 
985
with p1_ir_op select p0_uses_rs2 <=
986
    '1' when "000000",
987
    '1' when "000100",
988
    '1' when "000101",
989
    '1' when "000110",
990
    '1' when "000111",
991
    '1' when "010000",
992
    '1' when "101000",
993
    '1' when "101001",
994
    '1' when "101010",
995
    '1' when "101011",
996
    '1' when "101110",
997
    '0' when others;
998
 
999
 
1000 121 ja_rd
--##############################################################################
1001
-- Data memory interface
1002
 
1003 2 ja_rd
--------------------------------------------------------------------------------
1004 121 ja_rd
-- Memory addressing adder (data address generation)
1005 2 ja_rd
 
1006
p1_data_offset(31 downto 16) <= (others => p1_data_imm(15));
1007
p1_data_offset(15 downto 0) <= p1_data_imm(15 downto 0);
1008
 
1009
p1_data_addr <= p1_rs + p1_data_offset;
1010
 
1011
--------------------------------------------------------------------------------
1012 121 ja_rd
-- Write enable vector
1013 2 ja_rd
 
1014
-- byte_we is a function of the write size and alignment
1015
-- size = {00=1,01=2,11=4}; we 3 is MSB, 0 is LSB; big endian => 00 is msb
1016
 
1017 140 ja_rd
p1_we_control <= (mem_wait) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
1018 132 ja_rd
--p1_we_control <= (pipeline_stalled) & p1_do_store & p1_store_size & p1_data_addr(1 downto 0);
1019
 
1020
-- Bug: For two SW instructions in a row, the 2nd one will be stalled and lost: 
1021
-- the write will never be executed by the cache.
1022 140 ja_rd
-- Fixed by stalling immediately after asserting byte_we.
1023
-- FIXME the above fix has been tested but is still under trial (provisional)
1024
 
1025 132 ja_rd
-- The present code will not work in cache-less systems (such as the tb0) if 
1026
-- it stalls the CPU. Solution: don't allow stalls in cache-less systems.
1027
-- FIXME this little mess has to be documented.
1028
 
1029
 
1030 2 ja_rd
with p1_we_control select byte_we <=
1031
    "1000"  when "010000",    -- SB %0
1032
    "0100"  when "010001",    -- SB %1
1033
    "0010"  when "010010",    -- SB %2
1034
    "0001"  when "010011",    -- SB %3
1035
    "1100"  when "010100",    -- SH %0
1036
    "0011"  when "010110",    -- SH %2
1037
    "1111"  when "011100",    -- SW %4
1038
    "0000"  when others; -- all other combinations are spurious so don't write
1039
 
1040
-- Data to be stored always comes straight from the reg bank, but it needs to 
1041
-- be shifted so that the LSB is aligned to the write address:
1042
 
1043
data_wr(7 downto 0) <= p1_rt(7 downto 0);
1044
 
1045
with p1_we_control select data_wr(15 downto 8) <=
1046
    p1_rt( 7 downto  0) when "010010",  -- SB %2
1047
    p1_rt(15 downto  8) when others;
1048
 
1049
with p1_we_control select data_wr(23 downto 16) <=
1050
    p1_rt( 7 downto  0) when "010001",  -- SB %1
1051
    p1_rt( 7 downto  0) when "010100",  -- SH %0
1052
    p1_rt(23 downto 16) when others;
1053
 
1054
with p1_we_control select data_wr(31 downto 24) <=
1055
    p1_rt( 7 downto  0) when "010000",  -- SB %0
1056
    p1_rt(15 downto  8) when "010100",  -- SH %0
1057
    p1_rt(31 downto 24) when others;
1058
 
1059
 
1060
--##############################################################################
1061 153 ja_rd
-- CP0 and exception processing
1062 2 ja_rd
 
1063 153 ja_rd
cp0_registers:
1064 2 ja_rd
process(clk)
1065
begin
1066
    if clk'event and clk='1' then
1067
        if reset='1' then
1068 153 ja_rd
            -- KU/IE="10"  ==>  mode=kernel; ints=disabled
1069
            cp0_status <= "000010";  -- bits (KUo/IEo & KUp/IEp) reset to zero
1070 157 ja_rd
            cp0_sr_ku_reg <= '1'; -- delayed KU flag
1071 101 ja_rd
            cp0_cache_control <= "00";
1072 28 ja_rd
            cp0_cause_exc_code <= "00000";
1073
            cp0_cause_bd <= '0';
1074 2 ja_rd
        else
1075 153 ja_rd
            if pipeline_stalled='0' then
1076
                if p1_exception='1' then
1077
                    -- Exception: do all that needs to be done right here
1078 28 ja_rd
 
1079 153 ja_rd
                    -- Save PC in EPC register...
1080
                    cp0_epc <= p0_pc_restart;
1081
                    -- ... set KU flag to Kernel mode ...
1082
                    cp0_status(1) <= '1';
1083
                    -- ... and 'push' old KU/IE flag values 
1084
                    cp0_status(5 downto 4) <= cp0_status(3 downto 2);
1085
                    cp0_status(3 downto 2) <= cp0_status(1 downto 0);
1086
 
1087
                    -- Set the 'exception cause' code... 
1088
                    if p1_unknown_opcode='1' then
1089
                        cp0_cause_exc_code <= "01010"; -- bad opcode ('reserved')
1090
                    elsif p1_cp_unavailable='1' then
1091
                        -- this triggers for mtc0/mfc0 in user mode too
1092
                        cp0_cause_exc_code <= "01011"; -- CP* unavailable 
1093 28 ja_rd
                    else
1094 153 ja_rd
                        if p1_ir_fn(0)='0' then
1095
                            cp0_cause_exc_code <= "01000"; -- syscall
1096
                        else
1097
                            cp0_cause_exc_code <= "01001"; -- break
1098
                        end if;
1099 28 ja_rd
                    end if;
1100 153 ja_rd
                    -- ... and the BD flag for exceptions in delay slots
1101
                    cp0_cause_bd <= cp0_in_delay_slot;
1102
 
1103
                elsif p1_rfe='1' and cp0_status(1)='1' then
1104
                    -- RFE: restore ('pop') the KU/IE flag values
1105
 
1106
                    cp0_status(3 downto 2) <= cp0_status(5 downto 4);
1107
                    cp0_status(1 downto 0) <= cp0_status(3 downto 2);
1108
 
1109
                elsif p1_set_cp0='1' and cp0_status(1)='1' then
1110
                    -- MTC0: load CP0[xx] with Rt
1111
 
1112
                    -- NOTE: in MTCx, the source register is Rt
1113
                    -- FIXME this works because only SR is writeable; when 
1114
                    -- CP0[13].IP1-0 are implemented, check for CP0 reg index.
1115
                    cp0_status <= p1_rt(cp0_status'high downto 0);
1116
                    cp0_cache_control <= p1_rt(17 downto 16);
1117 28 ja_rd
                end if;
1118 2 ja_rd
            end if;
1119 157 ja_rd
            if stall_pipeline='0' then
1120
                cp0_sr_ku_reg <= cp0_status(1);
1121
            end if;
1122 2 ja_rd
        end if;
1123
    end if;
1124 153 ja_rd
end process cp0_registers;
1125 2 ja_rd
 
1126 101 ja_rd
cache_enable <= cp0_cache_control(17);
1127
ic_invalidate <= cp0_cache_control(16);
1128
 
1129 28 ja_rd
cp0_cause_ce <= "00"; -- FIXME CP* traps merged with unimplemented opcode traps
1130
cp0_cause <= cp0_cause_bd & '0' & cp0_cause_ce &
1131 153 ja_rd
             X"00000" & '0' & cp0_cause_exc_code & "00";
1132 28 ja_rd
 
1133 2 ja_rd
-- FIXME the mux should mask to zero for any unused reg index
1134 28 ja_rd
with p1_c0_rs_num select cp0_reg_read <=
1135 153 ja_rd
    X"000000" & "00" & cp0_status   when "01100",
1136 28 ja_rd
    cp0_cause                       when "01101",
1137
    cp0_epc & "00"                  when others;
1138 2 ja_rd
 
1139 28 ja_rd
 
1140 2 ja_rd
end architecture rtl;
1141
 
1142
--------------------------------------------------------------------------------
1143
-- Implementation notes
1144
--------------------------------------------------------------------------------
1145
-- @note1 : 
1146
-- This is the meaning of these two signals:
1147 46 ja_rd
-- pipeline_stalled & stalled_interlock =>
1148 2 ja_rd
--  "00" => normal state
1149
--  "01" => normal state (makes for easier decoding)
1150
--  "10" => all stages of pipeline stalled, including rbank
1151
--  "11" => all stages of pipeline stalled, except reg bank write port
1152
-- 
1153
-- Just to clarify, 'stage X stalled' here means that the registers named 
1154
-- pX_* don't load.
1155
--
1156
-- The register bank WE is enabled when the pipeline is not stalled and when 
1157
-- it is stalled because of a load interlock; so that in case of interlock the
1158
-- load operation can complete while the rest of the pipeline is frozen.
1159 121 ja_rd
--
1160
-- @note2:
1161
-- The logic that checks register indices for data hazards is 'commented out'
1162
-- because it has not been tested yet.
1163 153 ja_rd
--
1164
-- @note3:
1165
-- CP0 instructions (mtc0, mfc0 and rfe) are only partially decoded.
1166
-- This is possible because no other VALID MIPS* opcode shares the decoded 
1167
-- part; that is, we're not going to misdecode a MIPS32 opcode, but we MIGHT
1168
-- mistake a bad opcode for a COP0; we'll live with that for the time being.
1169
--
1170 2 ja_rd
--------------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.