OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_pkg.vhdl] - Blame information for rev 66

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 64 ja_rd
--------------------------------------------------------------------------------
2
-- mips_pkg.vhdl -- Configuration constants & utility types and functions
3
--------------------------------------------------------------------------------
4
-- IMPORTANT:
5
-- Here's where you define the memory map of the system, in the implementation 
6
-- of function decode_addr. 
7
-- You need to change that function to change the memory map, independent of any
8
-- additional address decoding you may do out of the FPGA (e.g. if you have more
9
-- than one chip on any data bus) or out of the MCU module (e.g. when you add
10
-- new IO registers).
11
-- Please see the module c2sb_demo and mips_mcu for examples of memory decoding.
12
--------------------------------------------------------------------------------
13
 
14 2 ja_rd
library ieee;
15
use ieee.std_logic_1164.all;
16
use ieee.std_logic_arith.all;
17
use ieee.std_logic_unsigned.all;
18
 
19
package mips_pkg is
20
 
21 64 ja_rd
---- Basic types ---------------------------------------------------------------
22
 
23
subtype t_word is std_logic_vector(31 downto 0);
24
 
25
 
26
---- System configuration constants --------------------------------------------
27
 
28
-- True to use standard-ish MIPS-1 memory map, false to use Plasma's
29
-- (see implementation of function decode_addr below).
30
constant USE_MIPS1_ADDR_MAP : boolean := true;
31
 
32
-- Reset vector address minus 4 (0xfffffffc for Plasma, 0xbfbffffc for mips1)
33
constant RESET_VECTOR_M4 : t_word   := X"bfbffffc";
34
 
35
-- Trap vector address (0x0000003c for Plasma, 0xbfc00180 for mips1)
36
constant TRAP_VECTOR : t_word       := X"bfc00180";
37
 
38
 
39
---- Address decoding ----------------------------------------------------------
40
 
41
-- Note: it is the cache module that does all internal address decoding --------
42
 
43
-- This is the slice of the address that will be used to decode memory areas
44 48 ja_rd
subtype t_addr_decode is std_logic_vector(31 downto 24);
45 37 ja_rd
 
46 64 ja_rd
-- 'Attributes' of some memory block -- used when decoding memory addresses
47
-- type[3] : can_write[1] : cacheable[1] : delay_states[2]
48
subtype t_range_attr is std_logic_vector(6 downto 0);
49
-- Part of the memory area attribute: the type of memory determines how the
50
-- cache module handles each block
51
subtype t_memory_type is std_logic_vector(2 downto 0);
52
-- These are all the types the cache knows about
53
constant MT_BRAM : t_memory_type            := "000";
54
constant MT_IO_SYNC : t_memory_type         := "001";
55
constant MT_SRAM_16B : t_memory_type        := "010";
56
constant MT_FLASH_16B : t_memory_type       := "011";
57
constant MT_DDR_16B : t_memory_type         := "100";
58
constant MT_UNMAPPED : t_memory_type        := "111";
59 37 ja_rd
 
60 64 ja_rd
 
61
---- More basic types and constants --------------------------------------------
62
 
63 2 ja_rd
subtype t_addr is std_logic_vector(31 downto 0);
64
subtype t_dword is std_logic_vector(63 downto 0);
65
subtype t_regnum is std_logic_vector(4 downto 0);
66
type t_rbank is array(0 to 31) of t_word;
67
subtype t_pc is std_logic_vector(31 downto 2);
68 64 ja_rd
-- This is used as a textual shortcut only
69 2 ja_rd
constant ZERO : t_word := (others => '0');
70 64 ja_rd
-- control word for ALU
71 2 ja_rd
type t_alu_control is record
72
    logic_sel :         std_logic_vector(1 downto 0);
73
    shift_sel :         std_logic_vector(1 downto 0);
74
    shift_amount :      std_logic_vector(4 downto 0);
75
    neg_sel :           std_logic_vector(1 downto 0);
76
    use_arith :         std_logic;
77
    use_logic :         std_logic_vector(1 downto 0);
78
    cy_in :             std_logic;
79
    use_slt :           std_logic;
80
    arith_unsigned :    std_logic;
81
end record t_alu_control;
82 64 ja_rd
-- Flags coming from the ALU
83 2 ja_rd
type t_alu_flags is record
84
    inp1_lt_zero :      std_logic;
85
    inp1_eq_zero :      std_logic;
86
    inp1_lt_inp2 :      std_logic;
87
    inp1_eq_inp2 :      std_logic;
88
end record t_alu_flags;
89
 
90 12 ja_rd
-- 32-cycle mul/div module control. Bits 4-3 & 1-0 of IR.
91
subtype t_mult_function is std_logic_vector(3 downto 0);
92
constant MULT_NOTHING       : t_mult_function := "0000";
93
constant MULT_READ_LO       : t_mult_function := "1010"; -- 18
94
constant MULT_READ_HI       : t_mult_function := "1000"; -- 16
95
constant MULT_WRITE_LO      : t_mult_function := "1011"; -- 19
96
constant MULT_WRITE_HI      : t_mult_function := "1001"; -- 17
97
constant MULT_MULT          : t_mult_function := "1101"; -- 25
98
constant MULT_SIGNED_MULT   : t_mult_function := "1100"; -- 24
99
constant MULT_DIVIDE        : t_mult_function := "1111"; -- 26
100
constant MULT_SIGNED_DIVIDE : t_mult_function := "1110"; -- 27
101
 
102 37 ja_rd
-- Computes ceil(log2(A)), e.g. address width of memory block
103
-- CAN BE USED IN SYNTHESIZABLE CODE as long as called with constant arguments
104
function log2(A : natural) return natural;
105 12 ja_rd
 
106 64 ja_rd
-- Decodes a memory address, gives the type of memory
107
-- CAN BE USED IN SYNTHESIZABLE CODE, argument does not need to be constant
108
function decode_addr(addr : t_addr_decode) return t_range_attr;
109 37 ja_rd
 
110 64 ja_rd
 
111 2 ja_rd
end package;
112 37 ja_rd
 
113
package body mips_pkg is
114
 
115
function log2(A : natural) return natural is
116
begin
117
    for I in 1 to 30 loop -- Works for up to 32 bit integers
118
        if(2**I > A) then
119
            return(I-1);
120
        end if;
121
    end loop;
122
    return(30);
123
end function log2;
124
 
125 64 ja_rd
-- Address decoding for Plasma-like system
126
function decode_addr_plasma(addr : t_addr_decode) return t_range_attr is
127
begin
128
 
129
    case addr(31 downto 27) is
130
    when "00000"    => return MT_BRAM     &"0"&"0"&"00"; -- useg
131
    when "10000"    => return MT_SRAM_16B &"1"&"1"&"00"; -- kseg0
132
    when "00100"    => return MT_IO_SYNC  &"1"&"0"&"00"; -- kseg1 i/o
133
    when others     => return MT_UNMAPPED &"0"&"0"&"00"; -- stray
134
    end case;
135
 
136
end function decode_addr_plasma;
137
 
138
-- Address decoding for MIPS-I-like system
139
function decode_addr_mips1(addr : t_addr_decode) return t_range_attr is
140
begin
141
 
142
    case addr(31 downto 27) is
143
    when "00000"    => return MT_SRAM_16B &"1"&"1"&"00"; -- useg
144
    when "10000"    => return MT_SRAM_16B &"1"&"1"&"00"; -- kseg0
145
    --when "10100"    => return MT_IO_SYNC  &"1"&"0"&"00"; -- kseg1 i/o
146
    when "00100"    => return MT_IO_SYNC  &"1"&"0"&"00"; -- kseg1 i/o
147
    when "10110"    => return MT_FLASH_16B&"0"&"0"&"10"; -- kseg1 flash
148
    when "10111"    => return MT_BRAM     &"0"&"0"&"00"; -- kseg1 boot rom
149
    when others     => return MT_UNMAPPED &"0"&"0"&"00"; -- stray
150
    end case;
151
 
152
end function decode_addr_mips1;
153
 
154
 
155
function decode_addr(addr : t_addr_decode) return t_range_attr is
156
begin
157
    if USE_MIPS1_ADDR_MAP then
158
        return decode_addr_mips1(addr);
159
    else
160
        return decode_addr_plasma(addr);
161
    end if;
162
 
163
end function decode_addr;
164
 
165 37 ja_rd
end package body;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.