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ja_rd |
--##############################################################################
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-- Simulation test bench -- not synthesizable.
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--
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-- Simulates the MCU core connected to a simulated external static RAM on a
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-- 16-bit bus, plus an optional 8-bit static ROM. This setup is more or less
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-- that of develoment board DE-1 from Terasic.
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--------------------------------------------------------------------------------
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-- Console logging:
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--
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-- Console output (at addresses compatible to Plasma's) is logged to text file
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-- "hw_sim_console_log.txt".
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--
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-- IMPORTANT: The code that echoes UART TX data to the simulation console does
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-- line buffering; it will not print anything until it gets a CR (0x0d), and
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-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you
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-- expect it.
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--
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-- Console logging is done by monitoring CPU writes to the UART, NOT by looking
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-- at the TxD pin. It will NOT catch baud-related problems, etc.
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--------------------------------------------------------------------------------
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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--##############################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.mips_pkg.all;
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use work.mips_tb_pkg.all;
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use work.sim_params_pkg.all;
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use work.txt_util.all;
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entity mips_tb is
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end;
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architecture testbench of mips_tb is
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-- NOTE: simulation parameters are defined in sim_params_pkg
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-- External SRAM and interface signals -----------------------------------------
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signal sram1 : t_sram := ( others => X"00");
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signal sram0 : t_sram := ( others => X"00");
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signal sram_chip_addr : std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_output : std_logic_vector(15 downto 0);
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-- PROM table and interface signals --------------------------------------------
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-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
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-- cycle time (70 or 90 ns).
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signal prom_rd_addr : t_prom_address;
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signal prom_output : std_logic_vector(7 downto 0);
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signal prom_oe_n : std_logic;
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signal prom : t_prom := ( PROM_DATA );
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-- I/O devices -----------------------------------------------------------------
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signal data_uart : std_logic_vector(31 downto 0);
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signal data_uart_status : std_logic_vector(31 downto 0);
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signal uart_tx_rdy : std_logic := '1';
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signal uart_rx_rdy : std_logic := '1';
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--------------------------------------------------------------------------------
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signal clk : std_logic := '0';
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signal reset : std_logic := '1';
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signal interrupt : std_logic := '0';
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signal done : std_logic := '0';
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-- interface to asynchronous 16-bit-wide external SRAM
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signal mpu_sram_address : t_word;
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signal mpu_sram_data_rd : std_logic_vector(15 downto 0);
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signal mpu_sram_data_wr : std_logic_vector(15 downto 0);
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signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
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signal mpu_sram_oe_n : std_logic;
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-- interface to i/o
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signal io_rd_data : std_logic_vector(31 downto 0);
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signal io_wr_data : std_logic_vector(31 downto 0);
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signal io_rd_addr : std_logic_vector(31 downto 2);
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signal io_wr_addr : std_logic_vector(31 downto 2);
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signal io_rd_vma : std_logic;
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signal io_byte_we : std_logic_vector(3 downto 0);
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signal rxd : std_logic;
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signal txd : std_logic;
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--------------------------------------------------------------------------------
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-- Logging signals
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-- Log file
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file log_file: TEXT open write_mode is "hw_sim_log.txt";
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-- Console output log file
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file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
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-- All the info needed by the logger is here
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signal log_info : t_log_info;
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-- Debug signals ---------------------------------------------------------------
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begin
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-- UUT instantiation -------------------------------------------------------
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mpu: entity work.mips_mpu
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generic map (
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CLOCK_FREQ => 50000000,
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SRAM_ADDR_SIZE => 32
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)
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port map (
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interrupt => '0',
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-- interface to FPGA i/o devices
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io_rd_data => io_rd_data,
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io_rd_addr => io_rd_addr,
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io_wr_addr => io_wr_addr,
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io_wr_data => io_wr_data,
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io_rd_vma => io_rd_vma,
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io_byte_we => io_byte_we,
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-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
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sram_address => mpu_sram_address,
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sram_data_rd => mpu_sram_data_rd,
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sram_data_wr => mpu_sram_data_wr,
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sram_byte_we_n => mpu_sram_byte_we_n,
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sram_oe_n => mpu_sram_oe_n,
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uart_rxd => rxd,
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uart_txd => txd,
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debug_info => OPEN,
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clk => clk,
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reset => reset
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);
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-- Master clock: free running clock used as main module clock --------------
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run_master_clock:
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process(done, clk)
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begin
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if done = '0' then
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clk <= not clk after T/2;
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end if;
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end process run_master_clock;
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-- Main simulation process: reset MCU and wait for fixed period ------------
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drive_uut:
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process
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variable l : line;
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begin
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wait for T*4;
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reset <= '0';
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wait for T*SIMULATION_LENGTH;
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-- Flush console output to log console file (in case the end of the
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-- simulation caugh an unterminated line in the buffer)
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if log_info.con_line_ix > 1 then
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write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
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writeline(con_file, l);
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end if;
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print("TB finished");
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done <= '1';
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wait;
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end process drive_uut;
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-- SRAM/FLASH mux (on a real board this would be a simple address decoder)
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mpu_sram_data_rd <=
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X"00" & prom_output when mpu_sram_address(31 downto 27)="10110" else
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sram_output;
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-- Do a very basic simulation of an external SRAM --------------------------
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sram_chip_addr <= mpu_sram_address(SRAM_ADDR_SIZE downto 1);
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-- FIXME should add some verification of /WE
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sram_output <=
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sram1(conv_integer(unsigned(sram_chip_addr))) &
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sram0(conv_integer(unsigned(sram_chip_addr))) when mpu_sram_oe_n='0'
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else (others => 'Z');
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simulated_sram_write:
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process(mpu_sram_byte_we_n, mpu_sram_address, mpu_sram_oe_n)
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begin
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-- Write cycle
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-- FIXME should add OE\ to write control logic
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if mpu_sram_byte_we_n'event or mpu_sram_address'event then
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if mpu_sram_byte_we_n(1)='0' then
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sram1(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr(15 downto 8);
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end if;
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if mpu_sram_byte_we_n(0)='0' then
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sram0(conv_integer(unsigned(sram_chip_addr))) <= mpu_sram_data_wr( 7 downto 0);
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end if;
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end if;
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end process simulated_sram_write;
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-- Do a very basic simulation of an external PROM (FLASH) ------------------
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-- (wired to the same bus as the sram and both are static).
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prom_rd_addr <= mpu_sram_address(PROM_ADDR_SIZE+1 downto 2);
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prom_oe_n <= mpu_sram_oe_n;
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prom_output <=
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prom(conv_integer(unsigned(prom_rd_addr)))(31 downto 24) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="00" else
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prom(conv_integer(unsigned(prom_rd_addr)))(23 downto 16) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="01" else
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prom(conv_integer(unsigned(prom_rd_addr)))(15 downto 8) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="10" else
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prom(conv_integer(unsigned(prom_rd_addr)))( 7 downto 0) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="11" else
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(others => 'Z');
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-- Simulate dummy I/O traffic external to the MCU --------------------------
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-- FIXME console logging missing! IO too!
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-- This is useless (the simulated UART will not be actually used)
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-- but at least prevents the simulator from optimizing the logic away.
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rxd <= txd;
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-- Logging process: launch logger function ---------------------------------
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log_execution:
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process
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begin
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log_cpu_activity(clk, reset, done,
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"mips_tb/mpu", "cpu",
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log_info, "log_info",
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LOG_TRIGGER_ADDRESS, log_file, con_file);
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wait;
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end process log_execution;
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end architecture testbench;
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