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1 193 ja_rd
--##############################################################################
2
-- Simulation test bench -- not synthesizable.
3
--
4
-- Simulates the MCU core connected to a simulated external static RAM on a 
5
-- 16-bit bus, plus an optional 8-bit static ROM. This setup is more or less 
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-- that of develoment board DE-1 from Terasic.
7
--------------------------------------------------------------------------------
8
-- Console logging:
9
--
10
-- Console output (at addresses compatible to Plasma's) is logged to text file
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-- "hw_sim_console_log.txt".
12
--
13
-- IMPORTANT: The code that echoes UART TX data to the simulation console does
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-- line buffering; it will not print anything until it gets a CR (0x0d), and
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-- will ifnore LFs (0x0a). Bear this in mind if you see no output when you 
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-- expect it.
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--
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-- Console logging is done by monitoring CPU writes to the UART, NOT by looking
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-- at the TxD pin. It will NOT catch baud-related problems, etc.
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--------------------------------------------------------------------------------
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-- WARNING: Will only work on Modelsim; uses custom library SignalSpy.
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--##############################################################################
23
 
24
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
29
 
30
use work.mips_pkg.all;
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use work.mips_tb_pkg.all;
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use work.sim_params_pkg.all;
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use work.txt_util.all;
34
 
35
entity mips_tb is
36
end;
37
 
38
 
39
architecture testbench of mips_tb is
40
 
41
-- NOTE: simulation parameters are defined in sim_params_pkg
42
 
43
 
44
-- External SRAM and interface signals -----------------------------------------
45
 
46 207 ja_rd
-- Static 16-bit wide RAM modelled as two separate byte-wide arrays foer easy 
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-- simulation of byte enables.
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-- Using shared variables for big memory arrays speeds up simulation a lot;
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-- see Modelsim 6.3 User Manual, section on 'Modelling Memory'.
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-- WARNING: I have only tested this construct with Modelsim SE 6.3.
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shared variable sram1 : t_sram := ( others => X"00");
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shared variable sram0 : t_sram := ( others => X"00");
53 193 ja_rd
 
54
signal sram_chip_addr :     std_logic_vector(SRAM_ADDR_SIZE downto 1);
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signal sram_output :        std_logic_vector(15 downto 0);
56
 
57
 
58
-- PROM table and interface signals --------------------------------------------
59
 
60
-- We'll simulate a 16-bit-wide static PROM (e.g. a Flash) with some serious
61
-- cycle time (70 or 90 ns).
62 207 ja_rd
-- FIXME FLASH read cycle time not modelled yet.
63 193 ja_rd
signal prom_rd_addr :       t_prom_address;
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signal prom_output :        std_logic_vector(7 downto 0);
65
signal prom_oe_n :          std_logic;
66
 
67 207 ja_rd
-- 8-bit wide FLASH modelled as read only block.
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-- We don't simulate the actual FLASH chip: no FLASH writes, control regs, etc.
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shared variable prom : t_prom := ( PROM_DATA );
70 193 ja_rd
 
71
 
72
-- I/O devices -----------------------------------------------------------------
73
 
74
signal data_uart :          std_logic_vector(31 downto 0);
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signal data_uart_status :   std_logic_vector(31 downto 0);
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signal uart_tx_rdy :        std_logic := '1';
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signal uart_rx_rdy :        std_logic := '1';
78
 
79
--------------------------------------------------------------------------------
80
 
81
signal clk :                std_logic := '0';
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signal reset :              std_logic := '1';
83
signal interrupt :          std_logic := '0';
84
signal done :               std_logic := '0';
85
 
86
-- interface to asynchronous 16-bit-wide external SRAM
87
signal mpu_sram_address :   t_word;
88
signal mpu_sram_data_rd :   std_logic_vector(15 downto 0);
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signal mpu_sram_data_wr :   std_logic_vector(15 downto 0);
90
signal mpu_sram_byte_we_n : std_logic_vector(1 downto 0);
91
signal mpu_sram_oe_n :      std_logic;
92
 
93
-- interface to i/o
94
signal io_rd_data :         std_logic_vector(31 downto 0);
95
signal io_wr_data :         std_logic_vector(31 downto 0);
96
signal io_rd_addr :         std_logic_vector(31 downto 2);
97
signal io_wr_addr :         std_logic_vector(31 downto 2);
98
signal io_rd_vma :          std_logic;
99
signal io_byte_we :         std_logic_vector(3 downto 0);
100
 
101
signal rxd :                std_logic;
102
signal txd :                std_logic;
103
 
104 200 ja_rd
-- Other CPU signals 
105
signal cpu_irq :            std_logic_vector(7 downto 0);
106 193 ja_rd
 
107
--------------------------------------------------------------------------------
108
-- Logging signals
109
 
110
 
111
-- Log file
112
file log_file: TEXT open write_mode is "hw_sim_log.txt";
113
 
114
-- Console output log file
115
file con_file: TEXT open write_mode is "hw_sim_console_log.txt";
116
 
117
-- All the info needed by the logger is here
118
signal log_info :           t_log_info;
119
 
120 200 ja_rd
-- IRQ trigger simulation ------------------------------------------------------
121 193 ja_rd
 
122 200 ja_rd
signal irq_trigger_addr :   std_logic_vector(2 downto 0);
123
signal irq_trigger_data :   std_logic_vector(31 downto 0);
124
signal irq_trigger_load :   std_logic;
125 193 ja_rd
 
126 200 ja_rd
subtype t_irq_countdown     is std_logic_vector(31 downto 0);
127
type t_irq_countdown_array  is array(0 to 7) of t_irq_countdown;
128 193 ja_rd
 
129 200 ja_rd
signal irq_countdown :      t_irq_countdown_array;
130
 
131 211 ja_rd
-- Simulated block of 4 read/write, 32-bit I/O registers, used in cache test. 
132
type t_debug_reg_block is array(0 to 3) of t_word;
133
signal debug_reg_block :    t_debug_reg_block;
134 200 ja_rd
 
135 211 ja_rd
 
136 193 ja_rd
begin
137
 
138
    -- UUT instantiation -------------------------------------------------------
139
    mpu: entity work.mips_mpu
140
    generic map (
141
        CLOCK_FREQ     => 50000000,
142
        SRAM_ADDR_SIZE => 32
143
    )
144
    port map (
145 205 ja_rd
        interrupt       => cpu_irq,
146 193 ja_rd
 
147
        -- interface to FPGA i/o devices
148
        io_rd_data      => io_rd_data,
149
        io_rd_addr      => io_rd_addr,
150
        io_wr_addr      => io_wr_addr,
151
        io_wr_data      => io_wr_data,
152
        io_rd_vma       => io_rd_vma,
153
        io_byte_we      => io_byte_we,
154
 
155
        -- interface to asynchronous 16-bit-wide EXTERNAL SRAM
156
        sram_address    => mpu_sram_address,
157
        sram_data_rd    => mpu_sram_data_rd,
158
        sram_data_wr    => mpu_sram_data_wr,
159
        sram_byte_we_n  => mpu_sram_byte_we_n,
160
        sram_oe_n       => mpu_sram_oe_n,
161
 
162
        uart_rxd        => rxd,
163
        uart_txd        => txd,
164
 
165
        debug_info      => OPEN,
166
 
167
        clk             => clk,
168
        reset           => reset
169
    );
170
 
171
 
172
    -- Master clock: free running clock used as main module clock --------------
173
    run_master_clock:
174
    process(done, clk)
175
    begin
176
        if done = '0' then
177
            clk <= not clk after T/2;
178
        end if;
179
    end process run_master_clock;
180
 
181
    -- Main simulation process: reset MCU and wait for fixed period ------------
182
    drive_uut:
183
    process
184
    variable l : line;
185
    begin
186
        wait for T*4;
187
        reset <= '0';
188
 
189
        wait for T*SIMULATION_LENGTH;
190
 
191
        -- Flush console output to log console file (in case the end of the
192
        -- simulation caugh an unterminated line in the buffer)
193
        if log_info.con_line_ix > 1 then
194
            write(l, log_info.con_line_buf(1 to log_info.con_line_ix));
195
            writeline(con_file, l);
196
        end if;
197
 
198
        print("TB finished");
199
        done <= '1';
200
        wait;
201
 
202
    end process drive_uut;
203
 
204
 
205
 
206
    -- SRAM/FLASH mux (on a real board this would be a simple address decoder)
207
    mpu_sram_data_rd <=
208
        X"00" & prom_output when mpu_sram_address(31 downto 27)="10110" else
209
        sram_output;
210
 
211
 
212
    -- Do a very basic simulation of an external SRAM --------------------------
213
 
214
    sram_chip_addr <= mpu_sram_address(SRAM_ADDR_SIZE downto 1);
215
 
216
    -- FIXME should add some verification of /WE 
217
    sram_output <=
218
        sram1(conv_integer(unsigned(sram_chip_addr))) &
219
        sram0(conv_integer(unsigned(sram_chip_addr)))   when mpu_sram_oe_n='0'
220
        else (others => 'Z');
221
 
222
    simulated_sram_write:
223
    process(mpu_sram_byte_we_n, mpu_sram_address, mpu_sram_oe_n)
224
    begin
225
        -- Write cycle
226
        -- FIXME should add OE\ to write control logic
227
        if mpu_sram_byte_we_n'event or mpu_sram_address'event then
228
            if mpu_sram_byte_we_n(1)='0' then
229 207 ja_rd
                sram1(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr(15 downto  8);
230 193 ja_rd
            end if;
231
            if mpu_sram_byte_we_n(0)='0' then
232 207 ja_rd
                sram0(conv_integer(unsigned(sram_chip_addr))) := mpu_sram_data_wr( 7 downto  0);
233 193 ja_rd
            end if;
234
        end if;
235
    end process simulated_sram_write;
236
 
237
 
238
    -- Do a very basic simulation of an external PROM (FLASH) ------------------
239
    -- (wired to the same bus as the sram and both are static).
240
 
241
    prom_rd_addr <= mpu_sram_address(PROM_ADDR_SIZE+1 downto 2);
242
 
243
    prom_oe_n <= mpu_sram_oe_n;
244
 
245
    prom_output <=
246
        prom(conv_integer(unsigned(prom_rd_addr)))(31 downto 24) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="00" else
247
        prom(conv_integer(unsigned(prom_rd_addr)))(23 downto 16) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="01" else
248
        prom(conv_integer(unsigned(prom_rd_addr)))(15 downto  8) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="10" else
249
        prom(conv_integer(unsigned(prom_rd_addr)))( 7 downto  0) when prom_oe_n='0' and mpu_sram_address(1 downto 0)="11" else
250
        (others => 'Z');
251
 
252
 
253
    -- Simulate dummy I/O traffic external to the MCU --------------------------
254 200 ja_rd
    -- the only IO present is the test interrupt trigger registers
255
    simulated_io:
256
    process(clk)
257
    variable i : integer;
258
    variable uart_data : integer;
259
    begin
260
        if clk'event and clk='1' then
261
            if io_byte_we /= "0000" then
262
                if io_wr_addr(31 downto 16)=X"2001" then
263 211 ja_rd
                    -- IRQ trigger register block (write only)
264 200 ja_rd
                    irq_trigger_load <= '1';
265
                    irq_trigger_data <= io_wr_data;
266
                    irq_trigger_addr <= io_wr_addr(4 downto 2);
267 211 ja_rd
                elsif io_wr_addr(31 downto 12)=X"2000f" then
268
                    -- Debug register block (read/write)
269
                    debug_reg_block(conv_integer(unsigned(io_wr_addr(3 downto 2)))) <= io_wr_data;
270 200 ja_rd
                else
271
                    irq_trigger_load <= '0';
272
                end if;
273
            else
274
                irq_trigger_load <= '0';
275
            end if;
276
        end if;
277
    end process simulated_io;
278
 
279 211 ja_rd
    -- The only readable i/o is the debug reg block. We simulate an asynchronous
280
    -- read port (a mux).
281
    io_rd_data <= debug_reg_block(conv_integer(unsigned(io_rd_addr(3 downto 2))));
282
 
283 200 ja_rd
    -- Simulate IRQs -----------------------------------------------------------
284
    irq_trigger_registers:
285
    process(clk)
286
    variable index : integer range 0 to 7;
287
    begin
288
        if clk'event and clk='1' then
289
            if reset='1' then
290
                cpu_irq <= "00000000";
291
            else
292
                if irq_trigger_load='1' then
293
                    index := conv_integer(irq_trigger_addr);
294
                    irq_countdown(index) <= irq_trigger_data;
295
                else
296
                    for index in 0 to 7 loop
297
                        if irq_countdown(index) = X"00000001" then
298
                            cpu_irq(index) <= '1';
299
                            irq_countdown(index) <= irq_countdown(index) - 1;
300
                        elsif irq_countdown(index)/=X"00000000" then
301
                            irq_countdown(index) <= irq_countdown(index) - 1;
302
                            cpu_irq(index) <= '0';
303
                        else
304
                            cpu_irq(index) <= '0';
305
                        end if;
306
                    end loop;
307
                end if;
308
            end if;
309
        end if;
310
    end process irq_trigger_registers;
311 193 ja_rd
 
312 200 ja_rd
 
313 193 ja_rd
    -- This is useless (the simulated UART will not be actually used)
314
    -- but at least prevents the simulator from optimizing the logic away.
315
    rxd <= txd;
316
 
317
 
318
    -- Logging process: launch logger function ---------------------------------
319
    log_execution:
320
    process
321
    begin
322
        log_cpu_activity(clk, reset, done,
323
                         "mips_tb/mpu", "cpu",
324
                         log_info, "log_info",
325
                         LOG_TRIGGER_ADDRESS, log_file, con_file);
326
        wait;
327
    end process log_execution;
328
 
329
end architecture testbench;

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