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[/] [ipv4_packet_transmitter/] [trunk/] [IPv4_PACKET_TRANSMITTER/] [ALLOW_ZERO_UDP_CHECKSUM.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 NikosAl
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    14:46:33 12/04/2009 
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-- Design Name: 
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-- Module Name:    ALLOW_ZERO_UDP_CHECKSUM - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ALLOW_ZERO_UDP_CHECKSUM is
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    Port ( clk : in  STD_LOGIC;
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           input : in  STD_LOGIC;
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                          output_to_readen  : out STD_LOGIC;
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           output_to_datasel : out  STD_LOGIC);
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end ALLOW_ZERO_UDP_CHECKSUM;
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architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is
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signal input_reg : std_logic;
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begin
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process(clk)
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begin
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        if clk'event and clk='1' then
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                input_reg<=input;
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        end if;
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end process;
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output_to_readen<=input_reg;
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process(clk)
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begin
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        if clk'event and clk='1' then
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                output_to_datasel<=input_reg;
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        end if;
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end process;
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end Behavioral;
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