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[/] [ipv4_packet_transmitter/] [trunk/] [IPv4_PACKET_TRANSMITTER/] [dist_mem_64x8.vhd] - Blame information for rev 2

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1 2 NikosAl 
--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--------------------------------------------------------------------------------
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--   ____  ____
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--  /   /\/   /
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-- /___/  \  /    Vendor: Xilinx
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-- \   \   \/     Version: K.39
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--  \   \         Application: netgen
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--  /   /         Filename: dist_mem_64x8.vhd
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-- /___/   /\     Timestamp: Tue Dec 01 15:45:04 2009
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-- \   \  /  \
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--  \___\/\___\
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--
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-- Command      : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.vhd
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-- Device       : 5vsx95tff1136-1
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-- Input file   : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.ngc
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-- Output file  : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.vhd
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-- # of Entities        : 1
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-- Design Name  : dist_mem_64x8
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-- Xilinx       : C:\Xilinx\10.1\ISE
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--
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-- Purpose:
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--     This VHDL netlist is a verification model and uses simulation
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--     primitives which may not represent the true implementation of the
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--     device, however the netlist is functionally correct and should not
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--     be modified. This file cannot be synthesized and should only be used
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--     with supported simulation tools.
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--
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-- Reference:
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--     Development System Reference Guide, Chapter 23
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--     Synthesis and Simulation Design Guide, Chapter 6
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--
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--------------------------------------------------------------------------------
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35 
 
36 
-- synthesis translate_off
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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use UNISIM.VPKG.ALL;
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43 
entity dist_mem_64x8 is
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  port (
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    clk : in STD_LOGIC := 'X';
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    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
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    qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
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  );
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end dist_mem_64x8;
50 
 
51 
architecture STRUCTURE of dist_mem_64x8 is
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  signal N0 : STD_LOGIC;
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  signal N1 : STD_LOGIC;
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  signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
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  signal qspo_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
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  signal BU2_U0_gen_rom_rom_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );
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  signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
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begin
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  a_2(5) <= a(5);
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  a_2(4) <= a(4);
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  a_2(3) <= a(3);
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  a_2(2) <= a(2);
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  a_2(1) <= a(1);
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  a_2(0) <= a(0);
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  qspo(7) <= qspo_3(7);
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  qspo(6) <= qspo_3(6);
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  qspo(5) <= qspo_3(5);
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  qspo(4) <= qspo_3(4);
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  qspo(3) <= qspo_3(3);
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  qspo(2) <= qspo_3(2);
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  qspo(1) <= qspo_3(1);
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  qspo(0) <= qspo_3(0);
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  VCC_0 : VCC
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    port map (
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      P => N1
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    );
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  GND_1 : GND
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    port map (
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      G => N0
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000111 : LUT6
82 
    generic map(
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      INIT => X"0000061400040604"
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    )
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    port map (
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      I0 => a_2(2),
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      I1 => a_2(3),
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      I2 => a_2(5),
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      I3 => a_2(1),
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      I4 => a_2(4),
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      I5 => a_2(0),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(1)
93 
    );
94 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000071 : LUT6
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    generic map(
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      INIT => X"2100210023022222"
97 
    )
98 
    port map (
99 
      I0 => a_2(3),
100 
      I1 => a_2(5),
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      I2 => a_2(4),
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      I3 => a_2(1),
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      I4 => a_2(0),
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      I5 => a_2(2),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(7)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000041 : LUT6
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    generic map(
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      INIT => X"0204162600041726"
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    )
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    port map (
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      I0 => a_2(2),
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      I1 => a_2(3),
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      I2 => a_2(5),
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      I3 => a_2(1),
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      I4 => a_2(4),
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      I5 => a_2(0),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(4)
119 
    );
120 
  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000051 : LUT6
121 
    generic map(
122 
      INIT => X"2301030311110112"
123 
    )
124 
    port map (
125 
      I0 => a_2(4),
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      I1 => a_2(5),
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      I2 => a_2(2),
128 
      I3 => a_2(0),
129 
      I4 => a_2(1),
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      I5 => a_2(3),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(5)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : LUT6
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    generic map(
135 
      INIT => X"0100057801014578"
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    )
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    port map (
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      I0 => a_2(5),
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      I1 => a_2(1),
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      I2 => a_2(2),
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      I3 => a_2(3),
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      I4 => a_2(4),
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      I5 => a_2(0),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(2)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : LUT6
147 
    generic map(
148 
      INIT => X"090101020B0A0202"
149 
    )
150 
    port map (
151 
      I0 => a_2(3),
152 
      I1 => a_2(4),
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      I2 => a_2(5),
154 
      I3 => a_2(1),
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      I4 => a_2(0),
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      I5 => a_2(2),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(3)
158 
    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000061 : LUT6
160 
    generic map(
161 
      INIT => X"010701EF02460224"
162 
    )
163 
    port map (
164 
      I0 => a_2(2),
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      I1 => a_2(3),
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      I2 => a_2(4),
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      I3 => a_2(5),
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      I4 => a_2(0),
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      I5 => a_2(1),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(6)
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    );
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  BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : LUT6
173 
    generic map(
174 
      INIT => X"1202020210347366"
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    )
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    port map (
177 
      I0 => a_2(3),
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      I1 => a_2(5),
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      I2 => a_2(1),
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      I3 => a_2(0),
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      I4 => a_2(2),
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      I5 => a_2(4),
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      O => BU2_U0_gen_rom_rom_inst_spo_int(0)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_7 : FD
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    generic map(
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      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(7),
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      Q => qspo_3(7)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_6 : FD
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    generic map(
196 
      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(6),
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      Q => qspo_3(6)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD
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    generic map(
205 
      INIT => '0'
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    )
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    port map (
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      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(5),
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      Q => qspo_3(5)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD
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    generic map(
214 
      INIT => '0'
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    )
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    port map (
217 
      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(4),
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      Q => qspo_3(4)
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    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_3 : FD
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    generic map(
223 
      INIT => '0'
224 
    )
225 
    port map (
226 
      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(3),
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      Q => qspo_3(3)
229 
    );
230 
  BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD
231 
    generic map(
232 
      INIT => '0'
233 
    )
234 
    port map (
235 
      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(2),
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      Q => qspo_3(2)
238 
    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD
240 
    generic map(
241 
      INIT => '0'
242 
    )
243 
    port map (
244 
      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(1),
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      Q => qspo_3(1)
247 
    );
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  BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD
249 
    generic map(
250 
      INIT => '0'
251 
    )
252 
    port map (
253 
      C => clk,
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      D => BU2_U0_gen_rom_rom_inst_spo_int(0),
255 
      Q => qspo_3(0)
256 
    );
257 
  BU2_XST_GND : GND
258 
    port map (
259 
      G => BU2_qdpo(0)
260 
    );
261 
 
262 
end STRUCTURE;
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-- synthesis translate_on

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