Subversion Repositories irig_regenerator

--------------------------------------------------------------------------

-- Package of IRIG time pattern generator components

--

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

package irig_time_pack is

-- This component includes the capability to output both DC Level and modulated timecode streams.

-- It has been coded with 32 bit wide registers

  component irig_time_generator

    generic (

      SYS_CLK_RATE : real; -- Needed for carrier generation

      DEF_R_0 : unsigned(31 downto 0); -- Years, Days

      DEF_R_1 : unsigned(31 downto 0); -- Hours, Minutes, Seconds

      DEF_R_2 : unsigned(31 downto 0); -- Control(31:0)

      DEF_R_3 : unsigned(31 downto 0); -- Control(44:32)

      DEF_R_4 : unsigned(31 downto 0); -- Rate Setting

      DEF_R_5 : unsigned(31 downto 0); -- Fields Used [ctrl,sbs,year]

      DEF_R_6 : unsigned(31 downto 0); -- Carrier Frequency

      DEF_R_Z : unsigned(31 downto 0)  -- Value returned for nonexistent registers

    );

    port (

      sys_rst_n   : in std_logic;

      sys_clk     : in std_logic;

      sys_clk_en  : in std_logic;

      -- Bus interface

      adr_i       : in  unsigned(3 downto 0);

      sel_i       : in  std_logic;

      we_i        : in  std_logic;

      dat_i       : in  unsigned(31 downto 0);

      dat_o       : out unsigned(31 downto 0);

      ack_o       : out std_logic;

      -- Pulse per second time reference

      pps_i       : in  std_logic;

      pps_ext_i   : in  std_logic;

      -- IRIG select inputs

      -- Active only when register 0x4 set to zero.

      rate_i      : in  unsigned(2 downto 0); -- Rates    : 0,1=>B, 2=>A, 3=>G, 4=>NASA 36-bit

      carrier_i   : in  unsigned(2 downto 0); -- Carriers : 0=DCLS, 1=100Hz, 2=1kHz, 3=10kHz, 4=100kHz

      codes_i     : in  unsigned(2 downto 0); -- Codes    : (2)=> control, (1)=> SBS, (0)=> year

      -- Serial IRIG time stream, LVTTL level output

      time_dcl_o  : out std_logic;

      cap_gnd_o   : out unsigned(2 downto 0);

      ref_o       : out std_logic;

      carrier_o   : out unsigned(1 downto 0)

    );

  end component;

-- This component includes the capability to receive DC Level timecode streams.

-- External circuitry should low-pass filter the timecode signal to remove the

-- carrier frequency, and pass the envelope signal directly

-- to this module, where it is treated as a digital input.

-- Although it is a receiver, it also acts as a "synchronized transmitter."

  component irig_time_regenerator

    generic (

      SYS_CLK_RATE   : real;

      LOCK_THRESHOLD : integer; -- Packets received before entering locked state

      DEF_R_0 : unsigned(31 downto 0); -- Years, Days

      DEF_R_1 : unsigned(31 downto 0); -- Hours, Minutes, Seconds

      DEF_R_2 : unsigned(31 downto 0); -- Control(31:0)

      DEF_R_3 : unsigned(31 downto 0); -- Control(44:32)

      DEF_R_4 : unsigned(31 downto 0); -- Rate Setting

      DEF_R_5 : unsigned(31 downto 0); -- Fields Used [ctrl,sbs,year]

      DEF_R_6 : unsigned(31 downto 0); -- Carrier Frequency

      DEF_R_A : unsigned(31 downto 0); -- Initial value of carrier detect bias

      DEF_R_Z : unsigned(31 downto 0)  -- Value returned for nonexistent registers

    );

    port (

      sys_rst_n     : in std_logic;

      sys_clk       : in std_logic;

      sys_clk_en    : in std_logic;

      -- Bus interface

      adr_i         : in  unsigned(3 downto 0);

      sel_i         : in  std_logic;

      we_i          : in  std_logic;

      dat_i         : in  unsigned(31 downto 0);

      dat_o         : out unsigned(31 downto 0);

      ack_o         : out std_logic;

      -- IRIG select inputs

      -- Active only when register 0x4 set to zero.

      rate_i        : in  unsigned(2 downto 0); -- Rates    : 0,1=>B, 2=>A, 3=>G, 4=>NASA 36-bit

      carrier_i     : in  unsigned(2 downto 0); -- Carriers : 0=DCLS, 1=100Hz, 2=1kHz, 3=10kHz, 4=100kHz

      codes_i       : in  unsigned(2 downto 0); -- Codes    : (2)=> control, (1)=> SBS, (0)=> year

      -- IRIG time output, parallel form

      time_o        : out unsigned(67 downto 0);

      -- Carrier Detect Select output, PPS input,

      -- IRIG time input, tracking and lock indicators

      cdet_sel_o    : out std_logic;

      pps_i         : in  std_logic;

      time_cdet_i   : in  std_logic;

      cdet_val_o    : out unsigned(1 downto 0);

      active_o      : out std_logic;

      tracking_o    : out std_logic;

      lock_o        : out std_logic;

      neverlocked_o : out std_logic;

      -- Serial IRIG time stream output, LVTTL level

      time_dcl_o    : out std_logic;

      cap_gnd_o     : out std_logic;

      ref_o         : out std_logic;

      carrier_o     : out unsigned(1 downto 0)

    );

  end component;

end irig_time_pack;

package body irig_time_pack is

end irig_time_pack;

-------------------------------------------------------------------------------

-- IRIG time pattern generator core

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Date  : Oct. 14, 2010 Copied code from irig_time, changed registers to

--                       a 32-bit format.

--         Nov. 24, 2010 Added DEF_R_Z generic parameter

--         Mar. 28, 2012 Moved clk_en_1mhz logic inside this module, updated

--                       description.  Added "pps_ext_i" input.  Changed name

--                       to "irig_time_generator"

--         Apr.  4, 2012 Swapped R0 and R1, so that years & days are first.

--                       This arrangement will be more congruent with the

--                       IRIG time receiver.

--         Apr.  5, 2012 Added support for NASA 36-bit (WWV) format, by

--                       extending the rate setting to include a new value,

--                       of 4.

--         Apr. 30, 2013 Changed SYS_CLK_RATE from integer to real type.

--         Dec.  2, 2013 Decreased SQF_BITS from 6 to 4, in order to increase

--                       the frequency of the square_fast signal by a factor

--                       of 4.

--         Mar. 11, 2015 Added leap_year bit to register zero.  Prevented

--                       day values higher than 366 from persisting.

--

-- Description

-------------------------------------------------------------------------------

-- This time pattern generator outputs DC Level data, plus a pair of digital outputs

-- which contain a modulated carrier signal.  The modulated carrier frequency is

-- the low-frequency heterodyne signal generated by digital mixing of a 500 kHz 

-- squarewave with a 501 kHz (IRIG "B"), 510 kHz (IRIG "A") or 600 kHz (IRIG "G") 

-- squarewave, as generated by a DDS.  As such, the digital output needs to be

-- low-pass filtered in order to cut down the amplitude of the high-frequency

-- heterodyne signal, plus the 3rd and higher order harmonics of the squarewaves

-- used.  In order to modulate the amplitude of the resulting low-pass filtered

-- carrier over a 3:1 ratio (An AM modulation index of 0.5, meaning 50% modulation

-- depth) a 2-bit R-2R resistor ladder network DAC is recommended for use outside

-- the FPGA.  Also, in order to keep the modulated signal balanced, a reference

-- voltage other than ground is used.  The reference voltage is nominally 1/2 of

-- the FPGA VCCo supply voltage (3.3V * 0.5 = 1.65V).  The FPGA generates this

-- reference voltage through the use of an output which provides a 50% duty cycle

-- squarewave.  The schematic is as follows:

--

--                    R  1.65V  R     R

--         ref_o o---/\/\--.--/\/\--/\/\--.

--                         |              |

--                    Cref - +            |

--                    15uF -              |

--                         |              |

--                        GND             |

--                              R     R   |

--  carrier_o(0) o------------/\/\--/\/\--.

--    (LSB)                               |

--                                      R <

--                                        <     Cout

--                              R     R   |     4.7uF

--  carrier_o(1) o------------/\/\--/\/\--.-----|(-------o AC coupled, Modulated Output

--    (MSB)                               |

--                          Cfilt         |

--                          0.01uF        |

--  cap_gnd_o(0) o------------|(----------.

--                                        |

--                          Cfilt         |

--                          0.01uF        |

--  cap_gnd_o(1) o------------|(----------.

--                                        |

--                          Cfilt         |

--                          1300pF        |

--  cap_gnd_o(2) o------------|(----------.

--

--  In practice, R=270 ohms has been successfully used.

--  The Cfilt values are not exact, but the values shown worked well enough.

--

-- The two carrier signals are identical, except that the LSB is constantly driving

-- the heterodyne signal out, while the MSB is only driving the heterodyne signal

-- during times when the irig DC level pulse is high.  The cap_gnd_o outputs serves

-- to adjust the corner frequency of the RC low pass filter.  They are not pulsed

-- with any high frequency signals.  They simply apply ground or else high impedance,

-- thereby effectively bringing the Cfilt capacitors in and out of the circuit.

--

-- It is recommended to use the Cout capacitor in series with the output to provide

-- AC coupling of the signal, and some DC isolation for the FPGA.

--

-- This core uses a 1MHz clock enable pulse, to count the passage of time

-- and output a pulse stream which conforms to IRIG standard 200-04, for the

-- following IRIG formats:

--

--   First  letter: B (100 pps), A (1000 pps) or G (10000 pps)

--   First  digit : 0 = DC Level shift output (no modulation)

--   Second digit : 0 = No carrier

--   Third  digit : [0..7] (BCD plus combinations of Year, CF and SBS fields)

--

-- The core can generate its own 1 MHz clock enable by dividing the sys_clk

-- by an integer divisor.  If no integer divisor can be found, then then

-- perhaps an NCO should be used to come arbitrarily close to the desired

-- 1 MHz rate.  No NCO is currently provided, so if you run into this situation

-- you may have to buckle up, and start coding.

--

-- Keeping the time accurate over the longer term is accomplished by using

-- the pps_i input, a single pulse per second, one sys_clk in duration.

-- The pps_i input may be supplied by an external GPS module for accurate time,

-- although in the absence of GPS reference, the local system clock can be

-- used to create a somewhat less accurate reference.  An internal pps

-- generator creates a pps signal by counting one million of the 1 MHz clock

-- enable pulses, which is useful as a surrogate when there is no external pps

-- reference.  To use the external pps_i input, simply make "pps_ext_i" high.

--

-- All settings for the core are contained in read/write registers, which

-- have default values determined by generics.  In the case of a "code"

-- selection which includes straight binary seconds ("SBS"), the control

-- bits for the P8 and P9 portions of the output are not used, and the

-- internally calculated SBS field is used instead.

--

-- The year field also displaces control bits when it is selected.  The two

-- digit year is fully supported, and will increment properly at the end of

-- 23:59:59 on day 364. (No leap year).

--

-- For rates A and G, there is a tenths of a second BCD digit present in the

-- latter end of the P4 period.

--

-- For rate G, there is a hundredths of a second BCD digit present in the

-- former end of the P5 period.

--

-- If the year is desired, it can be placed in the proper position within

-- the control bits, as shown here...

--    Format B or A :

--      Year_1 (the most significant BCD digit) =>

--          control_1(0) & control_0(7 downto 5)

--          control_0(4) remains '0'

--      Year_0 (the least significant BCD digit) =>

--          control_0(3 downto 0)

--

--    Format G :

--      Year_1 (the most significant BCD digit) =>

--          control_2(1 downto 0) & control_1(7 downto 6)

--          control_1(5) remains '0'

--      Year_0 (the least significant BCD digit) =>

--          control_1(4 downto 1)

--

-- Bus interface writes to the registers cannot be given higher priority

-- than internal updates for timekeeping based on pps_i, since bus writes

-- only affect one value, while timekeeping can occasionally alter all of

-- them.  Thus corrupt and undesired behavior could result if bus writes

-- were to override the timekeeping update values.  Therefore, the ack_o

-- signal is used to ensure that the timekeeping is finished before bus

-- writes take place.

--

-- The registers are summarized as follows:

--

-- Address   Structure      Function

-- -------   ----------   ----------------------------------------

--   0x0     [**YY*DDD]    BCD Year, Day of Year (Day is 1..365 or 366)

--   0x1     [**HHMMSS]    BCD Hours, Minutes, Seconds. (*=unused nibble)

--   0x2     [CCCCCCCC]    Control Bits (31:0)

--   0x3     [**CCCCCC]    Control Bits (44:32)

--   0x4     (2:0)         Rate Setting (See Notes below)

--   0x5     (2:0)         Codes Used [ctrl,SBS,year]

--   0x6     (2:0)         Carrier Modulation Frequency

--

-- Notes:

--

--   Register 0x0 (Leap Year, Year, Day of Year)

--

--    Bit 28 controls the leap year setting:

--    This register currently has only a single bit for setting leap year

--    behavior.  When the leap year bit is set, the day field advances to 366

--    before rolling over back to 1.  When the bit is clear, the day field

--    to 1 after the 365 day value.  Note that the DDD field can be written

--    with values higher than 366, but it will immediately roll over.

--

--   Register 0x4 (Rate)

--    000 => (Use external input for Rate/Form/Carrier/Codes)*

--    001 => IRIG-B (1 second updates)

--    010 => IRIG-A (0.1 second updates)

--    011 => IRIG-G (0.01 second updates)

--    100 => NASA 36-bit (WWV) time code

--

--    The "rate_i" input is used along with the register setting, in such

--    a way that the register Rate value being zero, causes the "rate_i" and

--    "codes_i" inputs to be used.  If, however, the register Rate is set to

--    a non-zero value, then the external input is ignored.

--

--    When external rate input is used, a setting of "000" results

--    in IRIG-B (1 second updates.)  All other settings remain

--    as outlined above.

--

--   Register 0x5 (Codes)

--    Each bit position, when set, activates the use of a specific field

--    within the output, according to the form:

--

--       [ctrl,SBS,year]

--

--    Where ctrl = Control field

--           SBS = Straight Binary Seconds

--          year = Year field

--

--     If year and control are both selected, then the year is used in its 

--     appropriate spot, preventing the control bits there from being used.

--

--     For Rate "G", the hundredths of a second field occludes the first four

--     control bits, so that they are not used.  The hundredths of a second field

--     is encoded in the register area for "year" since year is not used in

--     Rate "G"

--

--   Register 0x6 (Carrier)

--   000 => No carrier (DC Level Shift)

--   001 => 100 Hz / 10 ms. resolution

--   010 => 1 kHz / 1 millisecond resolution

--   011 => 10 kHz / 100 microsecond resolution

--   100 => 100 kHz / 10 microsecond resolution

--

-- Internal logic takes the day, hour, minute and second values and derives

-- a value for the SBS field (Straight Binary Second).

--

-- The generics used as defaults for the registers are the full width of the

-- data bus.  However, only those bits which are actually present in the actual

-- registers are used.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.MATH_REAL.ALL;

library work;

use work.convert_pack.all;

entity irig_time_generator is

    generic (

      SYS_CLK_RATE : real := 40000000.0; -- Needed for carrier generation

      DEF_R_0 : unsigned(31 downto 0) := str2u("00100123",32);

      DEF_R_1 : unsigned(31 downto 0) := str2u("00000000",32);

      DEF_R_2 : unsigned(31 downto 0) := str2u("00000000",32);

      DEF_R_3 : unsigned(31 downto 0) := str2u("00000000",32);

      DEF_R_4 : unsigned(31 downto 0) := str2u("00000001",32);

      DEF_R_5 : unsigned(31 downto 0) := str2u("00000007",32);

      DEF_R_6 : unsigned(31 downto 0) := str2u("00000002",32);

      DEF_R_Z : unsigned(31 downto 0) := str2u("00000000",32)  -- Value returned for nonexistent registers

    );

    port (

      sys_rst_n   : in std_logic;

      sys_clk     : in std_logic;

      sys_clk_en  : in std_logic;

      -- Bus interface

      adr_i       : in  unsigned(3 downto 0);

      sel_i       : in  std_logic;

      we_i        : in  std_logic;

      dat_i       : in  unsigned(31 downto 0);

      dat_o       : out unsigned(31 downto 0);

      ack_o       : out std_logic;

      -- Pulse per second time reference

      pps_i       : in  std_logic;

      pps_ext_i   : in  std_logic;

      -- IRIG select inputs

      -- Active only when register 0xC set to zero.

      rate_i      : in  unsigned(2 downto 0); -- Rates    : 0,1=>B, 2=>A, 3=>G, 4=> NASA 36-bit

      carrier_i   : in  unsigned(2 downto 0); -- Carriers : 0=DCLS, 1=100Hz, 2=1kHz, 3=10kHz, 4=100kHz

      codes_i     : in  unsigned(2 downto 0); -- Codes    : (2)=> control, (1)=> SBS, (0)=> year

      -- serial IRIG time stream, LVTTL level output

      time_dcl_o  : out std_logic;

      cap_gnd_o   : out unsigned(2 downto 0);

      ref_o       : out std_logic;

      carrier_o   : out unsigned(1 downto 0)

    );

end irig_time_generator;

architecture beh of irig_time_generator is

-- Constants

constant DDS_WIDTH          : integer := 32;

constant INCREMENT_600KHZ   : unsigned(DDS_WIDTH-1 downto 0) := to_unsigned(integer(2.0**DDS_WIDTH/SYS_CLK_RATE*600000.0),DDS_WIDTH);

constant INCREMENT_510KHZ   : unsigned(DDS_WIDTH-1 downto 0) := to_unsigned(integer(2.0**DDS_WIDTH/SYS_CLK_RATE*510000.0),DDS_WIDTH);

constant INCREMENT_501KHZ   : unsigned(DDS_WIDTH-1 downto 0) := to_unsigned(integer(2.0**DDS_WIDTH/SYS_CLK_RATE*501000.0),DDS_WIDTH);

constant INCREMENT_500100HZ : unsigned(DDS_WIDTH-1 downto 0) := to_unsigned(integer(2.0**DDS_WIDTH/SYS_CLK_RATE*500100.0),DDS_WIDTH);

constant DIVISOR_PPS     : real :=  1000000.0;

constant DIVISOR_1MHZ    : real :=  SYS_CLK_RATE/DIVISOR_PPS;

constant DIV_COUNT_WIDTH : natural :=  bit_width(DIVISOR_1MHZ);

constant PPS_COUNT_WIDTH : natural :=  bit_width(DIVISOR_PPS);

constant SQF_BITS        : natural :=  4; -- square_fast frequency is Fsys_clk/2^(SQF_BITS+1)

-- Internal signal declarations

  -- State Machine

type FSM_STATE_TYPE is (RESET, IDLE, P0_REF, PR_REF, P0_DOUT, P1_PLUS_REF, P1_PLUS_DOUT);

signal fsm_state        : FSM_STATE_TYPE;

signal fsm_ack          : std_logic;

-- Related to SBS calculation

  -- SBS Calculation State

type SBS_STATE_TYPE is (RESET, IDLE, TIMEKEEPING_DELAY, SBS_10H, SBS_1H, SBS_10M, SBS_1M, SBS_10S);

signal sbs_state        : SBS_STATE_TYPE;

-- Related to Registers

signal leap_year        : std_logic;

signal secs_0           : unsigned(3 downto 0);

signal secs_1           : unsigned(2 downto 0);

signal mins_0           : unsigned(3 downto 0);

signal mins_1           : unsigned(2 downto 0);

signal hours_0          : unsigned(3 downto 0);

signal hours_1          : unsigned(1 downto 0);

signal days_0           : unsigned(3 downto 0);

signal days_1           : unsigned(3 downto 0);

signal days_2           : unsigned(1 downto 0);

signal years_0          : unsigned(3 downto 0);

signal years_1          : unsigned(3 downto 0);

signal tenths           : unsigned(3 downto 0);

signal hundredths       : unsigned(3 downto 0);

signal micros           : unsigned(13 downto 0); -- Microsecond count

signal sbs              : unsigned(16 downto 0);

signal sbs_next         : unsigned(16 downto 0);

signal sbs_add_count    : unsigned(3 downto 0);

signal control          : unsigned(44 downto 0);

signal reg_rate         : unsigned(2 downto 0);

signal reg_carrier      : unsigned(2 downto 0);

signal reg_codes        : unsigned(2 downto 0);

signal irig_rate        : unsigned(2 downto 0);

signal irig_carrier     : unsigned(2 downto 0);

signal irig_codes       : unsigned(2 downto 0);

-- Related to pulse per second and 1MHz clock enable

signal clk_en_1mhz      : std_logic;

signal clk_div_count    : unsigned(DIV_COUNT_WIDTH-1 downto 0);

signal pps              : std_logic;

signal pps_local        : std_logic;

signal pps_count        : unsigned(PPS_COUNT_WIDTH-1 downto 0);

-- Related to generation of the output pulse stream

signal pulse_clk_count  : unsigned(9 downto 0); -- Divides by factor of 10, 100 or 1000

signal pulse_clk_en     : std_logic;

signal pulse_sub_count  : unsigned(3 downto 0); -- Advances when pulse_clk_en=1

signal sub_count_nine   : std_logic;

signal p_count          : unsigned(3 downto 0); -- Advances when sub_count=9 and pulse_sr_count=9

signal cycle_count      : unsigned(6 downto 0); -- Counts output cycles during the current second.

signal pulse_sr         : unsigned(8 downto 0);

signal pulse_sr_count   : unsigned(3 downto 0); -- Advances when sub_count=9

signal sr_load_bus      : unsigned(8 downto 0);

signal p0               : unsigned(8 downto 0); -- sr load value

signal p1               : unsigned(8 downto 0); -- sr load value

signal p2               : unsigned(8 downto 0); -- sr load value

signal p3               : unsigned(8 downto 0); -- sr load value

signal p4               : unsigned(8 downto 0); -- sr load value

signal p5               : unsigned(8 downto 0); -- sr load value

signal p6               : unsigned(8 downto 0); -- sr load value

signal p7               : unsigned(8 downto 0); -- sr load value

signal p8               : unsigned(8 downto 0); -- sr load value

signal p9               : unsigned(8 downto 0); -- sr load value

signal pulse_extent     : unsigned(3 downto 0);

signal time_pulses      : std_logic;

-- Related to generation of the sinewave carrier

signal dds_sync          : std_logic;

signal sqf_count         : unsigned(SQF_BITS-1 downto 0);

signal square_fast       : std_logic;

signal square_500khz     : std_logic;

signal heterodyne        : std_logic;

signal modulated_carrier : std_logic;

signal phase_dds         : unsigned(DDS_WIDTH-1 downto 0);

signal increment_dds     : unsigned(DDS_WIDTH-1 downto 0);

-----------------------------------------------------------------------------

begin

  --------------------------

  -- Clock enable generation

  -- This creates output pulses at 1MHz rate, for use by the IRIG time generator

  -- It also creates a 1 Hz "pps" signal in lieu of such a signal from a GPS reference.

  clk_en_1mhz_proc: Process(sys_rst_n,sys_clk)

  begin

    if (sys_rst_n = '0') then

      clk_div_count <= (others=>'0');

--      pps_count     <= (others=>'0');

      pps_count     <= to_unsigned(integer(DIVISOR_PPS-200.0),pps_count'length); -- For better simulation

      clk_en_1mhz   <= '0';

      pps_local     <= '0';

    elsif (sys_clk'event AND sys_clk='1') then

      if (sys_clk_en='1') then

        clk_en_1mhz <= '0';  -- Default

        pps_local   <= '0';  -- Default

        if (clk_div_count=integer(DIVISOR_1MHZ-1.0)) then

          clk_div_count <= (others=>'0');

          clk_en_1mhz   <= '1';

          if (pps_count=integer(DIVISOR_PPS-1.0)) then

            pps_count   <= (others=>'0');

            pps_local   <= '1';

          else

            pps_count   <= pps_count+1;

          end if;

        else

          clk_div_count <= clk_div_count+1;

        end if;

      end if; -- sys_clk_en

    end if; -- sys_clk

  end process;

-- Select which PPS signal to use

pps <= pps_local when pps_ext_i='0' else pps_i;

-- Select which settings to use

irig_rate    <= reg_rate    when (reg_rate/=0) else rate_i;

irig_carrier <= reg_carrier when (reg_rate/=0) else carrier_i;

irig_codes   <= reg_codes   when (reg_rate/=0) else codes_i;

-- Register read mux

with (adr_i) select

  dat_o <=

    "000" & leap_year & "0000" & years_1 & years_0 & "000000" & days_2 & days_1 & days_0 when "0000",  --  "0";

    "0000000000" & hours_1 & hours_0 & "0" & mins_1 & mins_0 & "0" & secs_1 & secs_0     when "0001",  --  "1";

    control(31 downto 0)                                                                 when "0010",  --  "2";

    "0000000000000000000" & control(44 downto 32)                                        when "0011",  --  "3";

    u_resize(reg_rate,32)                                                                when "0100",  --  "4";

    u_resize(reg_carrier,32)                                                             when "0101",  --  "5";

    u_resize(reg_codes,32)                                                               when "0110",  --  "6";

    DEF_R_Z                                                                              when others;   -- Default

-- Create acknowledge signal

ack_o <= '1' when (sel_i='1' and we_i='0') else fsm_ack;

  --------------------------

  -- Heterodyning Signals

  -- The idea here is to multiply or "mix" two "squarewave" sequences

  -- by using an XOR gate, to produce a sum and difference frequency.

  -- The sum frequency should be easily filtered out by an RC filter

  -- external to the FPGA.

  proc_square: Process(sys_rst_n,sys_clk)

  begin

    if (sys_rst_n = '0') then

      square_fast <= '0';

      sqf_count   <= (others=>'0');

    elsif (sys_clk'event AND sys_clk='1') then

      if (sys_clk_en='1') then

        sqf_count <= sqf_count+1;

        if (sqf_count=0) then

          square_fast <= not square_fast;

        end if;

      end if;

    end if;

  end process;

  proc_square_500khz: Process(sys_rst_n,sys_clk)

  begin

    if (sys_rst_n = '0') then

      square_500khz <= '0';

    elsif (sys_clk'event AND sys_clk='1') then

      if (sys_clk_en='1') then

        if (clk_en_1mhz='1') then

          square_500khz <= not square_500khz;

        end if;

      end if;

    end if;

  end process;

  proc_dds: Process(sys_rst_n,sys_clk)

  begin

    if (sys_rst_n = '0') then

      phase_dds <= (phase_dds'length-2=>'1',others=>'0'); -- Set to 1/4 phase point (sinewave "zero" output)

    elsif (sys_clk'event AND sys_clk='1') then

      if (sys_clk_en='1') then

        if (dds_sync='1') then

          phase_dds <= (phase_dds'length-2=>'1',others=>'0'); -- Set to 1/4 phase point (sinewave "zero" output)

        else

          phase_dds <= phase_dds + increment_dds;

        end if;

      end if; -- sys_clk_en

    end if; -- sys_clk

  end process;

  increment_dds <= INCREMENT_600KHZ when irig_carrier=4 else

                   INCREMENT_510KHZ when irig_carrier=3 else

                   INCREMENT_501KHZ when irig_carrier=2 else

                   INCREMENT_500100HZ;

  heterodyne <= square_500khz xor phase_dds(31); -- A sort of digital signal multiplication

  modulated_carrier <= heterodyne when time_pulses='1' else square_fast; -- Output midpoint when pulse is low

  carrier_o(0) <= '0' when irig_carrier=0 else heterodyne;

  carrier_o(1) <= time_pulses when irig_carrier=0 else

                  modulated_carrier;

  ref_o        <= '0' when irig_carrier=0 else square_fast; -- Used as a "midpoint" voltage reference

  --------------------------

  -- Setting for output filter capacitor.

  -- The idea here is to ground the particular capacitor needed to

  -- low pass filter the output.  Three different outputs are provided.

  cap_gnd_o     <= "ZZZ" when irig_carrier=0 or irig_carrier=1 else

                   "Z00" when irig_carrier=2 else  -- Two capacitors in parallel

                   "Z0Z" when irig_carrier=3 else

                   "0ZZ";

-- This process is where the different BCD values are compiled into

-- a "straight binary seconds" (SBS) field.

-- The calculations are done in a multiply accumulate fashion (MAC)

-- wherein the multiply is implemented as a series of additions.

-- An SBS accumulator stores the intermediate calculation total,

-- while a state variable tracks the current stage of calculation,

-- beginning at "tens of hours" and finishing at "seconds."

-- All the adds performed here are unsigned...

sbs_proc : process(sys_clk,sys_rst_n)

begin

  if (sys_rst_n='0') then

    sbs_state <= RESET;

    sbs <= (others=>'0');

    sbs_next <= (others=>'0');

    sbs_add_count <= (others=>'0');

  elsif (sys_clk'event and sys_clk='1') then

    if (sys_clk_en='1') then

      case (sbs_state) is

        when RESET =>