Subversion Repositories irig_regenerator

--------------------------------------------------------------------------

-- Package of Pulse Width Modulation (PWM) Components

--

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

package pwm_pack is

component pwm_simple

  generic (

    PERIOD     : natural := 800; -- Number of sys_clk_en per PWM cycle

    COUNT_BITS : natural := 10   -- LOG2(PERIOD)

  );

  port (

    -- Reset, System Clock and Clock Enable

    sys_rst_n  : in  std_logic;

    sys_clk    : in  std_logic;

    sys_clk_en : in  std_logic;

    -- Input Data

    dat_i      : in  signed((COUNT_BITS-1) downto 0);

    -- Output Signal

    dat_o      : out std_logic

  );

end component;

component pwm_unsigned

  generic (

    PERIOD     : natural := 800; -- Number of sys_clk_en per PWM cycle

    COUNT_BITS : natural := 10   -- LOG2(PERIOD)

  );

  port (

    -- Reset, System Clock and Clock Enable

    sys_rst_n  : in  std_logic;

    sys_clk    : in  std_logic;

    sys_clk_en : in  std_logic;

    -- Input Data

    dat_i      : in  unsigned((COUNT_BITS-1) downto 0);

    -- Output Signal

    dat_o      : out std_logic

  );

end component;

end pwm_pack;

package body pwm_pack is

end pwm_pack;

-------------------------------------------------------------------------------

-- Simple PWM unit

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Update: Oct. 14, 2013 Added this header.  Created description and code.

--

-- Description

-------------------------------------------------------------------------------

-- This is a quite simple pulse width modulator (PWM) unit.  It contains a

-- counter which increments at the sys_clk_en rate.  When the counter value

-- exceeds the value of the dat_i input, the output is driven high.  When

-- the counter reaches its terminal value, the counter resets and the output

-- is driven low once again.

--

-- In order to use a signed input with an unsigned up-counter, the dat_i

-- input is first converted into an unsigned quantity.  This is done by

-- adding 2**(COUNT_BITS-1) to the input.

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity pwm_simple is

  generic (

    PERIOD     : natural := 800; -- Number of sys_clk_en per PWM cycle

    COUNT_BITS : natural := 10   -- LOG2(PERIOD)

  );

  port (

    -- Reset, System Clock and Clock Enable

    sys_rst_n  : in  std_logic;

    sys_clk    : in  std_logic;

    sys_clk_en : in  std_logic;

    -- Input Data

    dat_i      : in  signed((COUNT_BITS-1) downto 0);

    -- Output Signal

    dat_o      : out std_logic

  );

end pwm_simple;

architecture beh1 of pwm_simple is

-- Constants

  constant adjustment : unsigned(COUNT_BITS-1 downto 0) := to_unsigned(2**(COUNT_BITS-1),COUNT_BITS);

-- Signals

  signal count        : unsigned(COUNT_BITS-1 downto 0);

  signal dac_val      : unsigned(COUNT_BITS-1 downto 0);

-----------------------------------------------------------------------------

begin  -- beh1

dac_val <= adjustment + unsigned(dat_i);

  process (sys_clk, sys_rst_n)

  begin  -- process

    if sys_rst_n='0' then -- asynchronous reset (active low)

      count <= to_unsigned(1,count'length);

      dat_o <= '0';

    elsif sys_clk'event and sys_clk='1' then -- rising clock edge

      if (sys_clk_en='1') then

        count <= count+1;

        if (count=PERIOD) then

          count <= to_unsigned(1,count'length);

        end if;

        if (count>=dac_val) then

          dat_o <= '1';

        else

          dat_o <= '0';

        end if;

      end if;

    end if;

  end process;

end beh1;

-------------------------------------------------------------------------------

-- Simple PWM unit, unsigned version

-------------------------------------------------------------------------------

--

-- Author: John Clayton

-- Update: Oct. 14, 2013 Copied pwm_simple, and modified it slightly.

--

-- Description

-------------------------------------------------------------------------------

-- This is a quite simple pulse width modulator (PWM) unit.  It contains a

-- counter which increments at the sys_clk_en rate.  When the counter value

-- exceeds the value of the dat_i input, the output is driven high.  When

-- the counter reaches its terminal value, the counter resets and the output

-- is driven low once again.

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity pwm_unsigned is

  generic (

    PERIOD     : natural := 800; -- Number of sys_clk_en per PWM cycle

    COUNT_BITS : natural := 10   -- LOG2(PERIOD)

  );

  port (

    -- Reset, System Clock and Clock Enable

    sys_rst_n  : in  std_logic;

    sys_clk    : in  std_logic;

    sys_clk_en : in  std_logic;

    -- Input Data

    dat_i      : in  unsigned(COUNT_BITS-1 downto 0);

    -- Output Signal

    dat_o      : out std_logic

  );

end pwm_unsigned;

architecture beh1 of pwm_unsigned is

-- Constants

-- Signals

  signal count : unsigned(COUNT_BITS-1 downto 0);

-----------------------------------------------------------------------------

begin  -- beh1

  process (sys_clk, sys_rst_n)

  begin  -- process

    if sys_rst_n='0' then -- asynchronous reset (active low)

      count <= to_unsigned(0,count'length);

      dat_o <= '0';

    elsif sys_clk'event and sys_clk='1' then -- rising clock edge

      if (sys_clk_en='1') then

        count <= count+1;

        if (count=PERIOD-1) then

          count <= to_unsigned(1,count'length);

        end if;

        if (count>=dat_i) then

          dat_o <= '1';

        else

          dat_o <= '0';

        end if;

      end if;

    end if;

  end process;

end beh1;