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acapola |
/*
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Author: Sebastien Riou (acapola)
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Creation date: 23:57:02 08/31/2010
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Counter.v $
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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/*
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A counter with increment and clear operation
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*/
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module Counter
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#(//parameters to override
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parameter DIVIDER_WIDTH = 16,
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parameter WIDTH = 8,
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parameter WIDTH_INIT = 1
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)
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(
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output reg [WIDTH-1:0] counter,
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acapola |
output wire earlyMatch,
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acapola |
output reg match,
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acapola |
output wire dividedClk,
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input wire [DIVIDER_WIDTH-1:0] divider, // clock divide factor
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input wire [WIDTH-1:0] compare,
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input wire inc,
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input wire clear,
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input wire [WIDTH_INIT-1:0] initVal,
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input wire clk,
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input wire nReset
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acapola |
);
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wire divideBy1;
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wire divMatch;
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wire divRisingMatch;
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wire divFallingMatch;
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ClkDivider #(.DIVIDER_WIDTH(DIVIDER_WIDTH))
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clkDivider(
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.nReset(nReset),
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.clk(clk),
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.divider(divider),
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.dividedClk(dividedClk),
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.divideBy1(divideBy1),
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.match(divMatch),
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.risingMatch(divRisingMatch),
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.fallingMatch(divFallingMatch)
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);
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wire [WIDTH-1:0] nextCounter = counter+1'b1;
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wire doInc = divideBy1 ? inc :inc & divRisingMatch;
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wire doEarlyMatch = divideBy1 ? (compare == nextCounter) : (compare == counter) & divRisingMatch;
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reg earlyMatchReg;
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assign earlyMatch = divideBy1 ? earlyMatchReg : doEarlyMatch;
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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counter <= 0;//initVal;
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earlyMatchReg <= 0;
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match <= 0;
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end else begin
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if(clear) begin
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counter <= initVal;
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end else if(doInc) begin
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if(compare == counter)
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counter <= initVal;
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else
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counter <= nextCounter;
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end
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if(doEarlyMatch)
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earlyMatchReg <= 1;
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else begin
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earlyMatchReg <= 0;
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end
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match <= divideBy1 ? earlyMatchReg : doEarlyMatch;
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end
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end
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endmodule
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11 |
acapola |
`default_nettype wire
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