1 |
11 |
acapola |
/*
|
2 |
|
|
Author: Sebastien Riou (acapola)
|
3 |
|
|
Creation date: 17:16:40 01/09/2011
|
4 |
|
|
|
5 |
|
|
$LastChangedDate: 2011-02-13 16:20:10 +0100 (Sun, 13 Feb 2011) $
|
6 |
|
|
$LastChangedBy: acapola $
|
7 |
|
|
$LastChangedRevision: 15 $
|
8 |
|
|
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
|
9 |
|
|
|
10 |
|
|
This file is under the BSD licence:
|
11 |
|
|
Copyright (c) 2011, Sebastien Riou
|
12 |
|
|
|
13 |
|
|
All rights reserved.
|
14 |
|
|
|
15 |
|
|
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
|
16 |
|
|
|
17 |
|
|
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
|
18 |
|
|
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
|
19 |
|
|
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
|
20 |
|
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
21 |
|
|
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
22 |
|
|
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
23 |
|
|
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
|
24 |
|
|
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
25 |
|
|
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
26 |
|
|
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
27 |
|
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
28 |
|
|
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
29 |
|
|
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
30 |
|
|
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
31 |
|
|
*/
|
32 |
4 |
acapola |
`default_nettype none
|
33 |
2 |
acapola |
module Iso7816_3_Master(
|
34 |
4 |
acapola |
input wire nReset,
|
35 |
|
|
input wire clk,
|
36 |
|
|
input wire [15:0] clkPerCycle,//not supported yet
|
37 |
|
|
input wire startActivation,//Starts activation sequence
|
38 |
|
|
input wire startDeactivation,//Starts deactivation sequence
|
39 |
|
|
input wire [7:0] dataIn,
|
40 |
|
|
input wire nWeDataIn,
|
41 |
7 |
acapola |
input wire [12:0] cyclesPerEtu,
|
42 |
15 |
acapola |
output reg [7:0] dataOut,
|
43 |
4 |
acapola |
input wire nCsDataOut,
|
44 |
|
|
output wire [7:0] statusOut,
|
45 |
|
|
input wire nCsStatusOut,
|
46 |
2 |
acapola |
output reg isActivated,//set to high by activation sequence, set to low by deactivation sequence
|
47 |
4 |
acapola |
output wire useIndirectConvention,
|
48 |
|
|
output wire tsError,//high if TS character is wrong
|
49 |
|
|
output wire tsReceived,
|
50 |
|
|
output wire atrIsEarly,//high if TS received before 400 cycles after reset release
|
51 |
|
|
output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
|
52 |
2 |
acapola |
//ISO7816 signals
|
53 |
4 |
acapola |
inout wire isoSio,
|
54 |
|
|
output wire isoClk,
|
55 |
3 |
acapola |
output reg isoReset,
|
56 |
|
|
output reg isoVdd
|
57 |
2 |
acapola |
);
|
58 |
|
|
|
59 |
3 |
acapola |
wire txRun,txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull;
|
60 |
|
|
assign {txRun, txPending, rxRun, rxStartBit, isTx, overrunErrorFlag, frameErrorFlag, bufferFull} = statusOut;
|
61 |
|
|
|
62 |
4 |
acapola |
wire serialOut;
|
63 |
|
|
assign isoSio = isTx ? serialOut : 1'bz;
|
64 |
|
|
pullup(isoSio);
|
65 |
3 |
acapola |
wire comClk;
|
66 |
2 |
acapola |
|
67 |
15 |
acapola |
wire stopBit2=1'b1;//0: 1 stop bit, 1: 2 stop bits
|
68 |
|
|
wire msbFirst = useIndirectConvention;//if 1, bits order is: startBit, b7, b6, b5...b0, parity
|
69 |
|
|
wire oddParity = 1'b0;//if 1, parity bit is such that data+parity have an odd number of 1
|
70 |
|
|
wire sioHighValue = ~useIndirectConvention;//apply only to data bits
|
71 |
|
|
|
72 |
|
|
wire [7:0] uart_dataOut;
|
73 |
|
|
wire [7:0] uart_dataIn = sioHighValue ? dataIn : ~dataIn;
|
74 |
|
|
always @(*) dataOut = sioHighValue ? uart_dataOut : ~uart_dataOut;
|
75 |
|
|
|
76 |
|
|
|
77 |
7 |
acapola |
HalfDuplexUartIf #(
|
78 |
|
|
.DIVIDER_WIDTH(1'b1),
|
79 |
|
|
.CLOCK_PER_BIT_WIDTH(4'd13)
|
80 |
|
|
)
|
81 |
|
|
uart (
|
82 |
2 |
acapola |
.nReset(nReset),
|
83 |
|
|
.clk(clk),
|
84 |
|
|
.clkPerCycle(1'b0),
|
85 |
15 |
acapola |
.dataIn(uart_dataIn),
|
86 |
2 |
acapola |
.nWeDataIn(nWeDataIn),
|
87 |
7 |
acapola |
.clocksPerBit(cyclesPerEtu),
|
88 |
15 |
acapola |
.stopBit2(stopBit2),
|
89 |
|
|
.oddParity(oddParity),
|
90 |
|
|
.msbFirst(msbFirst),
|
91 |
|
|
.dataOut(uart_dataOut),
|
92 |
2 |
acapola |
.nCsDataOut(nCsDataOut),
|
93 |
|
|
.statusOut(statusOut),
|
94 |
|
|
.nCsStatusOut(nCsStatusOut),
|
95 |
|
|
.serialIn(isoSio),
|
96 |
|
|
.serialOut(serialOut),
|
97 |
|
|
.comClk(comClk)
|
98 |
|
|
);
|
99 |
|
|
|
100 |
|
|
reg isoClkEn;
|
101 |
|
|
assign isoClk = isoClkEn ? comClk : 1'b0;
|
102 |
|
|
|
103 |
5 |
acapola |
reg [16:0] resetCnt;
|
104 |
|
|
reg waitTs;
|
105 |
|
|
assign tsReceived = ~waitTs;
|
106 |
|
|
reg [7:0] ts;
|
107 |
|
|
assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
|
108 |
|
|
assign atrIsLate = resetCnt>(16'h100+16'd40000);
|
109 |
|
|
assign useIndirectConvention = ~waitTs & (ts==8'h3F);
|
110 |
|
|
assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
|
111 |
|
|
always @(posedge comClk, negedge nReset) begin
|
112 |
|
|
if(~nReset) begin
|
113 |
|
|
isoClkEn <= 1'b0;
|
114 |
|
|
resetCnt<=16'b0;
|
115 |
|
|
waitTs<=1'b1;
|
116 |
|
|
isoReset <= 1'b0;
|
117 |
|
|
isoVdd <= 1'b0;
|
118 |
|
|
isActivated <= 1'b0;
|
119 |
|
|
end else if(isActivated) begin
|
120 |
|
|
if(waitTs) begin
|
121 |
|
|
if(statusOut[0]) begin
|
122 |
|
|
waitTs<=1'b0;
|
123 |
15 |
acapola |
case(dataOut)
|
124 |
|
|
8'h3B: ts<=dataOut;
|
125 |
|
|
8'h03: ts<=8'h3F;
|
126 |
|
|
default: ts<=dataOut;
|
127 |
|
|
endcase
|
128 |
5 |
acapola |
end
|
129 |
|
|
resetCnt<=resetCnt+1;
|
130 |
|
|
end
|
131 |
|
|
if(startDeactivation) begin
|
132 |
|
|
isoVdd <= 1'b0;
|
133 |
2 |
acapola |
isoClkEn <= 1'b0;
|
134 |
5 |
acapola |
isoReset <= 1'b0;
|
135 |
2 |
acapola |
resetCnt<=16'b0;
|
136 |
|
|
isActivated <= 1'b0;
|
137 |
5 |
acapola |
end
|
138 |
|
|
end else begin
|
139 |
|
|
if(startActivation) begin
|
140 |
|
|
waitTs <= 1'b1;
|
141 |
|
|
isoVdd <= 1'b1;
|
142 |
|
|
isoClkEn <= 1'b1;
|
143 |
|
|
if(16'h100 == resetCnt) begin
|
144 |
|
|
isActivated <=1'b1;
|
145 |
|
|
isoReset <=1'b1;
|
146 |
|
|
end else
|
147 |
|
|
resetCnt<=resetCnt + 1;
|
148 |
2 |
acapola |
end else begin
|
149 |
5 |
acapola |
resetCnt<=16'b0;
|
150 |
2 |
acapola |
end
|
151 |
|
|
end
|
152 |
5 |
acapola |
end
|
153 |
2 |
acapola |
endmodule
|
154 |
11 |
acapola |
`default_nettype wire
|