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/*
Author: Sebastien Riou (acapola)
Creation date: 23:57:02 08/31/2010
 
$LastChangedDate: 2011-02-14 15:11:43 +0100 (Mon, 14 Feb 2011) $
$LastChangedBy: acapola $
$LastChangedRevision: 16 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCore.v $
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
 
module RxCore
#(//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13,     //allow to support default speed of ISO7816
parameter PRECISE_STOP_BIT = 0, //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit
//default conventions (nothing to do with iso7816's convention, this is configured dynamically by the inputs)
parameter START_BIT = 1'b0,
parameter STOP_BIT1 = 1'b1,
parameter STOP_BIT2 = 1'b1
)
(
   output reg [7:0] dataOut,
   output reg overrunErrorFlag, //new data has been received before dataOut was read
   output reg dataOutReadyFlag, //new data available
   output reg frameErrorFlag,           //bad parity or bad stop bits
   output reg endOfRx,                          //one cycle pulse: 1 during last cycle of last stop bit
   output reg run,                                      //rx is definitely started, one of the three flag will be set
   output wire startBit,                        //rx is started, but we don't know yet if real rx or just a glitch
        output reg stopBit,                             //rx is over but still in stop bits
        input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
        input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
        input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
   input wire msbFirst,  //if 1, bits order is: startBit, b7, b6, b5...b0, parity
        input wire ackFlags,
        input wire serialIn,
        input wire clk,
   input wire nReset,
        //to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
        output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
        output reg bitClocksCounterInc,
        output reg bitClocksCounterClear,
        output wire bitClocksCounterInitVal,
   input wire bitClocksCounterEarlyMatch,
        input wire bitClocksCounterMatch,
        input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter
    );
 
//constant definition for states
localparam IDLE_STATE =         3'b000;
localparam START_STATE =        3'b001;
localparam DATA_STATE =         3'b011;
localparam PARITY_STATE =       3'b010;
localparam STOP1_STATE =        3'b110;
localparam STOP2_STATE =        3'b111;
localparam END_STATE =          3'b101;
localparam END2_STATE =    3'b100;
 
localparam IDLE_BIT = ~START_BIT;
 
reg [2:0] nextState;
 
reg [2:0] bitCounter;
wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
reg parityBit;
 
wire internalIn;
wire parityError;
 
assign startBit = (nextState == START_STATE);
//assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
assign internalIn = serialIn;
assign parityError= parityBit ^ internalIn ^ 1'b1;
reg flagsSet;
 
assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
always @(nextState, clocksPerBit, run, bitClocksCounterMatch) begin
        case(nextState)
                IDLE_STATE: begin
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterInc = run & ~bitClocksCounterMatch;//stop when reach 0
                        bitClocksCounterClear = ~run;
                end
                START_STATE: begin
                        bitClocksCounterCompare = (clocksPerBit/2);
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                end
                STOP2_STATE: begin
         //make the rx operation is one cycle shorter, 
         //since we detect the start bit at least one cycle later it starts.
                        bitClocksCounterCompare = clocksPerBit-1;
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                end
                default: begin
                        bitClocksCounterCompare = clocksPerBit;
                        bitClocksCounterInc = 1;
                        bitClocksCounterClear = 0;
                end
        endcase
end
 
always @(posedge clk, negedge nReset) begin
        if(~nReset) begin
                nextState <= #1 IDLE_STATE;
                bitCounter <= #1 0;
                parityBit <= #1 0;
                overrunErrorFlag <= #1 0;
                dataOutReadyFlag <= #1 0;
                frameErrorFlag <= #1 0;
                run <= #1 0;
      endOfRx <= #1 0;
                stopBit<= #1 0;
        end else begin
                case(nextState)
                        IDLE_STATE: begin
                                if(bitClocksCounterEarlyMatch)
               endOfRx <= #1 1'b1;
            if(bitClocksCounterMatch) begin
               endOfRx <= #1 0;
                                        stopBit <= #1 0;
                                end
            if(ackFlags) begin
                                        //overrunErrorFlag is auto cleared at PARITY_STATE
                                        //meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                if(START_BIT == internalIn) begin
                                        if(frameErrorFlag | overrunErrorFlag) begin
                                                //wait clear from outside
                                                if(bitClocksCounterMatch) begin
                     //endOfRx <= #1 0;
                                                        run <= #1 0;
                  end
                                        end else begin
                                                parityBit <= #1 ~oddParity;
                                                run <= #1 0;
                                                nextState <= #1 START_STATE;
                                        end
                                end else begin
                                        if(bitClocksCounterMatch) begin
                  //endOfRx <= #1 0;
                                                run <= #1 0;
               end
                                end
                        end
                        START_STATE: begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                if(bitClocksCounterMatch) begin
                                        if(START_BIT != internalIn) begin
                                                nextState <= #1 IDLE_STATE;
                                        end else begin
                                                run <= #1 1;
                                                nextState <= #1 DATA_STATE;
                                        end
                                end
                        end
                        DATA_STATE: begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                                if(bitClocksCounterMatch) begin
                                        if(dataOutReadyFlag) begin
                                                overrunErrorFlag <= #1 1;
                                        end else
                                                dataOut[bitIndex] <= #1 internalIn;
                                        parityBit <= #1 parityBit ^ internalIn;
                                        bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
                                        if(bitCounter == 7)
                                                nextState <= #1 PARITY_STATE;
                                end
                        end
                        PARITY_STATE: begin
                                if(bitClocksCounterMatch) begin
                                        if(~overrunErrorFlag) begin
                                                frameErrorFlag <= #1 parityError;
                                                dataOutReadyFlag <= #1 ~parityError;
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                        end
                                        flagsSet=1;
                                        if(PRECISE_STOP_BIT==0) stopBit <= #1 1;
                                        if(stopBit2)
                                                nextState <= #1 STOP1_STATE;
                                        else
                                                nextState <= #1 STOP2_STATE;
                                end else if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                        frameErrorFlag <= #1 0;
                                end
                        end
                        STOP1_STATE: begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                end
                                if(bitClocksCounterMatch) begin
                                        if(STOP_BIT1 != internalIn) begin
                                                frameErrorFlag <= #1 parityError;
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                        end
                                        nextState <= #1 STOP2_STATE;
                                end else if(ackFlags) begin
                                        frameErrorFlag <= #1 0;
                                end
                                if(PRECISE_STOP_BIT!=0) begin
                                        if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
                                                stopBit <= #1 1;
                                        end
                                end
                        end
                        STOP2_STATE: begin
                                if(ackFlags) begin
                                        dataOutReadyFlag <= #1 0;
                                end
            if(bitClocksCounterMatch) begin
                                        if(STOP_BIT2 != internalIn) begin
                                                frameErrorFlag <= #1 1;
                                        end else if(ackFlags) begin
                                                frameErrorFlag <= #1 0;
                                        end
                                        nextState <= #1 IDLE_STATE;
                                end else if(ackFlags) begin
                                        frameErrorFlag <= #1 0;
                                end
                                if(PRECISE_STOP_BIT!=0) begin
                                        if(bitClocksCounter==(bitClocksCounterCompare/2)) begin
                                                stopBit <= #1 1;
                                        end
                                end
                        end
                        default: nextState <= #1 IDLE_STATE;
                endcase
        end
end
 
endmodule
`default_nettype wire

Line No.	Rev	Author	Line
1	11	acapola	`/*`
2			`Author: Sebastien Riou (acapola)`
3			`Creation date: 23:57:02 08/31/2010`
4
5			$LastChangedDate: 2011-02-14 15:11:43 +0100 (Mon, 14 Feb 2011) $
6			$LastChangedBy: acapola $
7			$LastChangedRevision: 16 $
8			$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/RxCore.v $
9
10			`This file is under the BSD licence:`
11			`Copyright (c) 2011, Sebastien Riou`
12
13			`All rights reserved.`
14
15			`Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:`
16
17			`Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.`
18			`Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.`
19			`The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.`
20			`THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS`
21			`"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT`
22			`LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR`
23			`A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR`
24			`CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
25			`EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
26			`PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR`
27			`PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF`
28			`LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
29			`NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
30			`SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
31			`*/`
32			`default_nettype none
33	4	acapola	`timescale 1ns / 1ps
34	11	acapola
35	16	acapola	`module RxCore`
36			`#(//parameters to override`
37			`parameter CLOCK_PER_BIT_WIDTH = 13, //allow to support default speed of ISO7816`
38			`parameter PRECISE_STOP_BIT = 0, //if 1, stopBit signal goes high exactly at start of stop bit instead of middle of parity bit`
39			`//default conventions (nothing to do with iso7816's convention, this is configured dynamically by the inputs)`
40			`parameter START_BIT = 1'b0,`
41			`parameter STOP_BIT1 = 1'b1,`
42			`parameter STOP_BIT2 = 1'b1`
43			`)`
44			`(`
45	2	acapola	`output reg [7:0] dataOut,`
46			`output reg overrunErrorFlag, //new data has been received before dataOut was read`
47			`output reg dataOutReadyFlag, //new data available`
48			`output reg frameErrorFlag, //bad parity or bad stop bits`
49			`output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit`
50			`output reg run, //rx is definitely started, one of the three flag will be set`
51	5	acapola	`output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch`
52	7	acapola	`output reg stopBit, //rx is over but still in stop bits`
53	4	acapola	`input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,`
54			`input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits`
55			`input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1`
56			`input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity`
57			`input wire ackFlags,`
58			`input wire serialIn,`
59			`input wire clk,`
60			`input wire nReset,`
61	2	acapola	`//to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)`
62			`output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,`
63			`output reg bitClocksCounterInc,`
64			`output reg bitClocksCounterClear,`
65	4	acapola	`output wire bitClocksCounterInitVal,`
66			`input wire bitClocksCounterEarlyMatch,`
67	7	acapola	`input wire bitClocksCounterMatch,`
68			`input wire [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounter`
69	2	acapola	`);`
70
71			`//constant definition for states`
72			`localparam IDLE_STATE = 3'b000;`
73			`localparam START_STATE = 3'b001;`
74			`localparam DATA_STATE = 3'b011;`
75			`localparam PARITY_STATE = 3'b010;`
76			`localparam STOP1_STATE = 3'b110;`
77			`localparam STOP2_STATE = 3'b111;`
78			`localparam END_STATE = 3'b101;`
79			`localparam END2_STATE = 3'b100;`
80
81			`localparam IDLE_BIT = ~START_BIT;`
82
83			`reg [2:0] nextState;`
84
85			`reg [2:0] bitCounter;`
86			`wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;`
87			`reg parityBit;`
88
89			`wire internalIn;`
90			`wire parityError;`
91
92	5	acapola	`assign startBit = (nextState == START_STATE);`
93	7	acapola	`//assign stopBit = (nextState == STOP1_STATE) \| (nextState == STOP2_STATE);`
94	2	acapola	`assign internalIn = serialIn;`
95			`assign parityError= parityBit ^ internalIn ^ 1'b1;`
96			`reg flagsSet;`
97
98			`assign bitClocksCounterInitVal=(nextState==IDLE_STATE);`
99			`always @(nextState, clocksPerBit, run, bitClocksCounterMatch) begin`
100			`case(nextState)`
101			`IDLE_STATE: begin`
102			`bitClocksCounterCompare = (clocksPerBit/2);`
103			`bitClocksCounterInc = run & ~bitClocksCounterMatch;//stop when reach 0`
104			`bitClocksCounterClear = ~run;`
105			`end`
106			`START_STATE: begin`
107			`bitClocksCounterCompare = (clocksPerBit/2);`
108			`bitClocksCounterInc = 1;`
109			`bitClocksCounterClear = 0;`
110			`end`
111			`STOP2_STATE: begin`
112			`//make the rx operation is one cycle shorter,`
113			`//since we detect the start bit at least one cycle later it starts.`
114			`bitClocksCounterCompare = clocksPerBit-1;`
115			`bitClocksCounterInc = 1;`
116			`bitClocksCounterClear = 0;`
117			`end`
118			`default: begin`
119			`bitClocksCounterCompare = clocksPerBit;`
120			`bitClocksCounterInc = 1;`
121			`bitClocksCounterClear = 0;`
122			`end`
123			`endcase`
124			`end`
125
126			`always @(posedge clk, negedge nReset) begin`
127			`if(~nReset) begin`
128			`nextState <= #1 IDLE_STATE;`
129			`bitCounter <= #1 0;`
130			`parityBit <= #1 0;`
131			`overrunErrorFlag <= #1 0;`
132			`dataOutReadyFlag <= #1 0;`
133			`frameErrorFlag <= #1 0;`
134			`run <= #1 0;`
135	7	acapola	`endOfRx <= #1 0;`
136			`stopBit<= #1 0;`
137	2	acapola	`end else begin`
138			`case(nextState)`
139			`IDLE_STATE: begin`
140			`if(bitClocksCounterEarlyMatch)`
141			`endOfRx <= #1 1'b1;`
142	7	acapola	`if(bitClocksCounterMatch) begin`
143			`endOfRx <= #1 0;`
144			`stopBit <= #1 0;`
145			`end`
146	2	acapola	`if(ackFlags) begin`
147			`//overrunErrorFlag is auto cleared at PARITY_STATE`
148			`//meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte`
149			`dataOutReadyFlag <= #1 0;`
150			`frameErrorFlag <= #1 0;`
151			`end`
152			`if(START_BIT == internalIn) begin`
153			`if(frameErrorFlag \| overrunErrorFlag) begin`
154			`//wait clear from outside`
155			`if(bitClocksCounterMatch) begin`
156			`//endOfRx <= #1 0;`
157			`run <= #1 0;`
158			`end`
159			`end else begin`
160	9	acapola	`parityBit <= #1 ~oddParity;`
161	2	acapola	`run <= #1 0;`
162			`nextState <= #1 START_STATE;`
163			`end`
164			`end else begin`
165			`if(bitClocksCounterMatch) begin`
166			`//endOfRx <= #1 0;`
167			`run <= #1 0;`
168			`end`
169			`end`
170			`end`
171			`START_STATE: begin`
172			`if(ackFlags) begin`
173			`dataOutReadyFlag <= #1 0;`
174			`frameErrorFlag <= #1 0;`
175			`end`
176			`if(bitClocksCounterMatch) begin`
177			`if(START_BIT != internalIn) begin`
178			`nextState <= #1 IDLE_STATE;`
179			`end else begin`
180			`run <= #1 1;`
181			`nextState <= #1 DATA_STATE;`
182			`end`
183			`end`
184			`end`
185			`DATA_STATE: begin`
186			`if(ackFlags) begin`
187			`dataOutReadyFlag <= #1 0;`
188			`frameErrorFlag <= #1 0;`
189			`end`
190			`if(bitClocksCounterMatch) begin`
191			`if(dataOutReadyFlag) begin`
192			`overrunErrorFlag <= #1 1;`
193			`end else`
194			`dataOut[bitIndex] <= #1 internalIn;`
195			`parityBit <= #1 parityBit ^ internalIn;`
196			`bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;`
197			`if(bitCounter == 7)`
198			`nextState <= #1 PARITY_STATE;`
199			`end`
200			`end`
201			`PARITY_STATE: begin`
202			`if(bitClocksCounterMatch) begin`
203			`if(~overrunErrorFlag) begin`
204			`frameErrorFlag <= #1 parityError;`
205			`dataOutReadyFlag <= #1 ~parityError;`
206			`end else if(ackFlags) begin`
207			`frameErrorFlag <= #1 0;`
208			`end`
209	7	acapola	`flagsSet=1;`
210			`if(PRECISE_STOP_BIT==0) stopBit <= #1 1;`
211	2	acapola	`if(stopBit2)`
212			`nextState <= #1 STOP1_STATE;`
213			`else`
214			`nextState <= #1 STOP2_STATE;`
215			`end else if(ackFlags) begin`
216			`dataOutReadyFlag <= #1 0;`
217			`frameErrorFlag <= #1 0;`
218			`end`
219			`end`
220			`STOP1_STATE: begin`
221			`if(ackFlags) begin`
222			`dataOutReadyFlag <= #1 0;`
223			`end`
224			`if(bitClocksCounterMatch) begin`
225			`if(STOP_BIT1 != internalIn) begin`
226			`frameErrorFlag <= #1 parityError;`
227			`end else if(ackFlags) begin`
228			`frameErrorFlag <= #1 0;`
229			`end`
230			`nextState <= #1 STOP2_STATE;`
231			`end else if(ackFlags) begin`
232			`frameErrorFlag <= #1 0;`
233	7	acapola	`end`
234			`if(PRECISE_STOP_BIT!=0) begin`
235			`if(bitClocksCounter==(bitClocksCounterCompare/2)) begin`
236			`stopBit <= #1 1;`
237			`end`
238	2	acapola	`end`
239			`end`
240			`STOP2_STATE: begin`
241			`if(ackFlags) begin`
242			`dataOutReadyFlag <= #1 0;`
243			`end`
244			`if(bitClocksCounterMatch) begin`
245			`if(STOP_BIT2 != internalIn) begin`
246			`frameErrorFlag <= #1 1;`
247			`end else if(ackFlags) begin`
248			`frameErrorFlag <= #1 0;`
249			`end`
250			`nextState <= #1 IDLE_STATE;`
251			`end else if(ackFlags) begin`
252			`frameErrorFlag <= #1 0;`
253	7	acapola	`end`
254			`if(PRECISE_STOP_BIT!=0) begin`
255			`if(bitClocksCounter==(bitClocksCounterCompare/2)) begin`
256			`stopBit <= #1 1;`
257			`end`
258	2	acapola	`end`
259			`end`
260			`default: nextState <= #1 IDLE_STATE;`
261			`endcase`
262			`end`
263			`end`
264
265			`endmodule`
266	11	acapola	`default_nettype wire

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