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acapola |
`timescale 1ns / 1ps
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`default_nettype none
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2 |
acapola |
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: Sebastien Riou
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//
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// Create Date: 23:57:02 08/31/2010
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// Design Name:
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// Module Name: RxCore
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module RxCore(
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output reg [7:0] dataOut,
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output reg overrunErrorFlag, //new data has been received before dataOut was read
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output reg dataOutReadyFlag, //new data available
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output reg frameErrorFlag, //bad parity or bad stop bits
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output reg endOfRx, //one cycle pulse: 1 during last cycle of last stop bit
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output reg run, //rx is definitely started, one of the three flag will be set
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acapola |
output wire startBit, //rx is started, but we don't know yet if real rx or just a glitch
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output wire stopBit, //rx is over but still in stop bits
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input wire [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
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input wire stopBit2,//0: 1 stop bit, 1: 2 stop bits
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input wire oddParity, //if 1, parity bit is such that data+parity have an odd number of 1
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input wire msbFirst, //if 1, bits order is: startBit, b7, b6, b5...b0, parity
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input wire ackFlags,
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input wire serialIn,
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input wire clk,
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input wire nReset,
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//to connect to an instance of Counter.v (see RxCoreSelfContained.v for example)
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output reg [CLOCK_PER_BIT_WIDTH-1:0] bitClocksCounterCompare,
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output reg bitClocksCounterInc,
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output reg bitClocksCounterClear,
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output wire bitClocksCounterInitVal,
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input wire bitClocksCounterEarlyMatch,
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input wire bitClocksCounterMatch
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acapola |
);
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//parameters to override
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parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816
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//default conventions
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parameter START_BIT = 1'b0;
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parameter STOP_BIT1 = 1'b1;
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parameter STOP_BIT2 = 1'b1;
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//constant definition for states
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localparam IDLE_STATE = 3'b000;
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localparam START_STATE = 3'b001;
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localparam DATA_STATE = 3'b011;
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localparam PARITY_STATE = 3'b010;
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localparam STOP1_STATE = 3'b110;
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localparam STOP2_STATE = 3'b111;
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localparam END_STATE = 3'b101;
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localparam END2_STATE = 3'b100;
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localparam IDLE_BIT = ~START_BIT;
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reg [2:0] nextState;
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reg [2:0] bitCounter;
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wire [2:0] bitIndex = msbFirst ? 7-bitCounter : bitCounter;
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reg parityBit;
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wire internalIn;
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wire parityError;
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assign startBit = (nextState == START_STATE);
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assign stopBit = (nextState == STOP1_STATE) | (nextState == STOP2_STATE);
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assign internalIn = serialIn;
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assign parityError= parityBit ^ internalIn ^ 1'b1;
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reg flagsSet;
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assign bitClocksCounterInitVal=(nextState==IDLE_STATE);
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always @(nextState, clocksPerBit, run, bitClocksCounterMatch) begin
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case(nextState)
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IDLE_STATE: begin
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bitClocksCounterCompare = (clocksPerBit/2);
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bitClocksCounterInc = run & ~bitClocksCounterMatch;//stop when reach 0
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bitClocksCounterClear = ~run;
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end
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START_STATE: begin
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bitClocksCounterCompare = (clocksPerBit/2);
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bitClocksCounterInc = 1;
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bitClocksCounterClear = 0;
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end
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STOP2_STATE: begin
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//make the rx operation is one cycle shorter,
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//since we detect the start bit at least one cycle later it starts.
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bitClocksCounterCompare = clocksPerBit-1;
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bitClocksCounterInc = 1;
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bitClocksCounterClear = 0;
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end
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default: begin
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bitClocksCounterCompare = clocksPerBit;
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bitClocksCounterInc = 1;
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bitClocksCounterClear = 0;
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end
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endcase
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end
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always @(posedge clk, negedge nReset) begin
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if(~nReset) begin
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nextState <= #1 IDLE_STATE;
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bitCounter <= #1 0;
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parityBit <= #1 0;
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overrunErrorFlag <= #1 0;
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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run <= #1 0;
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endOfRx <= #1 0;
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end else begin
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case(nextState)
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IDLE_STATE: begin
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if(bitClocksCounterEarlyMatch)
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endOfRx <= #1 1'b1;
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if(bitClocksCounterMatch)
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endOfRx <= #1 0;
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if(ackFlags) begin
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//overrunErrorFlag is auto cleared at PARITY_STATE
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//meanwhile, it prevent dataOutReadyFlag to be set by the termination of the lost byte
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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if(START_BIT == internalIn) begin
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if(frameErrorFlag | overrunErrorFlag) begin
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//wait clear from outside
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if(bitClocksCounterMatch) begin
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//endOfRx <= #1 0;
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run <= #1 0;
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end
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end else begin
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parityBit <= #1 oddParity;
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run <= #1 0;
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nextState <= #1 START_STATE;
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end
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end else begin
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if(bitClocksCounterMatch) begin
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//endOfRx <= #1 0;
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run <= #1 0;
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end
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end
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end
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START_STATE: begin
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if(ackFlags) begin
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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if(bitClocksCounterMatch) begin
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if(START_BIT != internalIn) begin
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nextState <= #1 IDLE_STATE;
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end else begin
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run <= #1 1;
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nextState <= #1 DATA_STATE;
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end
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end
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end
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DATA_STATE: begin
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if(ackFlags) begin
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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if(bitClocksCounterMatch) begin
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if(dataOutReadyFlag) begin
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overrunErrorFlag <= #1 1;
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end else
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dataOut[bitIndex] <= #1 internalIn;
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parityBit <= #1 parityBit ^ internalIn;
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bitCounter <= #1 (bitCounter + 1'b1) & 3'b111;
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if(bitCounter == 7)
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nextState <= #1 PARITY_STATE;
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end
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end
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PARITY_STATE: begin
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if(bitClocksCounterMatch) begin
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if(~overrunErrorFlag) begin
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frameErrorFlag <= #1 parityError;
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dataOutReadyFlag <= #1 ~parityError;
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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end
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flagsSet=1;
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if(stopBit2)
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nextState <= #1 STOP1_STATE;
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else
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nextState <= #1 STOP2_STATE;
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end else if(ackFlags) begin
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dataOutReadyFlag <= #1 0;
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frameErrorFlag <= #1 0;
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end
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end
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STOP1_STATE: begin
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if(ackFlags) begin
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dataOutReadyFlag <= #1 0;
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end
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if(bitClocksCounterMatch) begin
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if(STOP_BIT1 != internalIn) begin
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frameErrorFlag <= #1 parityError;
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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end
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nextState <= #1 STOP2_STATE;
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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end
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end
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STOP2_STATE: begin
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if(ackFlags) begin
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dataOutReadyFlag <= #1 0;
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end
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if(bitClocksCounterMatch) begin
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if(STOP_BIT2 != internalIn) begin
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frameErrorFlag <= #1 1;
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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end
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nextState <= #1 IDLE_STATE;
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end else if(ackFlags) begin
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frameErrorFlag <= #1 0;
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end
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end
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default: nextState <= #1 IDLE_STATE;
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endcase
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end
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end
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endmodule
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