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/*
Author: Sebastien Riou (acapola)
Creation date: 21:02:24 09/02/2010
 
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
$LastChangedBy: acapola $
$LastChangedRevision: 11 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/RxCoreTestBench.v $
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
`timescale 1ns / 1ps
 
module tb_RxCoreComparator(
        output reg implMismatch,
    output [7:0] dataOut,
    output overrunErrorFlag,    //new data has been received before dataOut was read
    output dataOutReadyFlag,    //new data available
    output frameErrorFlag,              //bad parity or bad stop bits
    output endOfRx,
    output run,                                 //rx is definitely started, one of the three flag will be set
    output startBit,                            //rx is started, but we don't know yet if real rx or just a glitch
         input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
         input stopBit2,//0: 1 stop bit, 1: 2 stop bits
         input ackFlags,
         input serialIn,
    input clk,
    input nReset
    );
 
parameter CLK_PERIOD = 10;//should be %2
//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
//invert the polarity of the output or not
parameter IN_POLARITY = 1'b0;
parameter PARITY_POLARITY = 1'b0;
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
wire [7:0] ref_dataOut;
wire ref_overrunErrorFlag;
wire ref_dataOutReadyFlag;
wire ref_frameErrorFlag;
wire ref_endOfRx;
wire ref_run;
wire ref_startBit;
 
RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (
                .dataOut(ref_dataOut),
                .overrunErrorFlag(ref_overrunErrorFlag),
                .dataOutReadyFlag(ref_dataOutReadyFlag),
                .frameErrorFlag(ref_frameErrorFlag),
                .endOfRx(ref_endOfRx),
      .run(ref_run),
                .startBit(ref_startBit),
                .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(serialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (
        .dataOut(dataOut),
        .overrunErrorFlag(overrunErrorFlag),
        .dataOutReadyFlag(dataOutReadyFlag),
        .frameErrorFlag(frameErrorFlag),
        .endOfRx(endOfRx),
   .run(run),
        .startBit(startBit),
        .clocksPerBit(clocksPerBit),
        .stopBit2(stopBit2),
        .ackFlags(ackFlags),
        .serialIn(serialIn),
        .clk(clk),
        .nReset(nReset)
);
 
initial
        implMismatch=0;
 
always @(posedge clk, posedge nReset) begin
        implMismatch=0;
        if(dataOut!=ref_dataOut) begin
                implMismatch=1;
                $display ("ERROR: dataOut!=ref_dataOut");
        end
        if(overrunErrorFlag!=ref_overrunErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");
        end
        if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin
                implMismatch=1;
                $display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");
        end
        if(frameErrorFlag!=ref_frameErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");
        end
        if(endOfRx!=ref_endOfRx) begin
                implMismatch=1;
                $display ("ERROR: endOfRx!=ref_endOfRx");
        end
        if(run!=ref_run) begin
                implMismatch=1;
                $display ("ERROR: run!=ref_run");
        end
        if(startBit!=ref_startBit) begin
                implMismatch=1;
                $display ("ERROR: startBit!=ref_startBit");
        end
end
 
endmodule
 
 
module tb_RxCore;
parameter PARITY        = 1;
parameter CLK_PERIOD = 10;//should be %2
        // Inputs
        reg [12:0] clocksPerBit;
        reg stopBit2;
        reg ackFlags;
        wire realSerialIn;
        reg clk;
        reg nReset;
 
        // Outputs
        wire [7:0] dataOut;
        wire overrunErrorFlag;
        wire dataOutReadyFlag;
        wire frameErrorFlag;
        wire run;
        wire startBit;
        wire stopBit;
 
 
reg serialIn;
assign #1 realSerialIn = serialIn;
 
        // Instantiate the Unit Under Test (UUT)
        wire implMismatch;
        tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (
                .implMismatch(implMismatch),
                .dataOut(dataOut),
                .overrunErrorFlag(overrunErrorFlag),
                .dataOutReadyFlag(dataOutReadyFlag),
                .frameErrorFlag(frameErrorFlag),
                .endOfRx(endOfRx),
      .run(run),
                .startBit(startBit),
                .stopBit(stopBit),
      .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(realSerialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
 
//test bench signals
reg tbClock;
integer tbError;
integer tbClockCounter;
integer tbBitTime;
integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;
integer tbLastStartBit;
reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)
 
event TrigResetDut;
event TrigResetDutRelease;
event TrigTerminateSim;
 
initial
begin
 $display ("###################################################");
 clk = 0;
 nReset = 0;
 tbError = 0;
 tbClockCounter=0;
end
 
initial
@ (TrigTerminateSim)  begin
 $display ("Terminating simulation");
 if (tbError == 0) begin
   $display ("Simulation Result : PASSED");
 end
 else begin
   $display ("Simulation Result : FAILED, %d error(s)", tbError);
 end
 $display ("###################################################");
 #1 $finish;
end
 
//parameter values for SendByte task
localparam WRONG_PARITY=8;
localparam ACKFLAGS=4;
localparam EXPECT_OVERRUN=2;
localparam EXPECT_FRAME_ERROR=1;
 
initial
forever begin
 @ (TrigResetDut);
 $display ("Applying nReset");
   nReset = 0;
        #(CLK_PERIOD*10);
   nReset = 1;
 $display ("Reset release");
 -> TrigResetDutRelease;
end
 
        initial begin
                //tb signals
                tbBitTime=8;
                tbStartBitEn=1;
                // DUT Inputs
                clocksPerBit = tbBitTime-1;
                stopBit2=0;
                ackFlags = 0;
                clk = 0;
                nReset = 0;
                tbClock=0;
                tbError=0;
                serialIn=1;
 
                //tb signals which depends on DUT config
                //those times are in clock cycle unit
                tbByteTime=(11+stopBit2)*tbBitTime;
                tbByteMinTime=tbByteTime-(tbBitTime/4);
                tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;
                tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;
 
                tc01_basicTransfer();
                tc02_earliestAckFlags();
                tc03_ackFlagsPolling();
                tc04_contiuousTransfer();
                tc05_parityError();
                tc06_basicOverrun();
                tc07_abortedStart();
                tc08_stopBitViolation();
                tc09_ackFlagsPollingFrameError();
 
                #(CLK_PERIOD*12);
                -> TrigTerminateSim;
        end
 
reg ackFlagsDone;
task ackFlagsTask;
        begin
                ackFlags=1;
                #(CLK_PERIOD*1);
                ackFlagsDone=1;
                ackFlags=0;
                #(CLK_PERIOD*1);
                if(dataOutReadyFlag) begin
                        tbError=tbError+1;
                        $display("Error %d: dataOutReadyFlag is still set",tbError);
                end
        end
endtask
 
task tc01_basicTransfer;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h55, 0);
                #(CLK_PERIOD*tbBitTime*2);
                ackFlagsTask();
        end
endtask
 
task tc02_earliestAckFlags;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);
                                ackFlagsTask();
                        end
                join
        end
endtask
 
task tc03_ackFlagsPolling;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
task tc04_contiuousTransfer;
        integer i,tc04Done;
        begin
                tc04Done=0;
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                lateAckFlagsEnable=1;
                fork
                        begin
                                for(i=0;i<256;i=i+1) begin
                                        SendByte(i, 0);
                                        //not supported by ISE12.2 (AR#         36304)
                                        //replaced by LATE_ACKFLAGS
                                        /*fork
                                                SendByte(i, 0);
                                                begin//ackFlags at the latest time possible for continuous transfer
                                                        #(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));
                                                        ackFlagsTask();
                                                end
                                        join*/
                                end
                                tc04Done=1;
                        end
                        begin
                                wait(run===1);
                                @(negedge tbIsRx);
            //Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers
            //to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...
                                /*if(0==tc04Done) begin
                                        tbError=tbError+1;
                                        $display("Error %d: tbIsRx went low during continuous transfer",tbError);
                                end*/
                        end
                join
                lateAckFlagsEnable=0;
        end
endtask
 
task tc05_parityError;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                #(CLK_PERIOD*10);
                ackFlagsTask();
                #(CLK_PERIOD*10);
                SendByte(8'hAA, ACKFLAGS);
        end
endtask
 
task tc06_basicOverrun;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, 0);
                SendByte(8'hAA, EXPECT_OVERRUN);
        end
endtask
 
task tc07_abortedStart;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                tbStartBitEn=0;
                serialIn=0;
                #(CLK_PERIOD*((tbBitTime/2)-1));
                serialIn=1;
                tbStartBitEn=1;
                #(CLK_PERIOD*(tbBitTime/2));
                SendByte(8'h55, ACKFLAGS);
        end
endtask
 
task tc08_stopBitViolation;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByteEarlyExit(8'h00, ACKFLAGS);
                SendByte(8'h55, ACKFLAGS|EXPECT_FRAME_ERROR);
        end
endtask
 
task tc09_ackFlagsPollingFrameError;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                        begin
                                wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
        /*always
                #1      tbClock =  ! tbClock;*/
        always
                #(CLK_PERIOD/2) clk =  ! clk;
 
        always @(posedge clk) begin
                tbClockCounter = tbClockCounter + 1;
                if(implMismatch)
                        tbError=tbError+1;
        end
 
 
reg tbIsRx;
always @(posedge clk) begin
        case({run, startBit})
                2'bx0:  tbIsRx<=1'b0;
                2'b0x:  tbIsRx<=1'b0;
                2'b00:  tbIsRx<=1'b0;
                2'b01:  tbIsRx<=1'b1;
                2'b10:  tbIsRx<=1'b1;
                2'bx1:  tbIsRx<=1'b1;
                2'b1x:  tbIsRx<=1'b1;
                2'b11:  begin
                        tbError=tbError+1;
                        $display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);
                end
        endcase
end
 
reg lateAckFlagsEnable;
initial
        lateAckFlagsEnable=0;
 
always @(posedge SendByteStart) begin:LATE_ACKFLAGS
        if(lateAckFlagsEnable) begin
                #(CLK_PERIOD*(tbBitTime-1));
                //#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags
                ackFlagsTask();
        end
end
 
 
function  computeParity;
input [7:0] data;
integer parity;
begin
        parity = 0;
        parity = ^data;
        parity = parity  ^ PARITY ^ 1;
        computeParity = parity;
end
endfunction
 
integer tbStartBitTimeSampler;
initial
forever begin
        @ (posedge startBit);
        if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.
                tbStartBitTimeSampler = tbClockCounter;
                tbByteClockCounter=0;
                tbLastStartBit=startBit;
                fork
                        begin
                                #(CLK_PERIOD*tbBitTime);
                                tbStartBitTime=tbStartBitTimeSampler;
                        end
                        for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin
                                @ (posedge clk);
                                if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)
                                        $display("Early start bit (%d)",tbClockCounter);
                                        if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case
                                                if(frameErrorFlag != 1) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit too early but frameErrorFlag is not set",tbError);
                                                end
                                        end else begin
                                                if(frameErrorFlag != 0) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);
                                                end
                                        end
                                        tbStartBitTime = tbClockCounter;
                                        tbByteClockCounter=0;
                                end
                                tbLastStartBit=startBit;
                        end
                join
        end
end
initial
forever begin
        @ (negedge run);
        if(0===run) begin //ignore negedge from 1 to x.
                tbRunBitFallTime = tbClockCounter;
                if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );
                end
                if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );
                end
        end
end
initial
forever begin
        wait(dataOutReadyFlag===1);
        ackFlagsDone=0;
        wait(dataOutReadyFlag===0);
end
 
reg [7:0] latchedDataOut;
integer tbdataOutReadyBitTime;
integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;
initial
forever begin
        @ (posedge dataOutReadyFlag);
        if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.
                latchedDataOut<=dataOut;
                tbdataOutReadyBitTime = tbClockCounter;
                if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );
                end
                if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );
                end
        end
end
 
reg SendByteStart;
task SendByte;
  input [7:0] data;
  input [3:0] flags;
  begin
        SendByteEarlyExit(data,flags);
        #(CLK_PERIOD*(tbBitTime-3));
        end
endtask
task SendByteEarlyExit;
  input [7:0] data;
  input [3:0] flags;
  reg wrongParity;
  reg ackFlagsWhenReady;
  reg expectOverrunError;
  reg expectFrameError;
  reg [7:0] initialData;
  begin
                {wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;
                initialData=data;
                serialIn=0;//start bit
                fork
                        begin
                                SendByteStart=1;
                                #1;
                                SendByteStart=0;
                        end
                        #(CLK_PERIOD*tbBitTime);
                join
                serialIn=data[0];//0
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[1];//1
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[2];//2
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[3];//3
                `ifdef TEST_TB
                        force uut.internalIn=1;
                `endif
                #(CLK_PERIOD*tbBitTime);
                `ifdef TEST_TB
                        release uut.internalIn;
                `endif
                serialIn=data[4];//4
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[5];//5
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[6];//6
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[7];//7
                #(CLK_PERIOD*tbBitTime);
                if(wrongParity)
                        serialIn=~computeParity(data);//wrong parity
                else
                        serialIn=computeParity(data);//parity
                #(CLK_PERIOD*tbBitTime);
                if(expectOverrunError & ~ackFlagsDone) begin
                        if(overrunErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);
                        end else if(data!=initialData) begin
                                tbError=tbError+1;
                                $display("Error %d: Data changed despite overrun condition",tbError);
                        end
                end
                if(expectFrameError & ~ackFlagsDone) begin
                        if(frameErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);
                        end
                        serialIn=1;
                        #(CLK_PERIOD*tbBitTime*12);//make sure the receiver return to idle state
                end
                if(~expectOverrunError & ~expectFrameError) begin
                        if(dataOut!=latchedDataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);
                        end
                        if(data!==dataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);
                        end
                        if(~dataOutReadyFlag & ~ackFlagsDone)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOutReadyFlag is not set",tbError);
                        end
                        if(frameErrorFlag|overrunErrorFlag)begin
                                tbError=tbError+1;
                                $display("Error %d: frameErrorFlag|overrunErrorFlag not expected but set",tbError);
                        end
                end
                serialIn=1;//stop1
                fork
                        if(ackFlagsWhenReady) begin
                                #(CLK_PERIOD*1);
                                ackFlagsTask();
                        end else
                                #(CLK_PERIOD*3);
                join
  end
endtask
 
 
endmodule
`default_nettype wire
 

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[/] [iso7816_3_master/] [trunk/] [test/] [RxCoreTestBench.v] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	acapola	`/*`
2			`Author: Sebastien Riou (acapola)`
3			`Creation date: 21:02:24 09/02/2010`
4
5			$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
6			$LastChangedBy: acapola $
7			$LastChangedRevision: 11 $
8			$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/RxCoreTestBench.v $
9
10			`This file is under the BSD licence:`
11			`Copyright (c) 2011, Sebastien Riou`
12
13			`All rights reserved.`
14
15			`Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:`
16
17			`Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.`
18			`Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.`
19			`The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.`
20			`THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS`
21			`"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT`
22			`LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR`
23			`A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR`
24			`CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
25			`EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
26			`PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR`
27			`PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF`
28			`LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
29			`NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
30			`SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
31			`*/`
32			`default_nettype none
33	2	acapola	`timescale 1ns / 1ps
34
35			`module tb_RxCoreComparator(`
36			`output reg implMismatch,`
37			`output [7:0] dataOut,`
38			`output overrunErrorFlag, //new data has been received before dataOut was read`
39			`output dataOutReadyFlag, //new data available`
40			`output frameErrorFlag, //bad parity or bad stop bits`
41			`output endOfRx,`
42			`output run, //rx is definitely started, one of the three flag will be set`
43			`output startBit, //rx is started, but we don't know yet if real rx or just a glitch`
44			`input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,`
45			`input stopBit2,//0: 1 stop bit, 1: 2 stop bits`
46			`input ackFlags,`
47			`input serialIn,`
48			`input clk,`
49			`input nReset`
50			`);`
51
52			`parameter CLK_PERIOD = 10;//should be %2`
53			`//parameters to override`
54			`parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816`
55			`//invert the polarity of the output or not`
56			`parameter IN_POLARITY = 1'b0;`
57			`parameter PARITY_POLARITY = 1'b0;`
58			`//default conventions`
59			`parameter START_BIT = 1'b0;`
60			`parameter STOP_BIT1 = 1'b1;`
61			`parameter STOP_BIT2 = 1'b1;`
62
63			`wire [7:0] ref_dataOut;`
64			`wire ref_overrunErrorFlag;`
65			`wire ref_dataOutReadyFlag;`
66			`wire ref_frameErrorFlag;`
67			`wire ref_endOfRx;`
68			`wire ref_run;`
69			`wire ref_startBit;`
70
71			`RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (`
72			`.dataOut(ref_dataOut),`
73			`.overrunErrorFlag(ref_overrunErrorFlag),`
74			`.dataOutReadyFlag(ref_dataOutReadyFlag),`
75			`.frameErrorFlag(ref_frameErrorFlag),`
76			`.endOfRx(ref_endOfRx),`
77			`.run(ref_run),`
78			`.startBit(ref_startBit),`
79			`.clocksPerBit(clocksPerBit),`
80			`.stopBit2(stopBit2),`
81			`.ackFlags(ackFlags),`
82			`.serialIn(serialIn),`
83			`.clk(clk),`
84			`.nReset(nReset)`
85			`);`
86
87			`RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (`
88			`.dataOut(dataOut),`
89			`.overrunErrorFlag(overrunErrorFlag),`
90			`.dataOutReadyFlag(dataOutReadyFlag),`
91			`.frameErrorFlag(frameErrorFlag),`
92			`.endOfRx(endOfRx),`
93			`.run(run),`
94			`.startBit(startBit),`
95			`.clocksPerBit(clocksPerBit),`
96			`.stopBit2(stopBit2),`
97			`.ackFlags(ackFlags),`
98			`.serialIn(serialIn),`
99			`.clk(clk),`
100			`.nReset(nReset)`
101			`);`
102
103			`initial`
104			`implMismatch=0;`
105
106			`always @(posedge clk, posedge nReset) begin`
107			`implMismatch=0;`
108			`if(dataOut!=ref_dataOut) begin`
109			`implMismatch=1;`
110			`$display ("ERROR: dataOut!=ref_dataOut");`
111			`end`
112			`if(overrunErrorFlag!=ref_overrunErrorFlag) begin`
113			`implMismatch=1;`
114			`$display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");`
115			`end`
116			`if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin`
117			`implMismatch=1;`
118			`$display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");`
119			`end`
120			`if(frameErrorFlag!=ref_frameErrorFlag) begin`
121			`implMismatch=1;`
122			`$display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");`
123			`end`
124			`if(endOfRx!=ref_endOfRx) begin`
125			`implMismatch=1;`
126			`$display ("ERROR: endOfRx!=ref_endOfRx");`
127			`end`
128			`if(run!=ref_run) begin`
129			`implMismatch=1;`
130			`$display ("ERROR: run!=ref_run");`
131			`end`
132			`if(startBit!=ref_startBit) begin`
133			`implMismatch=1;`
134			`$display ("ERROR: startBit!=ref_startBit");`
135			`end`
136			`end`
137
138			`endmodule`
139
140
141			`module tb_RxCore;`
142			`parameter PARITY = 1;`
143			`parameter CLK_PERIOD = 10;//should be %2`
144			`// Inputs`
145			`reg [12:0] clocksPerBit;`
146			`reg stopBit2;`
147			`reg ackFlags;`
148			`wire realSerialIn;`
149			`reg clk;`
150			`reg nReset;`
151
152			`// Outputs`
153			`wire [7:0] dataOut;`
154			`wire overrunErrorFlag;`
155			`wire dataOutReadyFlag;`
156			`wire frameErrorFlag;`
157			`wire run;`
158	5	acapola	`wire startBit;`
159			`wire stopBit;`
160	2	acapola
161
162			`reg serialIn;`
163			`assign #1 realSerialIn = serialIn;`
164
165			`// Instantiate the Unit Under Test (UUT)`
166			`wire implMismatch;`
167			`tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (`
168			`.implMismatch(implMismatch),`
169			`.dataOut(dataOut),`
170			`.overrunErrorFlag(overrunErrorFlag),`
171			`.dataOutReadyFlag(dataOutReadyFlag),`
172			`.frameErrorFlag(frameErrorFlag),`
173			`.endOfRx(endOfRx),`
174			`.run(run),`
175			`.startBit(startBit),`
176	5	acapola	`.stopBit(stopBit),`
177			`.clocksPerBit(clocksPerBit),`
178	2	acapola	`.stopBit2(stopBit2),`
179			`.ackFlags(ackFlags),`
180			`.serialIn(realSerialIn),`
181			`.clk(clk),`
182			`.nReset(nReset)`
183			`);`
184
185
186			`//test bench signals`
187			`reg tbClock;`
188			`integer tbError;`
189			`integer tbClockCounter;`
190			`integer tbBitTime;`
191			`integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;`
192			`integer tbLastStartBit;`
193			`reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)`
194
195			`event TrigResetDut;`
196			`event TrigResetDutRelease;`
197			`event TrigTerminateSim;`
198
199			`initial`
200			`begin`
201			`$display ("###################################################");`
202			`clk = 0;`
203			`nReset = 0;`
204			`tbError = 0;`
205			`tbClockCounter=0;`
206			`end`
207
208			`initial`
209			`@ (TrigTerminateSim) begin`
210			`$display ("Terminating simulation");`
211			`if (tbError == 0) begin`
212			`$display ("Simulation Result : PASSED");`
213			`end`
214			`else begin`
215			`$display ("Simulation Result : FAILED, %d error(s)", tbError);`
216			`end`
217			`$display ("###################################################");`
218			`#1 $finish;`
219			`end`
220
221			`//parameter values for SendByte task`
222			`localparam WRONG_PARITY=8;`
223			`localparam ACKFLAGS=4;`
224			`localparam EXPECT_OVERRUN=2;`
225			`localparam EXPECT_FRAME_ERROR=1;`
226
227			`initial`
228			`forever begin`
229			`@ (TrigResetDut);`
230			`$display ("Applying nReset");`
231			`nReset = 0;`
232			`#(CLK_PERIOD*10);`
233			`nReset = 1;`
234			`$display ("Reset release");`
235			`-> TrigResetDutRelease;`
236			`end`
237
238			`initial begin`
239			`//tb signals`
240			`tbBitTime=8;`
241			`tbStartBitEn=1;`
242			`// DUT Inputs`
243			`clocksPerBit = tbBitTime-1;`
244			`stopBit2=0;`
245			`ackFlags = 0;`
246			`clk = 0;`
247			`nReset = 0;`
248			`tbClock=0;`
249			`tbError=0;`
250			`serialIn=1;`
251
252			`//tb signals which depends on DUT config`
253			`//those times are in clock cycle unit`
254			`tbByteTime=(11+stopBit2)*tbBitTime;`
255			`tbByteMinTime=tbByteTime-(tbBitTime/4);`
256			`tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;`
257			`tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;`
258
259			`tc01_basicTransfer();`
260			`tc02_earliestAckFlags();`
261			`tc03_ackFlagsPolling();`
262			`tc04_contiuousTransfer();`
263			`tc05_parityError();`
264			`tc06_basicOverrun();`
265			`tc07_abortedStart();`
266			`tc08_stopBitViolation();`
267			`tc09_ackFlagsPollingFrameError();`
268
269			`#(CLK_PERIOD*12);`
270			`-> TrigTerminateSim;`
271			`end`
272
273			`reg ackFlagsDone;`
274			`task ackFlagsTask;`
275			`begin`
276			`ackFlags=1;`
277			`#(CLK_PERIOD*1);`
278			`ackFlagsDone=1;`
279			`ackFlags=0;`
280			`#(CLK_PERIOD*1);`
281			`if(dataOutReadyFlag) begin`
282			`tbError=tbError+1;`
283			`$display("Error %d: dataOutReadyFlag is still set",tbError);`
284			`end`
285			`end`
286			`endtask`
287
288			`task tc01_basicTransfer;`
289			`begin`
290			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
291			`-> TrigResetDut;@(TrigResetDutRelease);`
292			`#(CLK_PERIOD*2);`
293			`SendByte(8'h55, 0);`
294			`#(CLK_PERIODtbBitTime2);`
295			`ackFlagsTask();`
296			`end`
297			`endtask`
298
299			`task tc02_earliestAckFlags;`
300			`begin`
301			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
302			`-> TrigResetDut;@(TrigResetDutRelease);`
303			`#(CLK_PERIOD*2);`
304			`SendByte(8'h00, ACKFLAGS);`
305			`fork`
306			`SendByte(8'h55, 0);`
307			`begin`
308			`wait(dataOutReadyFlag===1);`
309			`ackFlagsTask();`
310			`end`
311			`join`
312			`end`
313			`endtask`
314
315			`task tc03_ackFlagsPolling;`
316			`begin`
317			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
318			`-> TrigResetDut;@(TrigResetDutRelease);`
319			`#(CLK_PERIOD*2);`
320			`SendByte(8'h00, ACKFLAGS);`
321			`ackFlags=1;//stuck it to one to simulate intensive polling`
322			`#(CLK_PERIOD*2);`
323			`fork`
324			`SendByte(8'h55, 0);`
325			`begin`
326			`wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously`
327			`#1;`
328			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
329			`end`
330			`join`
331			`ackFlags=0;`
332			`end`
333			`endtask`
334
335			`task tc04_contiuousTransfer;`
336			`integer i,tc04Done;`
337			`begin`
338			`tc04Done=0;`
339			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
340			`-> TrigResetDut;@(TrigResetDutRelease);`
341			`#(CLK_PERIOD*2);`
342			`SendByte(8'h00, ACKFLAGS);`
343			`lateAckFlagsEnable=1;`
344			`fork`
345			`begin`
346			`for(i=0;i<256;i=i+1) begin`
347			`SendByte(i, 0);`
348			`//not supported by ISE12.2 (AR# 36304)`
349			`//replaced by LATE_ACKFLAGS`
350			`/*fork`
351			`SendByte(i, 0);`
352			`begin//ackFlags at the latest time possible for continuous transfer`
353			`#(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));`
354			`ackFlagsTask();`
355			`end`
356			`join*/`
357			`end`
358			`tc04Done=1;`
359			`end`
360			`begin`
361			`wait(run===1);`
362			`@(negedge tbIsRx);`
363			`//Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers`
364			`//to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...`
365			`/*if(0==tc04Done) begin`
366			`tbError=tbError+1;`
367			`$display("Error %d: tbIsRx went low during continuous transfer",tbError);`
368			`end*/`
369			`end`
370			`join`
371			`lateAckFlagsEnable=0;`
372			`end`
373			`endtask`
374
375			`task tc05_parityError;`
376			`begin`
377			`-> TrigResetDut;@(TrigResetDutRelease);`
378			`#(CLK_PERIOD*2);`
379			`SendByte(8'h00, ACKFLAGS);`
380			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
381			`#(CLK_PERIOD*10);`
382			`ackFlagsTask();`
383			`#(CLK_PERIOD*10);`
384			`SendByte(8'hAA, ACKFLAGS);`
385			`end`
386			`endtask`
387
388			`task tc06_basicOverrun;`
389			`begin`
390			`-> TrigResetDut;@(TrigResetDutRelease);`
391			`#(CLK_PERIOD*2);`
392			`SendByte(8'h00, ACKFLAGS);`
393			`SendByte(8'h55, 0);`
394			`SendByte(8'hAA, EXPECT_OVERRUN);`
395			`end`
396			`endtask`
397
398			`task tc07_abortedStart;`
399			`begin`
400			`-> TrigResetDut;@(TrigResetDutRelease);`
401			`#(CLK_PERIOD*2);`
402			`SendByte(8'h00, ACKFLAGS);`
403			`tbStartBitEn=0;`
404			`serialIn=0;`
405			`#(CLK_PERIOD*((tbBitTime/2)-1));`
406			`serialIn=1;`
407			`tbStartBitEn=1;`
408			`#(CLK_PERIOD*(tbBitTime/2));`
409			`SendByte(8'h55, ACKFLAGS);`
410			`end`
411			`endtask`
412
413			`task tc08_stopBitViolation;`
414			`begin`
415			`-> TrigResetDut;@(TrigResetDutRelease);`
416			`#(CLK_PERIOD*2);`
417			`SendByteEarlyExit(8'h00, ACKFLAGS);`
418			`SendByte(8'h55, ACKFLAGS\|EXPECT_FRAME_ERROR);`
419			`end`
420			`endtask`
421
422			`task tc09_ackFlagsPollingFrameError;`
423			`begin`
424			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
425			`-> TrigResetDut;@(TrigResetDutRelease);`
426			`#(CLK_PERIOD*2);`
427			`SendByte(8'h00, ACKFLAGS);`
428			`ackFlags=1;//stuck it to one to simulate intensive polling`
429			`#(CLK_PERIOD*2);`
430			`fork`
431			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
432			`begin`
433			`wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously`
434			`#1;`
435			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
436			`end`
437			`join`
438			`ackFlags=0;`
439			`end`
440			`endtask`
441
442			`/*always`
443			`#1 tbClock = ! tbClock;*/`
444			`always`
445			`#(CLK_PERIOD/2) clk = ! clk;`
446
447			`always @(posedge clk) begin`
448			`tbClockCounter = tbClockCounter + 1;`
449			`if(implMismatch)`
450			`tbError=tbError+1;`
451			`end`
452
453
454			`reg tbIsRx;`
455			`always @(posedge clk) begin`
456			`case({run, startBit})`
457			`2'bx0: tbIsRx<=1'b0;`
458			`2'b0x: tbIsRx<=1'b0;`
459			`2'b00: tbIsRx<=1'b0;`
460			`2'b01: tbIsRx<=1'b1;`
461			`2'b10: tbIsRx<=1'b1;`
462			`2'bx1: tbIsRx<=1'b1;`
463			`2'b1x: tbIsRx<=1'b1;`
464			`2'b11: begin`
465			`tbError=tbError+1;`
466			`$display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);`
467			`end`
468			`endcase`
469			`end`
470
471			`reg lateAckFlagsEnable;`
472			`initial`
473			`lateAckFlagsEnable=0;`
474
475			`always @(posedge SendByteStart) begin:LATE_ACKFLAGS`
476			`if(lateAckFlagsEnable) begin`
477			`#(CLK_PERIOD*(tbBitTime-1));`
478			`//#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags`
479			`ackFlagsTask();`
480			`end`
481			`end`
482
483
484			`function computeParity;`
485			`input [7:0] data;`
486			`integer parity;`
487			`begin`
488			`parity = 0;`
489			`parity = ^data;`
490			`parity = parity ^ PARITY ^ 1;`
491			`computeParity = parity;`
492			`end`
493			`endfunction`
494
495			`integer tbStartBitTimeSampler;`
496			`initial`
497			`forever begin`
498			`@ (posedge startBit);`
499			`if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.`
500			`tbStartBitTimeSampler = tbClockCounter;`
501			`tbByteClockCounter=0;`
502			`tbLastStartBit=startBit;`
503			`fork`
504			`begin`
505			`#(CLK_PERIOD*tbBitTime);`
506			`tbStartBitTime=tbStartBitTimeSampler;`
507			`end`
508			`for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin`
509			`@ (posedge clk);`
510			`if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)`
511			`$display("Early start bit (%d)",tbClockCounter);`
512			`if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case`
513			`if(frameErrorFlag != 1) begin`
514			`tbError=tbError+1;`
515			`$display("Error %d: start bit too early but frameErrorFlag is not set",tbError);`
516			`end`
517			`end else begin`
518			`if(frameErrorFlag != 0) begin`
519			`tbError=tbError+1;`
520			`$display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);`
521			`end`
522			`end`
523			`tbStartBitTime = tbClockCounter;`
524			`tbByteClockCounter=0;`
525			`end`
526			`tbLastStartBit=startBit;`
527			`end`
528			`join`
529			`end`
530			`end`
531			`initial`
532			`forever begin`
533			`@ (negedge run);`
534			`if(0===run) begin //ignore negedge from 1 to x.`
535			`tbRunBitFallTime = tbClockCounter;`
536			`if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin`
537			`tbError=tbError+1;`
538			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );`
539			`end`
540			`if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin`
541			`tbError=tbError+1;`
542			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );`
543			`end`
544			`end`
545			`end`
546			`initial`
547			`forever begin`
548			`wait(dataOutReadyFlag===1);`
549			`ackFlagsDone=0;`
550			`wait(dataOutReadyFlag===0);`
551			`end`
552
553			`reg [7:0] latchedDataOut;`
554			`integer tbdataOutReadyBitTime;`
555			`integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;`
556			`initial`
557			`forever begin`
558			`@ (posedge dataOutReadyFlag);`
559			`if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.`
560			`latchedDataOut<=dataOut;`
561			`tbdataOutReadyBitTime = tbClockCounter;`
562			`if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin`
563			`tbError=tbError+1;`
564			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );`
565			`end`
566			`if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin`
567			`tbError=tbError+1;`
568			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );`
569			`end`
570			`end`
571			`end`
572
573			`reg SendByteStart;`
574			`task SendByte;`
575			`input [7:0] data;`
576			`input [3:0] flags;`
577			`begin`
578			`SendByteEarlyExit(data,flags);`
579			`#(CLK_PERIOD*(tbBitTime-3));`
580			`end`
581			`endtask`
582			`task SendByteEarlyExit;`
583			`input [7:0] data;`
584			`input [3:0] flags;`
585			`reg wrongParity;`
586			`reg ackFlagsWhenReady;`
587			`reg expectOverrunError;`
588			`reg expectFrameError;`
589			`reg [7:0] initialData;`
590			`begin`
591			`{wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;`
592			`initialData=data;`
593			`serialIn=0;//start bit`
594			`fork`
595			`begin`
596			`SendByteStart=1;`
597			`#1;`
598			`SendByteStart=0;`
599			`end`
600			`#(CLK_PERIOD*tbBitTime);`
601			`join`
602			`serialIn=data[0];//0`
603			`#(CLK_PERIOD*tbBitTime);`
604			`serialIn=data[1];//1`
605			`#(CLK_PERIOD*tbBitTime);`
606			`serialIn=data[2];//2`
607			`#(CLK_PERIOD*tbBitTime);`
608			`serialIn=data[3];//3`
609			`ifdef TEST_TB
610			`force uut.internalIn=1;`
611			`endif
612			`#(CLK_PERIOD*tbBitTime);`
613			`ifdef TEST_TB
614			`release uut.internalIn;`
615			`endif
616			`serialIn=data[4];//4`
617			`#(CLK_PERIOD*tbBitTime);`
618			`serialIn=data[5];//5`
619			`#(CLK_PERIOD*tbBitTime);`
620			`serialIn=data[6];//6`
621			`#(CLK_PERIOD*tbBitTime);`
622			`serialIn=data[7];//7`
623			`#(CLK_PERIOD*tbBitTime);`
624			`if(wrongParity)`
625			`serialIn=~computeParity(data);//wrong parity`
626			`else`
627			`serialIn=computeParity(data);//parity`
628			`#(CLK_PERIOD*tbBitTime);`
629			`if(expectOverrunError & ~ackFlagsDone) begin`
630			`if(overrunErrorFlag != 1) begin`
631			`tbError=tbError+1;`
632			`$display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);`
633			`end else if(data!=initialData) begin`
634			`tbError=tbError+1;`
635			`$display("Error %d: Data changed despite overrun condition",tbError);`
636			`end`
637			`end`
638			`if(expectFrameError & ~ackFlagsDone) begin`
639			`if(frameErrorFlag != 1) begin`
640			`tbError=tbError+1;`
641			`$display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);`
642			`end`
643			`serialIn=1;`
644			`#(CLK_PERIODtbBitTime12);//make sure the receiver return to idle state`
645			`end`
646			`if(~expectOverrunError & ~expectFrameError) begin`
647			`if(dataOut!=latchedDataOut)begin`
648			`tbError=tbError+1;`
649			`$display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);`
650			`end`
651			`if(data!==dataOut)begin`
652			`tbError=tbError+1;`
653			`$display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);`
654			`end`
655			`if(~dataOutReadyFlag & ~ackFlagsDone)begin`
656			`tbError=tbError+1;`
657			`$display("Error %d: dataOutReadyFlag is not set",tbError);`
658			`end`
659			`if(frameErrorFlag\|overrunErrorFlag)begin`
660			`tbError=tbError+1;`
661			`$display("Error %d: frameErrorFlag\|overrunErrorFlag not expected but set",tbError);`
662			`end`
663			`end`
664			`serialIn=1;//stop1`
665			`fork`
666			`if(ackFlagsWhenReady) begin`
667			`#(CLK_PERIOD*1);`
668			`ackFlagsTask();`
669			`end else`
670			`#(CLK_PERIOD*3);`
671			`join`
672			`end`
673			`endtask`
674
675
676			`endmodule`
677	11	acapola	`default_nettype wire
678	2	acapola