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[/] [iso7816_3_master/] [trunk/] [test/] [RxCoreTestBench.v] - Blame information for rev 2

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:02:24 09/02/2010
// Design Name:   RxCore
// Module Name:   D:/Hardware/Uart/tb_RxCore.v
// Project Name:  Uart
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RxCore
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module tb_RxCoreComparator(
        output reg implMismatch,
    output [7:0] dataOut,
    output overrunErrorFlag,    //new data has been received before dataOut was read
    output dataOutReadyFlag,    //new data available
    output frameErrorFlag,              //bad parity or bad stop bits
    output endOfRx,
    output run,                                 //rx is definitely started, one of the three flag will be set
    output startBit,                            //rx is started, but we don't know yet if real rx or just a glitch
         input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
         input stopBit2,//0: 1 stop bit, 1: 2 stop bits
         input ackFlags,
         input serialIn,
    input clk,
    input nReset
    );
 
parameter CLK_PERIOD = 10;//should be %2
//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
//invert the polarity of the output or not
parameter IN_POLARITY = 1'b0;
parameter PARITY_POLARITY = 1'b0;
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
wire [7:0] ref_dataOut;
wire ref_overrunErrorFlag;
wire ref_dataOutReadyFlag;
wire ref_frameErrorFlag;
wire ref_endOfRx;
wire ref_run;
wire ref_startBit;
 
RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (
                .dataOut(ref_dataOut),
                .overrunErrorFlag(ref_overrunErrorFlag),
                .dataOutReadyFlag(ref_dataOutReadyFlag),
                .frameErrorFlag(ref_frameErrorFlag),
                .endOfRx(ref_endOfRx),
      .run(ref_run),
                .startBit(ref_startBit),
                .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(serialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (
        .dataOut(dataOut),
        .overrunErrorFlag(overrunErrorFlag),
        .dataOutReadyFlag(dataOutReadyFlag),
        .frameErrorFlag(frameErrorFlag),
        .endOfRx(endOfRx),
   .run(run),
        .startBit(startBit),
        .clocksPerBit(clocksPerBit),
        .stopBit2(stopBit2),
        .ackFlags(ackFlags),
        .serialIn(serialIn),
        .clk(clk),
        .nReset(nReset)
);
 
initial
        implMismatch=0;
 
always @(posedge clk, posedge nReset) begin
        implMismatch=0;
        if(dataOut!=ref_dataOut) begin
                implMismatch=1;
                $display ("ERROR: dataOut!=ref_dataOut");
        end
        if(overrunErrorFlag!=ref_overrunErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");
        end
        if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin
                implMismatch=1;
                $display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");
        end
        if(frameErrorFlag!=ref_frameErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");
        end
        if(endOfRx!=ref_endOfRx) begin
                implMismatch=1;
                $display ("ERROR: endOfRx!=ref_endOfRx");
        end
        if(run!=ref_run) begin
                implMismatch=1;
                $display ("ERROR: run!=ref_run");
        end
        if(startBit!=ref_startBit) begin
                implMismatch=1;
                $display ("ERROR: startBit!=ref_startBit");
        end
end
 
endmodule
 
 
module tb_RxCore;
parameter PARITY        = 1;
parameter CLK_PERIOD = 10;//should be %2
        // Inputs
        reg [12:0] clocksPerBit;
        reg stopBit2;
        reg ackFlags;
        wire realSerialIn;
        reg clk;
        reg nReset;
 
        // Outputs
        wire [7:0] dataOut;
        wire overrunErrorFlag;
        wire dataOutReadyFlag;
        wire frameErrorFlag;
        wire run;
        wire startBit;
 
 
reg serialIn;
assign #1 realSerialIn = serialIn;
 
        // Instantiate the Unit Under Test (UUT)
        wire implMismatch;
        tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (
                .implMismatch(implMismatch),
                .dataOut(dataOut),
                .overrunErrorFlag(overrunErrorFlag),
                .dataOutReadyFlag(dataOutReadyFlag),
                .frameErrorFlag(frameErrorFlag),
                .endOfRx(endOfRx),
      .run(run),
                .startBit(startBit),
                .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(realSerialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
 
//test bench signals
reg tbClock;
integer tbError;
integer tbClockCounter;
integer tbBitTime;
integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;
integer tbLastStartBit;
reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)
 
event TrigResetDut;
event TrigResetDutRelease;
event TrigTerminateSim;
 
initial
begin
 $display ("###################################################");
 clk = 0;
 nReset = 0;
 tbError = 0;
 tbClockCounter=0;
end
 
initial
@ (TrigTerminateSim)  begin
 $display ("Terminating simulation");
 if (tbError == 0) begin
   $display ("Simulation Result : PASSED");
 end
 else begin
   $display ("Simulation Result : FAILED, %d error(s)", tbError);
 end
 $display ("###################################################");
 #1 $finish;
end
 
//parameter values for SendByte task
localparam WRONG_PARITY=8;
localparam ACKFLAGS=4;
localparam EXPECT_OVERRUN=2;
localparam EXPECT_FRAME_ERROR=1;
 
initial
forever begin
 @ (TrigResetDut);
 $display ("Applying nReset");
   nReset = 0;
        #(CLK_PERIOD*10);
   nReset = 1;
 $display ("Reset release");
 -> TrigResetDutRelease;
end
 
        initial begin
                //tb signals
                tbBitTime=8;
                tbStartBitEn=1;
                // DUT Inputs
                clocksPerBit = tbBitTime-1;
                stopBit2=0;
                ackFlags = 0;
                clk = 0;
                nReset = 0;
                tbClock=0;
                tbError=0;
                serialIn=1;
 
                //tb signals which depends on DUT config
                //those times are in clock cycle unit
                tbByteTime=(11+stopBit2)*tbBitTime;
                tbByteMinTime=tbByteTime-(tbBitTime/4);
                tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;
                tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;
 
                tc01_basicTransfer();
                tc02_earliestAckFlags();
                tc03_ackFlagsPolling();
                tc04_contiuousTransfer();
                tc05_parityError();
                tc06_basicOverrun();
                tc07_abortedStart();
                tc08_stopBitViolation();
                tc09_ackFlagsPollingFrameError();
 
                #(CLK_PERIOD*12);
                -> TrigTerminateSim;
        end
 
reg ackFlagsDone;
task ackFlagsTask;
        begin
                ackFlags=1;
                #(CLK_PERIOD*1);
                ackFlagsDone=1;
                ackFlags=0;
                #(CLK_PERIOD*1);
                if(dataOutReadyFlag) begin
                        tbError=tbError+1;
                        $display("Error %d: dataOutReadyFlag is still set",tbError);
                end
        end
endtask
 
task tc01_basicTransfer;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h55, 0);
                #(CLK_PERIOD*tbBitTime*2);
                ackFlagsTask();
        end
endtask
 
task tc02_earliestAckFlags;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);
                                ackFlagsTask();
                        end
                join
        end
endtask
 
task tc03_ackFlagsPolling;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
task tc04_contiuousTransfer;
        integer i,tc04Done;
        begin
                tc04Done=0;
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                lateAckFlagsEnable=1;
                fork
                        begin
                                for(i=0;i<256;i=i+1) begin
                                        SendByte(i, 0);
                                        //not supported by ISE12.2 (AR#         36304)
                                        //replaced by LATE_ACKFLAGS
                                        /*fork
                                                SendByte(i, 0);
                                                begin//ackFlags at the latest time possible for continuous transfer
                                                        #(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));
                                                        ackFlagsTask();
                                                end
                                        join*/
                                end
                                tc04Done=1;
                        end
                        begin
                                wait(run===1);
                                @(negedge tbIsRx);
            //Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers
            //to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...
                                /*if(0==tc04Done) begin
                                        tbError=tbError+1;
                                        $display("Error %d: tbIsRx went low during continuous transfer",tbError);
                                end*/
                        end
                join
                lateAckFlagsEnable=0;
        end
endtask
 
task tc05_parityError;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                #(CLK_PERIOD*10);
                ackFlagsTask();
                #(CLK_PERIOD*10);
                SendByte(8'hAA, ACKFLAGS);
        end
endtask
 
task tc06_basicOverrun;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, 0);
                SendByte(8'hAA, EXPECT_OVERRUN);
        end
endtask
 
task tc07_abortedStart;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                tbStartBitEn=0;
                serialIn=0;
                #(CLK_PERIOD*((tbBitTime/2)-1));
                serialIn=1;
                tbStartBitEn=1;
                #(CLK_PERIOD*(tbBitTime/2));
                SendByte(8'h55, ACKFLAGS);
        end
endtask
 
task tc08_stopBitViolation;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByteEarlyExit(8'h00, ACKFLAGS);
                SendByte(8'h55, ACKFLAGS|EXPECT_FRAME_ERROR);
        end
endtask
 
task tc09_ackFlagsPollingFrameError;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                        begin
                                wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
        /*always
                #1      tbClock =  ! tbClock;*/
        always
                #(CLK_PERIOD/2) clk =  ! clk;
 
        always @(posedge clk) begin
                tbClockCounter = tbClockCounter + 1;
                if(implMismatch)
                        tbError=tbError+1;
        end
 
 
reg tbIsRx;
always @(posedge clk) begin
        case({run, startBit})
                2'bx0:  tbIsRx<=1'b0;
                2'b0x:  tbIsRx<=1'b0;
                2'b00:  tbIsRx<=1'b0;
                2'b01:  tbIsRx<=1'b1;
                2'b10:  tbIsRx<=1'b1;
                2'bx1:  tbIsRx<=1'b1;
                2'b1x:  tbIsRx<=1'b1;
                2'b11:  begin
                        tbError=tbError+1;
                        $display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);
                end
        endcase
end
 
reg lateAckFlagsEnable;
initial
        lateAckFlagsEnable=0;
 
always @(posedge SendByteStart) begin:LATE_ACKFLAGS
        if(lateAckFlagsEnable) begin
                #(CLK_PERIOD*(tbBitTime-1));
                //#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags
                ackFlagsTask();
        end
end
 
 
function  computeParity;
input [7:0] data;
integer parity;
begin
        parity = 0;
        parity = ^data;
        parity = parity  ^ PARITY ^ 1;
        computeParity = parity;
end
endfunction
 
integer tbStartBitTimeSampler;
initial
forever begin
        @ (posedge startBit);
        if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.
                tbStartBitTimeSampler = tbClockCounter;
                tbByteClockCounter=0;
                tbLastStartBit=startBit;
                fork
                        begin
                                #(CLK_PERIOD*tbBitTime);
                                tbStartBitTime=tbStartBitTimeSampler;
                        end
                        for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin
                                @ (posedge clk);
                                if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)
                                        $display("Early start bit (%d)",tbClockCounter);
                                        if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case
                                                if(frameErrorFlag != 1) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit too early but frameErrorFlag is not set",tbError);
                                                end
                                        end else begin
                                                if(frameErrorFlag != 0) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);
                                                end
                                        end
                                        tbStartBitTime = tbClockCounter;
                                        tbByteClockCounter=0;
                                end
                                tbLastStartBit=startBit;
                        end
                join
        end
end
initial
forever begin
        @ (negedge run);
        if(0===run) begin //ignore negedge from 1 to x.
                tbRunBitFallTime = tbClockCounter;
                if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );
                end
                if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );
                end
        end
end
initial
forever begin
        wait(dataOutReadyFlag===1);
        ackFlagsDone=0;
        wait(dataOutReadyFlag===0);
end
 
reg [7:0] latchedDataOut;
integer tbdataOutReadyBitTime;
integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;
initial
forever begin
        @ (posedge dataOutReadyFlag);
        if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.
                latchedDataOut<=dataOut;
                tbdataOutReadyBitTime = tbClockCounter;
                if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );
                end
                if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );
                end
        end
end
 
reg SendByteStart;
task SendByte;
  input [7:0] data;
  input [3:0] flags;
  begin
        SendByteEarlyExit(data,flags);
        #(CLK_PERIOD*(tbBitTime-3));
        end
endtask
task SendByteEarlyExit;
  input [7:0] data;
  input [3:0] flags;
  reg wrongParity;
  reg ackFlagsWhenReady;
  reg expectOverrunError;
  reg expectFrameError;
  reg [7:0] initialData;
  begin
                {wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;
                initialData=data;
                serialIn=0;//start bit
                fork
                        begin
                                SendByteStart=1;
                                #1;
                                SendByteStart=0;
                        end
                        #(CLK_PERIOD*tbBitTime);
                join
                serialIn=data[0];//0
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[1];//1
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[2];//2
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[3];//3
                `ifdef TEST_TB
                        force uut.internalIn=1;
                `endif
                #(CLK_PERIOD*tbBitTime);
                `ifdef TEST_TB
                        release uut.internalIn;
                `endif
                serialIn=data[4];//4
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[5];//5
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[6];//6
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[7];//7
                #(CLK_PERIOD*tbBitTime);
                if(wrongParity)
                        serialIn=~computeParity(data);//wrong parity
                else
                        serialIn=computeParity(data);//parity
                #(CLK_PERIOD*tbBitTime);
                if(expectOverrunError & ~ackFlagsDone) begin
                        if(overrunErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);
                        end else if(data!=initialData) begin
                                tbError=tbError+1;
                                $display("Error %d: Data changed despite overrun condition",tbError);
                        end
                end
                if(expectFrameError & ~ackFlagsDone) begin
                        if(frameErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);
                        end
                        serialIn=1;
                        #(CLK_PERIOD*tbBitTime*12);//make sure the receiver return to idle state
                end
                if(~expectOverrunError & ~expectFrameError) begin
                        if(dataOut!=latchedDataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);
                        end
                        if(data!==dataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);
                        end
                        if(~dataOutReadyFlag & ~ackFlagsDone)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOutReadyFlag is not set",tbError);
                        end
                        if(frameErrorFlag|overrunErrorFlag)begin
                                tbError=tbError+1;
                                $display("Error %d: frameErrorFlag|overrunErrorFlag not expected but set",tbError);
                        end
                end
                serialIn=1;//stop1
                fork
                        if(ackFlagsWhenReady) begin
                                #(CLK_PERIOD*1);
                                ackFlagsTask();
                        end else
                                #(CLK_PERIOD*3);
                join
  end
endtask
 
 
endmodule
 

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Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [RxCoreTestBench.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	acapola	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 21:02:24 09/02/2010`
8			`// Design Name: RxCore`
9			`// Module Name: D:/Hardware/Uart/tb_RxCore.v`
10			`// Project Name: Uart`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: RxCore`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module tb_RxCoreComparator(`
26			`output reg implMismatch,`
27			`output [7:0] dataOut,`
28			`output overrunErrorFlag, //new data has been received before dataOut was read`
29			`output dataOutReadyFlag, //new data available`
30			`output frameErrorFlag, //bad parity or bad stop bits`
31			`output endOfRx,`
32			`output run, //rx is definitely started, one of the three flag will be set`
33			`output startBit, //rx is started, but we don't know yet if real rx or just a glitch`
34			`input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,`
35			`input stopBit2,//0: 1 stop bit, 1: 2 stop bits`
36			`input ackFlags,`
37			`input serialIn,`
38			`input clk,`
39			`input nReset`
40			`);`
41
42			`parameter CLK_PERIOD = 10;//should be %2`
43			`//parameters to override`
44			`parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816`
45			`//invert the polarity of the output or not`
46			`parameter IN_POLARITY = 1'b0;`
47			`parameter PARITY_POLARITY = 1'b0;`
48			`//default conventions`
49			`parameter START_BIT = 1'b0;`
50			`parameter STOP_BIT1 = 1'b1;`
51			`parameter STOP_BIT2 = 1'b1;`
52
53			`wire [7:0] ref_dataOut;`
54			`wire ref_overrunErrorFlag;`
55			`wire ref_dataOutReadyFlag;`
56			`wire ref_frameErrorFlag;`
57			`wire ref_endOfRx;`
58			`wire ref_run;`
59			`wire ref_startBit;`
60
61			`RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (`
62			`.dataOut(ref_dataOut),`
63			`.overrunErrorFlag(ref_overrunErrorFlag),`
64			`.dataOutReadyFlag(ref_dataOutReadyFlag),`
65			`.frameErrorFlag(ref_frameErrorFlag),`
66			`.endOfRx(ref_endOfRx),`
67			`.run(ref_run),`
68			`.startBit(ref_startBit),`
69			`.clocksPerBit(clocksPerBit),`
70			`.stopBit2(stopBit2),`
71			`.ackFlags(ackFlags),`
72			`.serialIn(serialIn),`
73			`.clk(clk),`
74			`.nReset(nReset)`
75			`);`
76
77			`RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (`
78			`.dataOut(dataOut),`
79			`.overrunErrorFlag(overrunErrorFlag),`
80			`.dataOutReadyFlag(dataOutReadyFlag),`
81			`.frameErrorFlag(frameErrorFlag),`
82			`.endOfRx(endOfRx),`
83			`.run(run),`
84			`.startBit(startBit),`
85			`.clocksPerBit(clocksPerBit),`
86			`.stopBit2(stopBit2),`
87			`.ackFlags(ackFlags),`
88			`.serialIn(serialIn),`
89			`.clk(clk),`
90			`.nReset(nReset)`
91			`);`
92
93			`initial`
94			`implMismatch=0;`
95
96			`always @(posedge clk, posedge nReset) begin`
97			`implMismatch=0;`
98			`if(dataOut!=ref_dataOut) begin`
99			`implMismatch=1;`
100			`$display ("ERROR: dataOut!=ref_dataOut");`
101			`end`
102			`if(overrunErrorFlag!=ref_overrunErrorFlag) begin`
103			`implMismatch=1;`
104			`$display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");`
105			`end`
106			`if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin`
107			`implMismatch=1;`
108			`$display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");`
109			`end`
110			`if(frameErrorFlag!=ref_frameErrorFlag) begin`
111			`implMismatch=1;`
112			`$display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");`
113			`end`
114			`if(endOfRx!=ref_endOfRx) begin`
115			`implMismatch=1;`
116			`$display ("ERROR: endOfRx!=ref_endOfRx");`
117			`end`
118			`if(run!=ref_run) begin`
119			`implMismatch=1;`
120			`$display ("ERROR: run!=ref_run");`
121			`end`
122			`if(startBit!=ref_startBit) begin`
123			`implMismatch=1;`
124			`$display ("ERROR: startBit!=ref_startBit");`
125			`end`
126			`end`
127
128			`endmodule`
129
130
131			`module tb_RxCore;`
132			`parameter PARITY = 1;`
133			`parameter CLK_PERIOD = 10;//should be %2`
134			`// Inputs`
135			`reg [12:0] clocksPerBit;`
136			`reg stopBit2;`
137			`reg ackFlags;`
138			`wire realSerialIn;`
139			`reg clk;`
140			`reg nReset;`
141
142			`// Outputs`
143			`wire [7:0] dataOut;`
144			`wire overrunErrorFlag;`
145			`wire dataOutReadyFlag;`
146			`wire frameErrorFlag;`
147			`wire run;`
148			`wire startBit;`
149
150
151			`reg serialIn;`
152			`assign #1 realSerialIn = serialIn;`
153
154			`// Instantiate the Unit Under Test (UUT)`
155			`wire implMismatch;`
156			`tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (`
157			`.implMismatch(implMismatch),`
158			`.dataOut(dataOut),`
159			`.overrunErrorFlag(overrunErrorFlag),`
160			`.dataOutReadyFlag(dataOutReadyFlag),`
161			`.frameErrorFlag(frameErrorFlag),`
162			`.endOfRx(endOfRx),`
163			`.run(run),`
164			`.startBit(startBit),`
165			`.clocksPerBit(clocksPerBit),`
166			`.stopBit2(stopBit2),`
167			`.ackFlags(ackFlags),`
168			`.serialIn(realSerialIn),`
169			`.clk(clk),`
170			`.nReset(nReset)`
171			`);`
172
173
174			`//test bench signals`
175			`reg tbClock;`
176			`integer tbError;`
177			`integer tbClockCounter;`
178			`integer tbBitTime;`
179			`integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;`
180			`integer tbLastStartBit;`
181			`reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)`
182
183			`event TrigResetDut;`
184			`event TrigResetDutRelease;`
185			`event TrigTerminateSim;`
186
187			`initial`
188			`begin`
189			`$display ("###################################################");`
190			`clk = 0;`
191			`nReset = 0;`
192			`tbError = 0;`
193			`tbClockCounter=0;`
194			`end`
195
196			`initial`
197			`@ (TrigTerminateSim) begin`
198			`$display ("Terminating simulation");`
199			`if (tbError == 0) begin`
200			`$display ("Simulation Result : PASSED");`
201			`end`
202			`else begin`
203			`$display ("Simulation Result : FAILED, %d error(s)", tbError);`
204			`end`
205			`$display ("###################################################");`
206			`#1 $finish;`
207			`end`
208
209			`//parameter values for SendByte task`
210			`localparam WRONG_PARITY=8;`
211			`localparam ACKFLAGS=4;`
212			`localparam EXPECT_OVERRUN=2;`
213			`localparam EXPECT_FRAME_ERROR=1;`
214
215			`initial`
216			`forever begin`
217			`@ (TrigResetDut);`
218			`$display ("Applying nReset");`
219			`nReset = 0;`
220			`#(CLK_PERIOD*10);`
221			`nReset = 1;`
222			`$display ("Reset release");`
223			`-> TrigResetDutRelease;`
224			`end`
225
226			`initial begin`
227			`//tb signals`
228			`tbBitTime=8;`
229			`tbStartBitEn=1;`
230			`// DUT Inputs`
231			`clocksPerBit = tbBitTime-1;`
232			`stopBit2=0;`
233			`ackFlags = 0;`
234			`clk = 0;`
235			`nReset = 0;`
236			`tbClock=0;`
237			`tbError=0;`
238			`serialIn=1;`
239
240			`//tb signals which depends on DUT config`
241			`//those times are in clock cycle unit`
242			`tbByteTime=(11+stopBit2)*tbBitTime;`
243			`tbByteMinTime=tbByteTime-(tbBitTime/4);`
244			`tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;`
245			`tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;`
246
247			`tc01_basicTransfer();`
248			`tc02_earliestAckFlags();`
249			`tc03_ackFlagsPolling();`
250			`tc04_contiuousTransfer();`
251			`tc05_parityError();`
252			`tc06_basicOverrun();`
253			`tc07_abortedStart();`
254			`tc08_stopBitViolation();`
255			`tc09_ackFlagsPollingFrameError();`
256
257			`#(CLK_PERIOD*12);`
258			`-> TrigTerminateSim;`
259			`end`
260
261			`reg ackFlagsDone;`
262			`task ackFlagsTask;`
263			`begin`
264			`ackFlags=1;`
265			`#(CLK_PERIOD*1);`
266			`ackFlagsDone=1;`
267			`ackFlags=0;`
268			`#(CLK_PERIOD*1);`
269			`if(dataOutReadyFlag) begin`
270			`tbError=tbError+1;`
271			`$display("Error %d: dataOutReadyFlag is still set",tbError);`
272			`end`
273			`end`
274			`endtask`
275
276			`task tc01_basicTransfer;`
277			`begin`
278			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
279			`-> TrigResetDut;@(TrigResetDutRelease);`
280			`#(CLK_PERIOD*2);`
281			`SendByte(8'h55, 0);`
282			`#(CLK_PERIODtbBitTime2);`
283			`ackFlagsTask();`
284			`end`
285			`endtask`
286
287			`task tc02_earliestAckFlags;`
288			`begin`
289			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
290			`-> TrigResetDut;@(TrigResetDutRelease);`
291			`#(CLK_PERIOD*2);`
292			`SendByte(8'h00, ACKFLAGS);`
293			`fork`
294			`SendByte(8'h55, 0);`
295			`begin`
296			`wait(dataOutReadyFlag===1);`
297			`ackFlagsTask();`
298			`end`
299			`join`
300			`end`
301			`endtask`
302
303			`task tc03_ackFlagsPolling;`
304			`begin`
305			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
306			`-> TrigResetDut;@(TrigResetDutRelease);`
307			`#(CLK_PERIOD*2);`
308			`SendByte(8'h00, ACKFLAGS);`
309			`ackFlags=1;//stuck it to one to simulate intensive polling`
310			`#(CLK_PERIOD*2);`
311			`fork`
312			`SendByte(8'h55, 0);`
313			`begin`
314			`wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously`
315			`#1;`
316			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
317			`end`
318			`join`
319			`ackFlags=0;`
320			`end`
321			`endtask`
322
323			`task tc04_contiuousTransfer;`
324			`integer i,tc04Done;`
325			`begin`
326			`tc04Done=0;`
327			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
328			`-> TrigResetDut;@(TrigResetDutRelease);`
329			`#(CLK_PERIOD*2);`
330			`SendByte(8'h00, ACKFLAGS);`
331			`lateAckFlagsEnable=1;`
332			`fork`
333			`begin`
334			`for(i=0;i<256;i=i+1) begin`
335			`SendByte(i, 0);`
336			`//not supported by ISE12.2 (AR# 36304)`
337			`//replaced by LATE_ACKFLAGS`
338			`/*fork`
339			`SendByte(i, 0);`
340			`begin//ackFlags at the latest time possible for continuous transfer`
341			`#(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));`
342			`ackFlagsTask();`
343			`end`
344			`join*/`
345			`end`
346			`tc04Done=1;`
347			`end`
348			`begin`
349			`wait(run===1);`
350			`@(negedge tbIsRx);`
351			`//Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers`
352			`//to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...`
353			`/*if(0==tc04Done) begin`
354			`tbError=tbError+1;`
355			`$display("Error %d: tbIsRx went low during continuous transfer",tbError);`
356			`end*/`
357			`end`
358			`join`
359			`lateAckFlagsEnable=0;`
360			`end`
361			`endtask`
362
363			`task tc05_parityError;`
364			`begin`
365			`-> TrigResetDut;@(TrigResetDutRelease);`
366			`#(CLK_PERIOD*2);`
367			`SendByte(8'h00, ACKFLAGS);`
368			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
369			`#(CLK_PERIOD*10);`
370			`ackFlagsTask();`
371			`#(CLK_PERIOD*10);`
372			`SendByte(8'hAA, ACKFLAGS);`
373			`end`
374			`endtask`
375
376			`task tc06_basicOverrun;`
377			`begin`
378			`-> TrigResetDut;@(TrigResetDutRelease);`
379			`#(CLK_PERIOD*2);`
380			`SendByte(8'h00, ACKFLAGS);`
381			`SendByte(8'h55, 0);`
382			`SendByte(8'hAA, EXPECT_OVERRUN);`
383			`end`
384			`endtask`
385
386			`task tc07_abortedStart;`
387			`begin`
388			`-> TrigResetDut;@(TrigResetDutRelease);`
389			`#(CLK_PERIOD*2);`
390			`SendByte(8'h00, ACKFLAGS);`
391			`tbStartBitEn=0;`
392			`serialIn=0;`
393			`#(CLK_PERIOD*((tbBitTime/2)-1));`
394			`serialIn=1;`
395			`tbStartBitEn=1;`
396			`#(CLK_PERIOD*(tbBitTime/2));`
397			`SendByte(8'h55, ACKFLAGS);`
398			`end`
399			`endtask`
400
401			`task tc08_stopBitViolation;`
402			`begin`
403			`-> TrigResetDut;@(TrigResetDutRelease);`
404			`#(CLK_PERIOD*2);`
405			`SendByteEarlyExit(8'h00, ACKFLAGS);`
406			`SendByte(8'h55, ACKFLAGS\|EXPECT_FRAME_ERROR);`
407			`end`
408			`endtask`
409
410			`task tc09_ackFlagsPollingFrameError;`
411			`begin`
412			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
413			`-> TrigResetDut;@(TrigResetDutRelease);`
414			`#(CLK_PERIOD*2);`
415			`SendByte(8'h00, ACKFLAGS);`
416			`ackFlags=1;//stuck it to one to simulate intensive polling`
417			`#(CLK_PERIOD*2);`
418			`fork`
419			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
420			`begin`
421			`wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously`
422			`#1;`
423			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
424			`end`
425			`join`
426			`ackFlags=0;`
427			`end`
428			`endtask`
429
430			`/*always`
431			`#1 tbClock = ! tbClock;*/`
432			`always`
433			`#(CLK_PERIOD/2) clk = ! clk;`
434
435			`always @(posedge clk) begin`
436			`tbClockCounter = tbClockCounter + 1;`
437			`if(implMismatch)`
438			`tbError=tbError+1;`
439			`end`
440
441
442			`reg tbIsRx;`
443			`always @(posedge clk) begin`
444			`case({run, startBit})`
445			`2'bx0: tbIsRx<=1'b0;`
446			`2'b0x: tbIsRx<=1'b0;`
447			`2'b00: tbIsRx<=1'b0;`
448			`2'b01: tbIsRx<=1'b1;`
449			`2'b10: tbIsRx<=1'b1;`
450			`2'bx1: tbIsRx<=1'b1;`
451			`2'b1x: tbIsRx<=1'b1;`
452			`2'b11: begin`
453			`tbError=tbError+1;`
454			`$display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);`
455			`end`
456			`endcase`
457			`end`
458
459			`reg lateAckFlagsEnable;`
460			`initial`
461			`lateAckFlagsEnable=0;`
462
463			`always @(posedge SendByteStart) begin:LATE_ACKFLAGS`
464			`if(lateAckFlagsEnable) begin`
465			`#(CLK_PERIOD*(tbBitTime-1));`
466			`//#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags`
467			`ackFlagsTask();`
468			`end`
469			`end`
470
471
472			`function computeParity;`
473			`input [7:0] data;`
474			`integer parity;`
475			`begin`
476			`parity = 0;`
477			`parity = ^data;`
478			`parity = parity ^ PARITY ^ 1;`
479			`computeParity = parity;`
480			`end`
481			`endfunction`
482
483			`integer tbStartBitTimeSampler;`
484			`initial`
485			`forever begin`
486			`@ (posedge startBit);`
487			`if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.`
488			`tbStartBitTimeSampler = tbClockCounter;`
489			`tbByteClockCounter=0;`
490			`tbLastStartBit=startBit;`
491			`fork`
492			`begin`
493			`#(CLK_PERIOD*tbBitTime);`
494			`tbStartBitTime=tbStartBitTimeSampler;`
495			`end`
496			`for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin`
497			`@ (posedge clk);`
498			`if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)`
499			`$display("Early start bit (%d)",tbClockCounter);`
500			`if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case`
501			`if(frameErrorFlag != 1) begin`
502			`tbError=tbError+1;`
503			`$display("Error %d: start bit too early but frameErrorFlag is not set",tbError);`
504			`end`
505			`end else begin`
506			`if(frameErrorFlag != 0) begin`
507			`tbError=tbError+1;`
508			`$display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);`
509			`end`
510			`end`
511			`tbStartBitTime = tbClockCounter;`
512			`tbByteClockCounter=0;`
513			`end`
514			`tbLastStartBit=startBit;`
515			`end`
516			`join`
517			`end`
518			`end`
519			`initial`
520			`forever begin`
521			`@ (negedge run);`
522			`if(0===run) begin //ignore negedge from 1 to x.`
523			`tbRunBitFallTime = tbClockCounter;`
524			`if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin`
525			`tbError=tbError+1;`
526			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );`
527			`end`
528			`if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin`
529			`tbError=tbError+1;`
530			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );`
531			`end`
532			`end`
533			`end`
534			`initial`
535			`forever begin`
536			`wait(dataOutReadyFlag===1);`
537			`ackFlagsDone=0;`
538			`wait(dataOutReadyFlag===0);`
539			`end`
540
541			`reg [7:0] latchedDataOut;`
542			`integer tbdataOutReadyBitTime;`
543			`integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;`
544			`initial`
545			`forever begin`
546			`@ (posedge dataOutReadyFlag);`
547			`if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.`
548			`latchedDataOut<=dataOut;`
549			`tbdataOutReadyBitTime = tbClockCounter;`
550			`if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin`
551			`tbError=tbError+1;`
552			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );`
553			`end`
554			`if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin`
555			`tbError=tbError+1;`
556			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );`
557			`end`
558			`end`
559			`end`
560
561			`reg SendByteStart;`
562			`task SendByte;`
563			`input [7:0] data;`
564			`input [3:0] flags;`
565			`begin`
566			`SendByteEarlyExit(data,flags);`
567			`#(CLK_PERIOD*(tbBitTime-3));`
568			`end`
569			`endtask`
570			`task SendByteEarlyExit;`
571			`input [7:0] data;`
572			`input [3:0] flags;`
573			`reg wrongParity;`
574			`reg ackFlagsWhenReady;`
575			`reg expectOverrunError;`
576			`reg expectFrameError;`
577			`reg [7:0] initialData;`
578			`begin`
579			`{wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;`
580			`initialData=data;`
581			`serialIn=0;//start bit`
582			`fork`
583			`begin`
584			`SendByteStart=1;`
585			`#1;`
586			`SendByteStart=0;`
587			`end`
588			`#(CLK_PERIOD*tbBitTime);`
589			`join`
590			`serialIn=data[0];//0`
591			`#(CLK_PERIOD*tbBitTime);`
592			`serialIn=data[1];//1`
593			`#(CLK_PERIOD*tbBitTime);`
594			`serialIn=data[2];//2`
595			`#(CLK_PERIOD*tbBitTime);`
596			`serialIn=data[3];//3`
597			`ifdef TEST_TB
598			`force uut.internalIn=1;`
599			`endif
600			`#(CLK_PERIOD*tbBitTime);`
601			`ifdef TEST_TB
602			`release uut.internalIn;`
603			`endif
604			`serialIn=data[4];//4`
605			`#(CLK_PERIOD*tbBitTime);`
606			`serialIn=data[5];//5`
607			`#(CLK_PERIOD*tbBitTime);`
608			`serialIn=data[6];//6`
609			`#(CLK_PERIOD*tbBitTime);`
610			`serialIn=data[7];//7`
611			`#(CLK_PERIOD*tbBitTime);`
612			`if(wrongParity)`
613			`serialIn=~computeParity(data);//wrong parity`
614			`else`
615			`serialIn=computeParity(data);//parity`
616			`#(CLK_PERIOD*tbBitTime);`
617			`if(expectOverrunError & ~ackFlagsDone) begin`
618			`if(overrunErrorFlag != 1) begin`
619			`tbError=tbError+1;`
620			`$display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);`
621			`end else if(data!=initialData) begin`
622			`tbError=tbError+1;`
623			`$display("Error %d: Data changed despite overrun condition",tbError);`
624			`end`
625			`end`
626			`if(expectFrameError & ~ackFlagsDone) begin`
627			`if(frameErrorFlag != 1) begin`
628			`tbError=tbError+1;`
629			`$display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);`
630			`end`
631			`serialIn=1;`
632			`#(CLK_PERIODtbBitTime12);//make sure the receiver return to idle state`
633			`end`
634			`if(~expectOverrunError & ~expectFrameError) begin`
635			`if(dataOut!=latchedDataOut)begin`
636			`tbError=tbError+1;`
637			`$display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);`
638			`end`
639			`if(data!==dataOut)begin`
640			`tbError=tbError+1;`
641			`$display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);`
642			`end`
643			`if(~dataOutReadyFlag & ~ackFlagsDone)begin`
644			`tbError=tbError+1;`
645			`$display("Error %d: dataOutReadyFlag is not set",tbError);`
646			`end`
647			`if(frameErrorFlag\|overrunErrorFlag)begin`
648			`tbError=tbError+1;`
649			`$display("Error %d: frameErrorFlag\|overrunErrorFlag not expected but set",tbError);`
650			`end`
651			`end`
652			`serialIn=1;//stop1`
653			`fork`
654			`if(ackFlagsWhenReady) begin`
655			`#(CLK_PERIOD*1);`
656			`ackFlagsTask();`
657			`end else`
658			`#(CLK_PERIOD*3);`
659			`join`
660			`end`
661			`endtask`
662
663
664			`endmodule`
665