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[/] [iso7816_3_master/] [trunk/] [test/] [RxCoreTestBench.v] - Blame information for rev 8

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:02:24 09/02/2010
// Design Name:   RxCore
// Module Name:   tb_RxCore.v
// Project Name:  Uart
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RxCore
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module tb_RxCoreComparator(
        output reg implMismatch,
    output [7:0] dataOut,
    output overrunErrorFlag,    //new data has been received before dataOut was read
    output dataOutReadyFlag,    //new data available
    output frameErrorFlag,              //bad parity or bad stop bits
    output endOfRx,
    output run,                                 //rx is definitely started, one of the three flag will be set
    output startBit,                            //rx is started, but we don't know yet if real rx or just a glitch
         input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,
         input stopBit2,//0: 1 stop bit, 1: 2 stop bits
         input ackFlags,
         input serialIn,
    input clk,
    input nReset
    );
 
parameter CLK_PERIOD = 10;//should be %2
//parameters to override
parameter CLOCK_PER_BIT_WIDTH = 13;     //allow to support default speed of ISO7816
//invert the polarity of the output or not
parameter IN_POLARITY = 1'b0;
parameter PARITY_POLARITY = 1'b0;
//default conventions
parameter START_BIT = 1'b0;
parameter STOP_BIT1 = 1'b1;
parameter STOP_BIT2 = 1'b1;
 
wire [7:0] ref_dataOut;
wire ref_overrunErrorFlag;
wire ref_dataOutReadyFlag;
wire ref_frameErrorFlag;
wire ref_endOfRx;
wire ref_run;
wire ref_startBit;
 
RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (
                .dataOut(ref_dataOut),
                .overrunErrorFlag(ref_overrunErrorFlag),
                .dataOutReadyFlag(ref_dataOutReadyFlag),
                .frameErrorFlag(ref_frameErrorFlag),
                .endOfRx(ref_endOfRx),
      .run(ref_run),
                .startBit(ref_startBit),
                .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(serialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (
        .dataOut(dataOut),
        .overrunErrorFlag(overrunErrorFlag),
        .dataOutReadyFlag(dataOutReadyFlag),
        .frameErrorFlag(frameErrorFlag),
        .endOfRx(endOfRx),
   .run(run),
        .startBit(startBit),
        .clocksPerBit(clocksPerBit),
        .stopBit2(stopBit2),
        .ackFlags(ackFlags),
        .serialIn(serialIn),
        .clk(clk),
        .nReset(nReset)
);
 
initial
        implMismatch=0;
 
always @(posedge clk, posedge nReset) begin
        implMismatch=0;
        if(dataOut!=ref_dataOut) begin
                implMismatch=1;
                $display ("ERROR: dataOut!=ref_dataOut");
        end
        if(overrunErrorFlag!=ref_overrunErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");
        end
        if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin
                implMismatch=1;
                $display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");
        end
        if(frameErrorFlag!=ref_frameErrorFlag) begin
                implMismatch=1;
                $display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");
        end
        if(endOfRx!=ref_endOfRx) begin
                implMismatch=1;
                $display ("ERROR: endOfRx!=ref_endOfRx");
        end
        if(run!=ref_run) begin
                implMismatch=1;
                $display ("ERROR: run!=ref_run");
        end
        if(startBit!=ref_startBit) begin
                implMismatch=1;
                $display ("ERROR: startBit!=ref_startBit");
        end
end
 
endmodule
 
 
module tb_RxCore;
parameter PARITY        = 1;
parameter CLK_PERIOD = 10;//should be %2
        // Inputs
        reg [12:0] clocksPerBit;
        reg stopBit2;
        reg ackFlags;
        wire realSerialIn;
        reg clk;
        reg nReset;
 
        // Outputs
        wire [7:0] dataOut;
        wire overrunErrorFlag;
        wire dataOutReadyFlag;
        wire frameErrorFlag;
        wire run;
        wire startBit;
        wire stopBit;
 
 
reg serialIn;
assign #1 realSerialIn = serialIn;
 
        // Instantiate the Unit Under Test (UUT)
        wire implMismatch;
        tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (
                .implMismatch(implMismatch),
                .dataOut(dataOut),
                .overrunErrorFlag(overrunErrorFlag),
                .dataOutReadyFlag(dataOutReadyFlag),
                .frameErrorFlag(frameErrorFlag),
                .endOfRx(endOfRx),
      .run(run),
                .startBit(startBit),
                .stopBit(stopBit),
      .clocksPerBit(clocksPerBit),
                .stopBit2(stopBit2),
                .ackFlags(ackFlags),
                .serialIn(realSerialIn),
                .clk(clk),
                .nReset(nReset)
        );
 
 
//test bench signals
reg tbClock;
integer tbError;
integer tbClockCounter;
integer tbBitTime;
integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;
integer tbLastStartBit;
reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)
 
event TrigResetDut;
event TrigResetDutRelease;
event TrigTerminateSim;
 
initial
begin
 $display ("###################################################");
 clk = 0;
 nReset = 0;
 tbError = 0;
 tbClockCounter=0;
end
 
initial
@ (TrigTerminateSim)  begin
 $display ("Terminating simulation");
 if (tbError == 0) begin
   $display ("Simulation Result : PASSED");
 end
 else begin
   $display ("Simulation Result : FAILED, %d error(s)", tbError);
 end
 $display ("###################################################");
 #1 $finish;
end
 
//parameter values for SendByte task
localparam WRONG_PARITY=8;
localparam ACKFLAGS=4;
localparam EXPECT_OVERRUN=2;
localparam EXPECT_FRAME_ERROR=1;
 
initial
forever begin
 @ (TrigResetDut);
 $display ("Applying nReset");
   nReset = 0;
        #(CLK_PERIOD*10);
   nReset = 1;
 $display ("Reset release");
 -> TrigResetDutRelease;
end
 
        initial begin
                //tb signals
                tbBitTime=8;
                tbStartBitEn=1;
                // DUT Inputs
                clocksPerBit = tbBitTime-1;
                stopBit2=0;
                ackFlags = 0;
                clk = 0;
                nReset = 0;
                tbClock=0;
                tbError=0;
                serialIn=1;
 
                //tb signals which depends on DUT config
                //those times are in clock cycle unit
                tbByteTime=(11+stopBit2)*tbBitTime;
                tbByteMinTime=tbByteTime-(tbBitTime/4);
                tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;
                tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;
 
                tc01_basicTransfer();
                tc02_earliestAckFlags();
                tc03_ackFlagsPolling();
                tc04_contiuousTransfer();
                tc05_parityError();
                tc06_basicOverrun();
                tc07_abortedStart();
                tc08_stopBitViolation();
                tc09_ackFlagsPollingFrameError();
 
                #(CLK_PERIOD*12);
                -> TrigTerminateSim;
        end
 
reg ackFlagsDone;
task ackFlagsTask;
        begin
                ackFlags=1;
                #(CLK_PERIOD*1);
                ackFlagsDone=1;
                ackFlags=0;
                #(CLK_PERIOD*1);
                if(dataOutReadyFlag) begin
                        tbError=tbError+1;
                        $display("Error %d: dataOutReadyFlag is still set",tbError);
                end
        end
endtask
 
task tc01_basicTransfer;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h55, 0);
                #(CLK_PERIOD*tbBitTime*2);
                ackFlagsTask();
        end
endtask
 
task tc02_earliestAckFlags;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);
                                ackFlagsTask();
                        end
                join
        end
endtask
 
task tc03_ackFlagsPolling;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, 0);
                        begin
                                wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
task tc04_contiuousTransfer;
        integer i,tc04Done;
        begin
                tc04Done=0;
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                lateAckFlagsEnable=1;
                fork
                        begin
                                for(i=0;i<256;i=i+1) begin
                                        SendByte(i, 0);
                                        //not supported by ISE12.2 (AR#         36304)
                                        //replaced by LATE_ACKFLAGS
                                        /*fork
                                                SendByte(i, 0);
                                                begin//ackFlags at the latest time possible for continuous transfer
                                                        #(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));
                                                        ackFlagsTask();
                                                end
                                        join*/
                                end
                                tc04Done=1;
                        end
                        begin
                                wait(run===1);
                                @(negedge tbIsRx);
            //Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers
            //to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...
                                /*if(0==tc04Done) begin
                                        tbError=tbError+1;
                                        $display("Error %d: tbIsRx went low during continuous transfer",tbError);
                                end*/
                        end
                join
                lateAckFlagsEnable=0;
        end
endtask
 
task tc05_parityError;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                #(CLK_PERIOD*10);
                ackFlagsTask();
                #(CLK_PERIOD*10);
                SendByte(8'hAA, ACKFLAGS);
        end
endtask
 
task tc06_basicOverrun;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                SendByte(8'h55, 0);
                SendByte(8'hAA, EXPECT_OVERRUN);
        end
endtask
 
task tc07_abortedStart;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                tbStartBitEn=0;
                serialIn=0;
                #(CLK_PERIOD*((tbBitTime/2)-1));
                serialIn=1;
                tbStartBitEn=1;
                #(CLK_PERIOD*(tbBitTime/2));
                SendByte(8'h55, ACKFLAGS);
        end
endtask
 
task tc08_stopBitViolation;
        begin
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByteEarlyExit(8'h00, ACKFLAGS);
                SendByte(8'h55, ACKFLAGS|EXPECT_FRAME_ERROR);
        end
endtask
 
task tc09_ackFlagsPollingFrameError;
        begin
                //uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started
                -> TrigResetDut;@(TrigResetDutRelease);
                #(CLK_PERIOD*2);
                SendByte(8'h00, ACKFLAGS);
                ackFlags=1;//stuck it to one to simulate intensive polling
                #(CLK_PERIOD*2);
                fork
                        SendByte(8'h55, WRONG_PARITY|EXPECT_FRAME_ERROR);
                        begin
                                wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously
                                #1;
                                ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte
                        end
                join
                ackFlags=0;
        end
endtask
 
        /*always
                #1      tbClock =  ! tbClock;*/
        always
                #(CLK_PERIOD/2) clk =  ! clk;
 
        always @(posedge clk) begin
                tbClockCounter = tbClockCounter + 1;
                if(implMismatch)
                        tbError=tbError+1;
        end
 
 
reg tbIsRx;
always @(posedge clk) begin
        case({run, startBit})
                2'bx0:  tbIsRx<=1'b0;
                2'b0x:  tbIsRx<=1'b0;
                2'b00:  tbIsRx<=1'b0;
                2'b01:  tbIsRx<=1'b1;
                2'b10:  tbIsRx<=1'b1;
                2'bx1:  tbIsRx<=1'b1;
                2'b1x:  tbIsRx<=1'b1;
                2'b11:  begin
                        tbError=tbError+1;
                        $display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);
                end
        endcase
end
 
reg lateAckFlagsEnable;
initial
        lateAckFlagsEnable=0;
 
always @(posedge SendByteStart) begin:LATE_ACKFLAGS
        if(lateAckFlagsEnable) begin
                #(CLK_PERIOD*(tbBitTime-1));
                //#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags
                ackFlagsTask();
        end
end
 
 
function  computeParity;
input [7:0] data;
integer parity;
begin
        parity = 0;
        parity = ^data;
        parity = parity  ^ PARITY ^ 1;
        computeParity = parity;
end
endfunction
 
integer tbStartBitTimeSampler;
initial
forever begin
        @ (posedge startBit);
        if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.
                tbStartBitTimeSampler = tbClockCounter;
                tbByteClockCounter=0;
                tbLastStartBit=startBit;
                fork
                        begin
                                #(CLK_PERIOD*tbBitTime);
                                tbStartBitTime=tbStartBitTimeSampler;
                        end
                        for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin
                                @ (posedge clk);
                                if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)
                                        $display("Early start bit (%d)",tbClockCounter);
                                        if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case
                                                if(frameErrorFlag != 1) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit too early but frameErrorFlag is not set",tbError);
                                                end
                                        end else begin
                                                if(frameErrorFlag != 0) begin
                                                        tbError=tbError+1;
                                                        $display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);
                                                end
                                        end
                                        tbStartBitTime = tbClockCounter;
                                        tbByteClockCounter=0;
                                end
                                tbLastStartBit=startBit;
                        end
                join
        end
end
initial
forever begin
        @ (negedge run);
        if(0===run) begin //ignore negedge from 1 to x.
                tbRunBitFallTime = tbClockCounter;
                if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );
                end
                if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );
                end
        end
end
initial
forever begin
        wait(dataOutReadyFlag===1);
        ackFlagsDone=0;
        wait(dataOutReadyFlag===0);
end
 
reg [7:0] latchedDataOut;
integer tbdataOutReadyBitTime;
integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;
initial
forever begin
        @ (posedge dataOutReadyFlag);
        if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.
                latchedDataOut<=dataOut;
                tbdataOutReadyBitTime = tbClockCounter;
                if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );
                end
                if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin
                        tbError=tbError+1;
                        $display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );
                end
        end
end
 
reg SendByteStart;
task SendByte;
  input [7:0] data;
  input [3:0] flags;
  begin
        SendByteEarlyExit(data,flags);
        #(CLK_PERIOD*(tbBitTime-3));
        end
endtask
task SendByteEarlyExit;
  input [7:0] data;
  input [3:0] flags;
  reg wrongParity;
  reg ackFlagsWhenReady;
  reg expectOverrunError;
  reg expectFrameError;
  reg [7:0] initialData;
  begin
                {wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;
                initialData=data;
                serialIn=0;//start bit
                fork
                        begin
                                SendByteStart=1;
                                #1;
                                SendByteStart=0;
                        end
                        #(CLK_PERIOD*tbBitTime);
                join
                serialIn=data[0];//0
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[1];//1
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[2];//2
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[3];//3
                `ifdef TEST_TB
                        force uut.internalIn=1;
                `endif
                #(CLK_PERIOD*tbBitTime);
                `ifdef TEST_TB
                        release uut.internalIn;
                `endif
                serialIn=data[4];//4
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[5];//5
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[6];//6
                #(CLK_PERIOD*tbBitTime);
                serialIn=data[7];//7
                #(CLK_PERIOD*tbBitTime);
                if(wrongParity)
                        serialIn=~computeParity(data);//wrong parity
                else
                        serialIn=computeParity(data);//parity
                #(CLK_PERIOD*tbBitTime);
                if(expectOverrunError & ~ackFlagsDone) begin
                        if(overrunErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);
                        end else if(data!=initialData) begin
                                tbError=tbError+1;
                                $display("Error %d: Data changed despite overrun condition",tbError);
                        end
                end
                if(expectFrameError & ~ackFlagsDone) begin
                        if(frameErrorFlag != 1) begin
                                tbError=tbError+1;
                                $display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);
                        end
                        serialIn=1;
                        #(CLK_PERIOD*tbBitTime*12);//make sure the receiver return to idle state
                end
                if(~expectOverrunError & ~expectFrameError) begin
                        if(dataOut!=latchedDataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);
                        end
                        if(data!==dataOut)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);
                        end
                        if(~dataOutReadyFlag & ~ackFlagsDone)begin
                                tbError=tbError+1;
                                $display("Error %d: dataOutReadyFlag is not set",tbError);
                        end
                        if(frameErrorFlag|overrunErrorFlag)begin
                                tbError=tbError+1;
                                $display("Error %d: frameErrorFlag|overrunErrorFlag not expected but set",tbError);
                        end
                end
                serialIn=1;//stop1
                fork
                        if(ackFlagsWhenReady) begin
                                #(CLK_PERIOD*1);
                                ackFlagsTask();
                        end else
                                #(CLK_PERIOD*3);
                join
  end
endtask
 
 
endmodule
 

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Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [RxCoreTestBench.v] - Blame information for rev 8

Line No.	Rev	Author	Line
1	2	acapola	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 21:02:24 09/02/2010`
8			`// Design Name: RxCore`
9	3	acapola	`// Module Name: tb_RxCore.v`
10	2	acapola	`// Project Name: Uart`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: RxCore`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module tb_RxCoreComparator(`
26			`output reg implMismatch,`
27			`output [7:0] dataOut,`
28			`output overrunErrorFlag, //new data has been received before dataOut was read`
29			`output dataOutReadyFlag, //new data available`
30			`output frameErrorFlag, //bad parity or bad stop bits`
31			`output endOfRx,`
32			`output run, //rx is definitely started, one of the three flag will be set`
33			`output startBit, //rx is started, but we don't know yet if real rx or just a glitch`
34			`input [CLOCK_PER_BIT_WIDTH-1:0] clocksPerBit,`
35			`input stopBit2,//0: 1 stop bit, 1: 2 stop bits`
36			`input ackFlags,`
37			`input serialIn,`
38			`input clk,`
39			`input nReset`
40			`);`
41
42			`parameter CLK_PERIOD = 10;//should be %2`
43			`//parameters to override`
44			`parameter CLOCK_PER_BIT_WIDTH = 13; //allow to support default speed of ISO7816`
45			`//invert the polarity of the output or not`
46			`parameter IN_POLARITY = 1'b0;`
47			`parameter PARITY_POLARITY = 1'b0;`
48			`//default conventions`
49			`parameter START_BIT = 1'b0;`
50			`parameter STOP_BIT1 = 1'b1;`
51			`parameter STOP_BIT2 = 1'b1;`
52
53			`wire [7:0] ref_dataOut;`
54			`wire ref_overrunErrorFlag;`
55			`wire ref_dataOutReadyFlag;`
56			`wire ref_frameErrorFlag;`
57			`wire ref_endOfRx;`
58			`wire ref_run;`
59			`wire ref_startBit;`
60
61			`RxCoreSpec #(.PARITY_POLARITY(PARITY_POLARITY)) ref (`
62			`.dataOut(ref_dataOut),`
63			`.overrunErrorFlag(ref_overrunErrorFlag),`
64			`.dataOutReadyFlag(ref_dataOutReadyFlag),`
65			`.frameErrorFlag(ref_frameErrorFlag),`
66			`.endOfRx(ref_endOfRx),`
67			`.run(ref_run),`
68			`.startBit(ref_startBit),`
69			`.clocksPerBit(clocksPerBit),`
70			`.stopBit2(stopBit2),`
71			`.ackFlags(ackFlags),`
72			`.serialIn(serialIn),`
73			`.clk(clk),`
74			`.nReset(nReset)`
75			`);`
76
77			`RxCoreSelfContained #(.PARITY_POLARITY(PARITY_POLARITY)) uut (`
78			`.dataOut(dataOut),`
79			`.overrunErrorFlag(overrunErrorFlag),`
80			`.dataOutReadyFlag(dataOutReadyFlag),`
81			`.frameErrorFlag(frameErrorFlag),`
82			`.endOfRx(endOfRx),`
83			`.run(run),`
84			`.startBit(startBit),`
85			`.clocksPerBit(clocksPerBit),`
86			`.stopBit2(stopBit2),`
87			`.ackFlags(ackFlags),`
88			`.serialIn(serialIn),`
89			`.clk(clk),`
90			`.nReset(nReset)`
91			`);`
92
93			`initial`
94			`implMismatch=0;`
95
96			`always @(posedge clk, posedge nReset) begin`
97			`implMismatch=0;`
98			`if(dataOut!=ref_dataOut) begin`
99			`implMismatch=1;`
100			`$display ("ERROR: dataOut!=ref_dataOut");`
101			`end`
102			`if(overrunErrorFlag!=ref_overrunErrorFlag) begin`
103			`implMismatch=1;`
104			`$display ("ERROR: overrunErrorFlag!=ref_overrunErrorFlag");`
105			`end`
106			`if(dataOutReadyFlag!=ref_dataOutReadyFlag) begin`
107			`implMismatch=1;`
108			`$display ("ERROR: dataOutReadyFlag!=ref_dataOutReadyFlag");`
109			`end`
110			`if(frameErrorFlag!=ref_frameErrorFlag) begin`
111			`implMismatch=1;`
112			`$display ("ERROR: frameErrorFlag!=ref_frameErrorFlag");`
113			`end`
114			`if(endOfRx!=ref_endOfRx) begin`
115			`implMismatch=1;`
116			`$display ("ERROR: endOfRx!=ref_endOfRx");`
117			`end`
118			`if(run!=ref_run) begin`
119			`implMismatch=1;`
120			`$display ("ERROR: run!=ref_run");`
121			`end`
122			`if(startBit!=ref_startBit) begin`
123			`implMismatch=1;`
124			`$display ("ERROR: startBit!=ref_startBit");`
125			`end`
126			`end`
127
128			`endmodule`
129
130
131			`module tb_RxCore;`
132			`parameter PARITY = 1;`
133			`parameter CLK_PERIOD = 10;//should be %2`
134			`// Inputs`
135			`reg [12:0] clocksPerBit;`
136			`reg stopBit2;`
137			`reg ackFlags;`
138			`wire realSerialIn;`
139			`reg clk;`
140			`reg nReset;`
141
142			`// Outputs`
143			`wire [7:0] dataOut;`
144			`wire overrunErrorFlag;`
145			`wire dataOutReadyFlag;`
146			`wire frameErrorFlag;`
147			`wire run;`
148	5	acapola	`wire startBit;`
149			`wire stopBit;`
150	2	acapola
151
152			`reg serialIn;`
153			`assign #1 realSerialIn = serialIn;`
154
155			`// Instantiate the Unit Under Test (UUT)`
156			`wire implMismatch;`
157			`tb_RxCoreComparator #(.PARITY_POLARITY(PARITY)) uut (`
158			`.implMismatch(implMismatch),`
159			`.dataOut(dataOut),`
160			`.overrunErrorFlag(overrunErrorFlag),`
161			`.dataOutReadyFlag(dataOutReadyFlag),`
162			`.frameErrorFlag(frameErrorFlag),`
163			`.endOfRx(endOfRx),`
164			`.run(run),`
165			`.startBit(startBit),`
166	5	acapola	`.stopBit(stopBit),`
167			`.clocksPerBit(clocksPerBit),`
168	2	acapola	`.stopBit2(stopBit2),`
169			`.ackFlags(ackFlags),`
170			`.serialIn(realSerialIn),`
171			`.clk(clk),`
172			`.nReset(nReset)`
173			`);`
174
175
176			`//test bench signals`
177			`reg tbClock;`
178			`integer tbError;`
179			`integer tbClockCounter;`
180			`integer tbBitTime;`
181			`integer tbStartBitTime,tbRunBitFallTime, tbByteTime, tbByteMinTime, tbByteClockCounter;`
182			`integer tbLastStartBit;`
183			`reg tbStartBitEn;//set this to 0 to turn of start bit detection (useful when testing glitch)`
184
185			`event TrigResetDut;`
186			`event TrigResetDutRelease;`
187			`event TrigTerminateSim;`
188
189			`initial`
190			`begin`
191			`$display ("###################################################");`
192			`clk = 0;`
193			`nReset = 0;`
194			`tbError = 0;`
195			`tbClockCounter=0;`
196			`end`
197
198			`initial`
199			`@ (TrigTerminateSim) begin`
200			`$display ("Terminating simulation");`
201			`if (tbError == 0) begin`
202			`$display ("Simulation Result : PASSED");`
203			`end`
204			`else begin`
205			`$display ("Simulation Result : FAILED, %d error(s)", tbError);`
206			`end`
207			`$display ("###################################################");`
208			`#1 $finish;`
209			`end`
210
211			`//parameter values for SendByte task`
212			`localparam WRONG_PARITY=8;`
213			`localparam ACKFLAGS=4;`
214			`localparam EXPECT_OVERRUN=2;`
215			`localparam EXPECT_FRAME_ERROR=1;`
216
217			`initial`
218			`forever begin`
219			`@ (TrigResetDut);`
220			`$display ("Applying nReset");`
221			`nReset = 0;`
222			`#(CLK_PERIOD*10);`
223			`nReset = 1;`
224			`$display ("Reset release");`
225			`-> TrigResetDutRelease;`
226			`end`
227
228			`initial begin`
229			`//tb signals`
230			`tbBitTime=8;`
231			`tbStartBitEn=1;`
232			`// DUT Inputs`
233			`clocksPerBit = tbBitTime-1;`
234			`stopBit2=0;`
235			`ackFlags = 0;`
236			`clk = 0;`
237			`nReset = 0;`
238			`tbClock=0;`
239			`tbError=0;`
240			`serialIn=1;`
241
242			`//tb signals which depends on DUT config`
243			`//those times are in clock cycle unit`
244			`tbByteTime=(11+stopBit2)*tbBitTime;`
245			`tbByteMinTime=tbByteTime-(tbBitTime/4);`
246			`tbdataOutReadyBitMinTime=9*tbBitTime+(tbBitTime/2)-1;`
247			`tbdataOutReadyBitMaxTime=tbdataOutReadyBitMinTime+(tbBitTime/4)+1;`
248
249			`tc01_basicTransfer();`
250			`tc02_earliestAckFlags();`
251			`tc03_ackFlagsPolling();`
252			`tc04_contiuousTransfer();`
253			`tc05_parityError();`
254			`tc06_basicOverrun();`
255			`tc07_abortedStart();`
256			`tc08_stopBitViolation();`
257			`tc09_ackFlagsPollingFrameError();`
258
259			`#(CLK_PERIOD*12);`
260			`-> TrigTerminateSim;`
261			`end`
262
263			`reg ackFlagsDone;`
264			`task ackFlagsTask;`
265			`begin`
266			`ackFlags=1;`
267			`#(CLK_PERIOD*1);`
268			`ackFlagsDone=1;`
269			`ackFlags=0;`
270			`#(CLK_PERIOD*1);`
271			`if(dataOutReadyFlag) begin`
272			`tbError=tbError+1;`
273			`$display("Error %d: dataOutReadyFlag is still set",tbError);`
274			`end`
275			`end`
276			`endtask`
277
278			`task tc01_basicTransfer;`
279			`begin`
280			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
281			`-> TrigResetDut;@(TrigResetDutRelease);`
282			`#(CLK_PERIOD*2);`
283			`SendByte(8'h55, 0);`
284			`#(CLK_PERIODtbBitTime2);`
285			`ackFlagsTask();`
286			`end`
287			`endtask`
288
289			`task tc02_earliestAckFlags;`
290			`begin`
291			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
292			`-> TrigResetDut;@(TrigResetDutRelease);`
293			`#(CLK_PERIOD*2);`
294			`SendByte(8'h00, ACKFLAGS);`
295			`fork`
296			`SendByte(8'h55, 0);`
297			`begin`
298			`wait(dataOutReadyFlag===1);`
299			`ackFlagsTask();`
300			`end`
301			`join`
302			`end`
303			`endtask`
304
305			`task tc03_ackFlagsPolling;`
306			`begin`
307			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
308			`-> TrigResetDut;@(TrigResetDutRelease);`
309			`#(CLK_PERIOD*2);`
310			`SendByte(8'h00, ACKFLAGS);`
311			`ackFlags=1;//stuck it to one to simulate intensive polling`
312			`#(CLK_PERIOD*2);`
313			`fork`
314			`SendByte(8'h55, 0);`
315			`begin`
316			`wait(dataOutReadyFlag===1);//check that dataOutReadyFlag is set even if ackFlags is set continuously`
317			`#1;`
318			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
319			`end`
320			`join`
321			`ackFlags=0;`
322			`end`
323			`endtask`
324
325			`task tc04_contiuousTransfer;`
326			`integer i,tc04Done;`
327			`begin`
328			`tc04Done=0;`
329			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
330			`-> TrigResetDut;@(TrigResetDutRelease);`
331			`#(CLK_PERIOD*2);`
332			`SendByte(8'h00, ACKFLAGS);`
333			`lateAckFlagsEnable=1;`
334			`fork`
335			`begin`
336			`for(i=0;i<256;i=i+1) begin`
337			`SendByte(i, 0);`
338			`//not supported by ISE12.2 (AR# 36304)`
339			`//replaced by LATE_ACKFLAGS`
340			`/*fork`
341			`SendByte(i, 0);`
342			`begin//ackFlags at the latest time possible for continuous transfer`
343			`#(CLK_PERIOD*((tbBitTime/2)+tbBitTime-1));`
344			`ackFlagsTask();`
345			`end`
346			`join*/`
347			`end`
348			`tc04Done=1;`
349			`end`
350			`begin`
351			`wait(run===1);`
352			`@(negedge tbIsRx);`
353			`//Spec change, run goes low one cycles earlier so a negedge happen even during continuous transfers`
354			`//to emulate old behavior, a signal following run can be implement using a flip flop and combine run and following signal with an or gate...`
355			`/*if(0==tc04Done) begin`
356			`tbError=tbError+1;`
357			`$display("Error %d: tbIsRx went low during continuous transfer",tbError);`
358			`end*/`
359			`end`
360			`join`
361			`lateAckFlagsEnable=0;`
362			`end`
363			`endtask`
364
365			`task tc05_parityError;`
366			`begin`
367			`-> TrigResetDut;@(TrigResetDutRelease);`
368			`#(CLK_PERIOD*2);`
369			`SendByte(8'h00, ACKFLAGS);`
370			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
371			`#(CLK_PERIOD*10);`
372			`ackFlagsTask();`
373			`#(CLK_PERIOD*10);`
374			`SendByte(8'hAA, ACKFLAGS);`
375			`end`
376			`endtask`
377
378			`task tc06_basicOverrun;`
379			`begin`
380			`-> TrigResetDut;@(TrigResetDutRelease);`
381			`#(CLK_PERIOD*2);`
382			`SendByte(8'h00, ACKFLAGS);`
383			`SendByte(8'h55, 0);`
384			`SendByte(8'hAA, EXPECT_OVERRUN);`
385			`end`
386			`endtask`
387
388			`task tc07_abortedStart;`
389			`begin`
390			`-> TrigResetDut;@(TrigResetDutRelease);`
391			`#(CLK_PERIOD*2);`
392			`SendByte(8'h00, ACKFLAGS);`
393			`tbStartBitEn=0;`
394			`serialIn=0;`
395			`#(CLK_PERIOD*((tbBitTime/2)-1));`
396			`serialIn=1;`
397			`tbStartBitEn=1;`
398			`#(CLK_PERIOD*(tbBitTime/2));`
399			`SendByte(8'h55, ACKFLAGS);`
400			`end`
401			`endtask`
402
403			`task tc08_stopBitViolation;`
404			`begin`
405			`-> TrigResetDut;@(TrigResetDutRelease);`
406			`#(CLK_PERIOD*2);`
407			`SendByteEarlyExit(8'h00, ACKFLAGS);`
408			`SendByte(8'h55, ACKFLAGS\|EXPECT_FRAME_ERROR);`
409			`end`
410			`endtask`
411
412			`task tc09_ackFlagsPollingFrameError;`
413			`begin`
414			`//uut.dataOut=8'b0;//to see the point where it becomes undefined when a rx started`
415			`-> TrigResetDut;@(TrigResetDutRelease);`
416			`#(CLK_PERIOD*2);`
417			`SendByte(8'h00, ACKFLAGS);`
418			`ackFlags=1;//stuck it to one to simulate intensive polling`
419			`#(CLK_PERIOD*2);`
420			`fork`
421			`SendByte(8'h55, WRONG_PARITY\|EXPECT_FRAME_ERROR);`
422			`begin`
423			`wait(frameErrorFlag===1);//check that frameErrorFlag is set even if ackFlags is set continuously`
424			`#1;`
425			`ackFlagsDone=1;//set ackFlagsDone to avoid to get dummy error due to the check within SendByte`
426			`end`
427			`join`
428			`ackFlags=0;`
429			`end`
430			`endtask`
431
432			`/*always`
433			`#1 tbClock = ! tbClock;*/`
434			`always`
435			`#(CLK_PERIOD/2) clk = ! clk;`
436
437			`always @(posedge clk) begin`
438			`tbClockCounter = tbClockCounter + 1;`
439			`if(implMismatch)`
440			`tbError=tbError+1;`
441			`end`
442
443
444			`reg tbIsRx;`
445			`always @(posedge clk) begin`
446			`case({run, startBit})`
447			`2'bx0: tbIsRx<=1'b0;`
448			`2'b0x: tbIsRx<=1'b0;`
449			`2'b00: tbIsRx<=1'b0;`
450			`2'b01: tbIsRx<=1'b1;`
451			`2'b10: tbIsRx<=1'b1;`
452			`2'bx1: tbIsRx<=1'b1;`
453			`2'b1x: tbIsRx<=1'b1;`
454			`2'b11: begin`
455			`tbError=tbError+1;`
456			`$display("Error %d: run & StartBit are set simultaneously during clock rising edge",tbError);`
457			`end`
458			`endcase`
459			`end`
460
461			`reg lateAckFlagsEnable;`
462			`initial`
463			`lateAckFlagsEnable=0;`
464
465			`always @(posedge SendByteStart) begin:LATE_ACKFLAGS`
466			`if(lateAckFlagsEnable) begin`
467			`#(CLK_PERIOD*(tbBitTime-1));`
468			`//#(CLK_PERIOD);//to test it is really the latest cycle to ack the flags`
469			`ackFlagsTask();`
470			`end`
471			`end`
472
473
474			`function computeParity;`
475			`input [7:0] data;`
476			`integer parity;`
477			`begin`
478			`parity = 0;`
479			`parity = ^data;`
480			`parity = parity ^ PARITY ^ 1;`
481			`computeParity = parity;`
482			`end`
483			`endfunction`
484
485			`integer tbStartBitTimeSampler;`
486			`initial`
487			`forever begin`
488			`@ (posedge startBit);`
489			`if(tbStartBitEn && (1===startBit)) begin //ignore posedge from 0 to x.`
490			`tbStartBitTimeSampler = tbClockCounter;`
491			`tbByteClockCounter=0;`
492			`tbLastStartBit=startBit;`
493			`fork`
494			`begin`
495			`#(CLK_PERIOD*tbBitTime);`
496			`tbStartBitTime=tbStartBitTimeSampler;`
497			`end`
498			`for(tbByteClockCounter=0;tbByteClockCounter<tbByteTime;tbByteClockCounter=tbByteClockCounter+1) begin`
499			`@ (posedge clk);`
500			`if((tbLastStartBit ==0) && (startBit == 1)) begin //this is to handle early start bit (happens before end of previous byte)`
501			`$display("Early start bit (%d)",tbClockCounter);`
502			`if(tbClockCounter-tbStartBitTime < tbByteMinTime) begin //frame error case`
503			`if(frameErrorFlag != 1) begin`
504			`tbError=tbError+1;`
505			`$display("Error %d: start bit too early but frameErrorFlag is not set",tbError);`
506			`end`
507			`end else begin`
508			`if(frameErrorFlag != 0) begin`
509			`tbError=tbError+1;`
510			`$display("Error %d: start bit within tolerated advance but frameErrorFlag is set",tbError);`
511			`end`
512			`end`
513			`tbStartBitTime = tbClockCounter;`
514			`tbByteClockCounter=0;`
515			`end`
516			`tbLastStartBit=startBit;`
517			`end`
518			`join`
519			`end`
520			`end`
521			`initial`
522			`forever begin`
523			`@ (negedge run);`
524			`if(0===run) begin //ignore negedge from 1 to x.`
525			`tbRunBitFallTime = tbClockCounter;`
526			`if(tbRunBitFallTime-tbStartBitTime < tbByteMinTime) begin`
527			`tbError=tbError+1;`
528			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, >= %d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteMinTime );`
529			`end`
530			`if(tbRunBitFallTime-tbStartBitTime > tbByteTime) begin`
531			`tbError=tbError+1;`
532			`$display("Error %d: tbRunBitFallTime-tbStartBitTime =%d, <=%d was expected",tbError, tbRunBitFallTime-tbStartBitTime, tbByteTime );`
533			`end`
534			`end`
535			`end`
536			`initial`
537			`forever begin`
538			`wait(dataOutReadyFlag===1);`
539			`ackFlagsDone=0;`
540			`wait(dataOutReadyFlag===0);`
541			`end`
542
543			`reg [7:0] latchedDataOut;`
544			`integer tbdataOutReadyBitTime;`
545			`integer tbdataOutReadyBitMinTime,tbdataOutReadyBitMaxTime;`
546			`initial`
547			`forever begin`
548			`@ (posedge dataOutReadyFlag);`
549			`if(1===dataOutReadyFlag) begin //ignore posedge from 0 to x.`
550			`latchedDataOut<=dataOut;`
551			`tbdataOutReadyBitTime = tbClockCounter;`
552			`if(tbdataOutReadyBitTime-tbStartBitTime < tbdataOutReadyBitMinTime) begin`
553			`tbError=tbError+1;`
554			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, >= %d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMinTime );`
555			`end`
556			`if(tbdataOutReadyBitTime-tbStartBitTime > tbdataOutReadyBitMaxTime) begin`
557			`tbError=tbError+1;`
558			`$display("Error %d: tbdataOutReadyBitTime-tbStartBitTime =%d, <=%d was expected",tbError, tbdataOutReadyBitTime-tbStartBitTime, tbdataOutReadyBitMaxTime );`
559			`end`
560			`end`
561			`end`
562
563			`reg SendByteStart;`
564			`task SendByte;`
565			`input [7:0] data;`
566			`input [3:0] flags;`
567			`begin`
568			`SendByteEarlyExit(data,flags);`
569			`#(CLK_PERIOD*(tbBitTime-3));`
570			`end`
571			`endtask`
572			`task SendByteEarlyExit;`
573			`input [7:0] data;`
574			`input [3:0] flags;`
575			`reg wrongParity;`
576			`reg ackFlagsWhenReady;`
577			`reg expectOverrunError;`
578			`reg expectFrameError;`
579			`reg [7:0] initialData;`
580			`begin`
581			`{wrongParity,ackFlagsWhenReady,expectOverrunError,expectFrameError}=flags;`
582			`initialData=data;`
583			`serialIn=0;//start bit`
584			`fork`
585			`begin`
586			`SendByteStart=1;`
587			`#1;`
588			`SendByteStart=0;`
589			`end`
590			`#(CLK_PERIOD*tbBitTime);`
591			`join`
592			`serialIn=data[0];//0`
593			`#(CLK_PERIOD*tbBitTime);`
594			`serialIn=data[1];//1`
595			`#(CLK_PERIOD*tbBitTime);`
596			`serialIn=data[2];//2`
597			`#(CLK_PERIOD*tbBitTime);`
598			`serialIn=data[3];//3`
599			`ifdef TEST_TB
600			`force uut.internalIn=1;`
601			`endif
602			`#(CLK_PERIOD*tbBitTime);`
603			`ifdef TEST_TB
604			`release uut.internalIn;`
605			`endif
606			`serialIn=data[4];//4`
607			`#(CLK_PERIOD*tbBitTime);`
608			`serialIn=data[5];//5`
609			`#(CLK_PERIOD*tbBitTime);`
610			`serialIn=data[6];//6`
611			`#(CLK_PERIOD*tbBitTime);`
612			`serialIn=data[7];//7`
613			`#(CLK_PERIOD*tbBitTime);`
614			`if(wrongParity)`
615			`serialIn=~computeParity(data);//wrong parity`
616			`else`
617			`serialIn=computeParity(data);//parity`
618			`#(CLK_PERIOD*tbBitTime);`
619			`if(expectOverrunError & ~ackFlagsDone) begin`
620			`if(overrunErrorFlag != 1) begin`
621			`tbError=tbError+1;`
622			`$display("Error %d: Overrun error expected but overrunErrorFlag is not set",tbError);`
623			`end else if(data!=initialData) begin`
624			`tbError=tbError+1;`
625			`$display("Error %d: Data changed despite overrun condition",tbError);`
626			`end`
627			`end`
628			`if(expectFrameError & ~ackFlagsDone) begin`
629			`if(frameErrorFlag != 1) begin`
630			`tbError=tbError+1;`
631			`$display("Error %d: Frame error expected but frameErrorFlag is not set",tbError);`
632			`end`
633			`serialIn=1;`
634			`#(CLK_PERIODtbBitTime12);//make sure the receiver return to idle state`
635			`end`
636			`if(~expectOverrunError & ~expectFrameError) begin`
637			`if(dataOut!=latchedDataOut)begin`
638			`tbError=tbError+1;`
639			`$display("Error %d: latchedDataOut mismatch-->dataOut changed after dataOutReadyFlag edge, dataOut=0x%x, latchedDataOut=0x%x",tbError, dataOut, latchedDataOut);`
640			`end`
641			`if(data!==dataOut)begin`
642			`tbError=tbError+1;`
643			`$display("Error %d: dataOut mismatch, dataOut=0x%x, 0x%x was expected",tbError, dataOut, data);`
644			`end`
645			`if(~dataOutReadyFlag & ~ackFlagsDone)begin`
646			`tbError=tbError+1;`
647			`$display("Error %d: dataOutReadyFlag is not set",tbError);`
648			`end`
649			`if(frameErrorFlag\|overrunErrorFlag)begin`
650			`tbError=tbError+1;`
651			`$display("Error %d: frameErrorFlag\|overrunErrorFlag not expected but set",tbError);`
652			`end`
653			`end`
654			`serialIn=1;//stop1`
655			`fork`
656			`if(ackFlagsWhenReady) begin`
657			`#(CLK_PERIOD*1);`
658			`ackFlagsTask();`
659			`end else`
660			`#(CLK_PERIOD*3);`
661			`join`
662			`end`
663			`endtask`
664
665
666			`endmodule`
667