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/*
Author: Sebastien Riou (acapola)
Creation date: 22:22:43 01/10/2011
 
$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
$LastChangedBy: acapola $
$LastChangedRevision: 11 $
$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
 
This file is under the BSD licence:
Copyright (c) 2011, Sebastien Riou
 
All rights reserved.
 
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
 
Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
 
 
module Iso7816_3_t0_analyzer
#(parameter DIVIDER_WIDTH = 1)
(
        input wire nReset,
        input wire clk,
        input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
        input wire isoReset,
        input wire isoClk,
        input wire isoVdd,
        input wire isoSioTerm,
        input wire isoSioCard,
        input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs
        output reg [3:0] fiCode,
        output reg [3:0] diCode,
        output wire [12:0] fi,
        output wire [7:0] di,
        output wire [12:0] cyclesPerEtu,
        output wire [7:0] fMax,
        output wire isActivated,
        output wire tsReceived,
        output wire tsError,
        output wire useIndirectConvention,
        output wire atrIsEarly,//high if TS received before 400 cycles after reset release
        output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
        output reg [3:0] atrK,//number of historical bytes
        output reg atrHasTck,
        output reg atrCompleted,
        output reg useT0,
        output reg useT1,
        output reg useT15,
        output reg waitCardTx,
        output reg waitTermTx,
        output wire cardTx,
        output wire termTx,
        output wire guardTime,
        output wire overrunError,
        output wire frameError,
        output reg [7:0] lastByte,
        output reg [31:0] bytesCnt
        );
 
wire isoSio = isoSioTerm & isoSioCard;
 
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
reg [7:0] buffer[256+5:0];
localparam CLA_I= 8*4;
localparam INS_I= 8*3;
localparam P1_I = 8*2;
localparam P2_I = 8*1;
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
//wire COM_clk=isoClk;
//integer COM_errorCnt;
//wire txPending=1'b0;
//wire txRun=1'b0;
 
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign overrunErrorFlag = overrunError;
assign frameErrorFlag = frameError;
 
wire [7:0] rxData;
reg ackFlags;
 
wire msbFirst = useIndirectConvention;
wire sioHighValue = ~useIndirectConvention;
wire oddParity = 1'b0;
 
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
 
 
//`include "ComRxDriverTasks.v"
 
wire endOfRx;
 
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
wire [12:0] clocksPerBit = cyclesPerEtu-1;
RxCoreSelfContained #(
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .CLOCK_PER_BIT_WIDTH(4'd13),
                .PRECISE_STOP_BIT(1'b1))
        rxCore (
    .dataOut(rxData),
    .overrunErrorFlag(overrunError),
    .dataOutReadyFlag(bufferFull),
    .frameErrorFlag(frameError),
    .endOfRx(endOfRx),
    .run(rxRun),
    .startBit(rxStartBit),
         .stopBit(guardTime),
    .clkPerCycle(clkPerCycle),
    .clocksPerBit(clocksPerBit),
    .stopBit2(stopBit2),
    .oddParity(oddParity),
    .msbFirst(msbFirst),
         .ackFlags(ackFlags),
    .serialIn(isoSio),
    .comClk(isoClk),
    .clk(clk),
    .nReset(nReset)
    );
 
TsAnalyzer tsAnalyzer(
        .nReset(nReset),
        .isoReset(isoReset),
        .isoClk(isoClk),
        .isoVdd(isoVdd),
        .isoSio(isoSio),
        .endOfRx(endOfRx),
        .rxData(rxData),
        .isActivated(isActivated),
        .tsReceived(tsReceived),
        .tsError(tsError),
        .atrIsEarly(atrIsEarly),
        .atrIsLate(atrIsLate),
        .useIndirectConvention(useIndirectConvention)
        );
 
FiDiAnalyzer fiDiAnalyzer(
        .fiCode(fiCode),
        .diCode(diCode),
        .fi(fi),
        .di(di),
        .cyclesPerEtu(cyclesPerEtu),
        .fMax(fMax)
        );
 
wire run = rxStartBit | rxRun;
localparam ATR_T0 = 0;
localparam ATR_TDI = 1;
localparam ATR_HISTORICAL = 2;
localparam ATR_TCK = 3;
localparam T0_HEADER = 0;
localparam T0_HEADER_TPDU = 1;
localparam T0_PB = 2;
localparam T0_DATA = 3;
localparam T0_NACK_DATA = 4;
localparam T0_SW1 = 5;
localparam T0_SW2 = 6;
localparam T0_HEADER_PPS = 100;
 
integer fsmState;
 
reg [11:0] tdiStruct;
wire [3:0] tdiCnt;//i+1
wire [7:0] tdiData;//value of TDi
assign {tdiCnt,tdiData}=tdiStruct;
 
wire [1:0] nIfBytes;
HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
reg [7:0] tempBytesCnt;
always @(posedge isoClk, negedge nReset) begin
        if(~nReset) begin
                lastByte<=8'b0;
                ackFlags<=1'b0;
                bytesCnt<=32'b0;
        end else if(ackFlags) begin
                ackFlags<=1'b0;
        end else if(frameErrorFlag|bufferFull) begin
                lastByte<=dataOut;
                ackFlags<=1'b1;
                bytesCnt<=bytesCnt+1'b1;
        end
end
always @(posedge isoClk, negedge nReset) begin
        if(~nReset) begin
                fiCode<=4'b0001;
                diCode<=4'b0001;
                useT0<=1'b1;
                useT1<=1'b0;
                useT15<=1'b0;
                {waitCardTx,waitTermTx}<=2'b00;
                fsmState<=ATR_TDI;
                atrHasTck<=1'b0;
                tempBytesCnt<=8'h0;
                tdiStruct<=12'h0;
                atrCompleted<=1'b0;
                atrK<=4'b0;
        end else if(isActivated) begin
                if(~tsReceived) begin
                        {waitCardTx,waitTermTx}<=2'b10;
                end else if(~atrCompleted) begin
                        //ATR analysis
                        case(fsmState)
                                ATR_TDI: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==nIfBytes) begin //TDi bytes
                                                        tempBytesCnt <= 2'h0;
                                                        tdiStruct <= {tdiCnt+1,dataOut};
                                                        if(4'h0==tdiCnt) begin//this is T0
                                                                atrK <= dataOut[3:0];
                                                                fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
                                                                                                (4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
                                                        end else begin//TDi, i from 1 to 15
                                                                fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
                                                                                                (4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
                                                        end
                                                        if(12'h0=={dataOut,atrK}) begin
                                                                atrCompleted <= 1'b1;
                                                                {waitCardTx,waitTermTx}<=2'b01;
                                                        end
                                                end else begin //TA, TB or TC bytes
                                                        //TODO: get relevant info
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                ATR_HISTORICAL: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==atrK) begin
                                                        tempBytesCnt <= 8'h0;
                                                        if(atrHasTck) begin
                                                                fsmState <= ATR_TCK;
                                                        end else begin
                                                                atrCompleted <= ~atrHasTck;
                                                                {waitCardTx,waitTermTx}<=2'b10;
                                                                fsmState <= T0_HEADER;
                                                        end
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                ATR_TCK: begin
                                        if(endOfRx) begin
                                        //TODO:check
                                                atrCompleted <= 1'b1;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                                fsmState <= T0_HEADER;
                                        end
                                end
                        endcase
                end else if(useT0) begin
                        //T=0 cmd/response monitoring state machine
                        case(fsmState)
                                T0_HEADER: begin
                                        if(endOfRx) begin
                                                tpduHeader[CLA_I+:8]<=dataOut;
                                                tempBytesCnt <= 1;
                                                if(8'hFF==dataOut)
                                                        fsmState <= T0_HEADER_PPS;//TODO
                                                else
                                                        fsmState <= T0_HEADER_TPDU;
                                        end
                                end
                                T0_HEADER_TPDU: begin
                                        if(endOfRx) begin
                                                tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
                                                if(4==tempBytesCnt) begin
                                                        tempBytesCnt <= 8'h0;
                                                        fsmState <= T0_PB;
                                                        {waitCardTx,waitTermTx}<=2'b10;
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                T0_PB: begin
                                        if(endOfRx) begin
                                                case(dataOut[7:4])
                                                        4'h6: begin
                                                                fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
                                                        end
                                                        4'h9: begin
                                                                fsmState <= T0_SW2;
                                                        end
                                                        default: begin
                                                                case(dataOut)
                                                                        tpduHeader[INS_I+:8]: begin//ACK
                                                                                fsmState <= T0_DATA;
                                                                                {waitCardTx,waitTermTx}<=2'b11;
                                                                        end
                                                                        ~tpduHeader[INS_I+:8]: begin//NACK
                                                                                fsmState <= T0_NACK_DATA;
                                                                                {waitCardTx,waitTermTx}<=2'b11;
                                                                        end
                                                                        default: begin //invalid
                                                                                //TODO
                                                                        end
                                                                endcase
                                                        end
                                                endcase
                                        end
                                end
                                T0_NACK_DATA: begin
                                        if(endOfRx) begin
                                                fsmState <= T0_PB;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                                tempBytesCnt <= tempBytesCnt+1;
                                        end
                                end
                                T0_SW1: begin
                                        if(endOfRx) begin
                                        //TODO:check != 60 but equal to 6x or 9x
                                                fsmState <= T0_SW2;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                        end
                                end
                                T0_SW2: begin
                                        if(endOfRx) begin
                                                fsmState <= T0_HEADER;
                                                {waitCardTx,waitTermTx}<=2'b01;
                                        end
                                end
                                T0_DATA: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
                                                        tempBytesCnt <= 0;
                                                        fsmState <= T0_SW1;
                                                        {waitCardTx,waitTermTx}<=2'b10;
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                        endcase
                end
        end
end
 
reg [1:0] txDir;
reg proto_cardTx;
reg proto_termTx;
always @(*) begin: protoComDirectionCombiBlock
        if(guardTime & ~isoSio)
                {proto_cardTx, proto_termTx}={txDir[0],txDir[1]};
        else
                {proto_cardTx, proto_termTx}={txDir[1],txDir[0]};
end
always @(posedge isoClk, negedge nReset) begin: protoComDirectionSeqBlock
        if(~nReset | ~run) begin
                txDir<=2'b00;
        end else begin
                if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
                        case({waitCardTx, waitTermTx})
                                2'b00: txDir<=2'b00;//no one should/is sending
                                2'b01: txDir<=2'b01;//terminal should/is sending
                                2'b10: txDir<=2'b10;//card should/is sending
                                2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
                        endcase
                end
        end
end
 
reg phy_cardTx;
reg phy_termTx;
always @(negedge isoSio, negedge nReset) begin: phyComDirectionBlock
        if(~nReset) begin
                phy_cardTx<=1'b0;
                phy_termTx<=1'b0;
        end else begin
                if(~isoSioTerm) begin
                        phy_cardTx<=1'b0;
                        phy_termTx<=1'b1;
                end else begin
                        phy_cardTx<=1'b1;
                        phy_termTx<=1'b0;
                end
        end
end
 
assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;
assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;
 
endmodule
`default_nettype wire
 

Line No.	Rev	Author	Line
1	11	acapola	`/*`
2			`Author: Sebastien Riou (acapola)`
3			`Creation date: 22:22:43 01/10/2011`
4
5			$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
6			$LastChangedBy: acapola $
7			$LastChangedRevision: 11 $
8			$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
9
10			`This file is under the BSD licence:`
11			`Copyright (c) 2011, Sebastien Riou`
12
13			`All rights reserved.`
14
15			`Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:`
16
17			`Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.`
18			`Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.`
19			`The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.`
20			`THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS`
21			`"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT`
22			`LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR`
23			`A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR`
24			`CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,`
25			`EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
26			`PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR`
27			`PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF`
28			`LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
29			`NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
30			`SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
31			`*/`
32	5	acapola	`default_nettype none
33
34	11	acapola
35	10	acapola	`module Iso7816_3_t0_analyzer`
36			`#(parameter DIVIDER_WIDTH = 1)`
37			`(`
38	5	acapola	`input wire nReset,`
39			`input wire clk,`
40	6	acapola	`input wire [DIVIDER_WIDTH-1:0] clkPerCycle,`
41	5	acapola	`input wire isoReset,`
42			`input wire isoClk,`
43			`input wire isoVdd,`
44	10	acapola	`input wire isoSioTerm,`
45			`input wire isoSioCard,`
46			`input wire useDirectionProbe,//if 1, isoSioTerm and isoSioCard must be connected to Iso7816_directionProbe outputs`
47	5	acapola	`output reg [3:0] fiCode,`
48			`output reg [3:0] diCode,`
49	6	acapola	`output wire [12:0] fi,`
50			`output wire [7:0] di,`
51			`output wire [12:0] cyclesPerEtu,`
52			`output wire [7:0] fMax,`
53	5	acapola	`output wire isActivated,`
54			`output wire tsReceived,`
55			`output wire tsError,`
56			`output wire useIndirectConvention,`
57			`output wire atrIsEarly,//high if TS received before 400 cycles after reset release`
58			`output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release`
59	6	acapola	`output reg [3:0] atrK,//number of historical bytes`
60			`output reg atrHasTck,`
61			`output reg atrCompleted,`
62	5	acapola	`output reg useT0,`
63			`output reg useT1,`
64			`output reg useT15,`
65			`output reg waitCardTx,`
66			`output reg waitTermTx,`
67	10	acapola	`output wire cardTx,`
68			`output wire termTx,`
69	5	acapola	`output wire guardTime,`
70			`output wire overrunError,`
71			`output wire frameError,`
72	7	acapola	`output reg [7:0] lastByte,`
73			`output reg [31:0] bytesCnt`
74	5	acapola	`);`
75	10	acapola
76			`wire isoSio = isoSioTerm & isoSioCard;`
77	5	acapola
78			`reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release`
79
80			`reg [7:0] buffer[256+5:0];`
81			`localparam CLA_I= 8*4;`
82			`localparam INS_I= 8*3;`
83			`localparam P1_I = 8*2;`
84			`localparam P2_I = 8*1;`
85			`localparam P3_I = 0;`
86			`reg [CLA_I+7:0] tpduHeader;`
87
88	7	acapola	`//wire COM_clk=isoClk;`
89			`//integer COM_errorCnt;`
90			`//wire txPending=1'b0;`
91			`//wire txRun=1'b0;`
92	5	acapola
93			`wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;`
94			`assign overrunErrorFlag = overrunError;`
95			`assign frameErrorFlag = frameError;`
96
97			`wire [7:0] rxData;`
98	7	acapola	`reg ackFlags;`
99	5	acapola
100	6	acapola	`wire msbFirst = useIndirectConvention;`
101			`wire sioHighValue = ~useIndirectConvention;`
102			`wire oddParity = 1'b0;`
103
104			`wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;`
105
106
107	7	acapola	//`include "ComRxDriverTasks.v"
108	5	acapola
109			`wire endOfRx;`
110
111	6	acapola	`wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte`
112	10	acapola	`wire [12:0] clocksPerBit = cyclesPerEtu-1;`
113	5	acapola	`RxCoreSelfContained #(`
114	6	acapola	`.DIVIDER_WIDTH(DIVIDER_WIDTH),`
115	7	acapola	`.CLOCK_PER_BIT_WIDTH(4'd13),`
116			`.PRECISE_STOP_BIT(1'b1))`
117	5	acapola	`rxCore (`
118			`.dataOut(rxData),`
119			`.overrunErrorFlag(overrunError),`
120			`.dataOutReadyFlag(bufferFull),`
121			`.frameErrorFlag(frameError),`
122			`.endOfRx(endOfRx),`
123			`.run(rxRun),`
124			`.startBit(rxStartBit),`
125			`.stopBit(guardTime),`
126			`.clkPerCycle(clkPerCycle),`
127	10	acapola	`.clocksPerBit(clocksPerBit),`
128	5	acapola	`.stopBit2(stopBit2),`
129			`.oddParity(oddParity),`
130			`.msbFirst(msbFirst),`
131	7	acapola	`.ackFlags(ackFlags),`
132	5	acapola	`.serialIn(isoSio),`
133	6	acapola	`.comClk(isoClk),`
134	5	acapola	`.clk(clk),`
135			`.nReset(nReset)`
136			`);`
137
138			`TsAnalyzer tsAnalyzer(`
139			`.nReset(nReset),`
140			`.isoReset(isoReset),`
141			`.isoClk(isoClk),`
142			`.isoVdd(isoVdd),`
143			`.isoSio(isoSio),`
144			`.endOfRx(endOfRx),`
145			`.rxData(rxData),`
146			`.isActivated(isActivated),`
147			`.tsReceived(tsReceived),`
148			`.tsError(tsError),`
149			`.atrIsEarly(atrIsEarly),`
150			`.atrIsLate(atrIsLate),`
151			`.useIndirectConvention(useIndirectConvention)`
152			`);`
153
154			`FiDiAnalyzer fiDiAnalyzer(`
155			`.fiCode(fiCode),`
156			`.diCode(diCode),`
157			`.fi(fi),`
158			`.di(di),`
159			`.cyclesPerEtu(cyclesPerEtu),`
160			`.fMax(fMax)`
161			`);`
162
163			`wire run = rxStartBit \| rxRun;`
164	6	acapola	`localparam ATR_T0 = 0;`
165			`localparam ATR_TDI = 1;`
166			`localparam ATR_HISTORICAL = 2;`
167			`localparam ATR_TCK = 3;`
168			`localparam T0_HEADER = 0;`
169	8	acapola	`localparam T0_HEADER_TPDU = 1;`
170			`localparam T0_PB = 2;`
171			`localparam T0_DATA = 3;`
172			`localparam T0_NACK_DATA = 4;`
173			`localparam T0_SW1 = 5;`
174			`localparam T0_SW2 = 6;`
175			`localparam T0_HEADER_PPS = 100;`
176
177	6	acapola	`integer fsmState;`
178
179			`reg [11:0] tdiStruct;`
180			`wire [3:0] tdiCnt;//i+1`
181			`wire [7:0] tdiData;//value of TDi`
182			`assign {tdiCnt,tdiData}=tdiStruct;`
183
184			`wire [1:0] nIfBytes;`
185			`HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));`
186	7	acapola	`reg [7:0] tempBytesCnt;`
187	6	acapola	`always @(posedge isoClk, negedge nReset) begin`
188	5	acapola	`if(~nReset) begin`
189	7	acapola	`lastByte<=8'b0;`
190			`ackFlags<=1'b0;`
191			`bytesCnt<=32'b0;`
192			`end else if(ackFlags) begin`
193			`ackFlags<=1'b0;`
194			`end else if(frameErrorFlag\|bufferFull) begin`
195			`lastByte<=dataOut;`
196			`ackFlags<=1'b1;`
197			`bytesCnt<=bytesCnt+1'b1;`
198			`end`
199			`end`
200			`always @(posedge isoClk, negedge nReset) begin`
201			`if(~nReset) begin`
202	5	acapola	`fiCode<=4'b0001;`
203			`diCode<=4'b0001;`
204	6	acapola	`useT0<=1'b1;`
205	5	acapola	`useT1<=1'b0;`
206			`useT15<=1'b0;`
207	8	acapola	`{waitCardTx,waitTermTx}<=2'b00;`
208	6	acapola	`fsmState<=ATR_TDI;`
209			`atrHasTck<=1'b0;`
210	7	acapola	`tempBytesCnt<=8'h0;`
211	6	acapola	`tdiStruct<=12'h0;`
212			`atrCompleted<=1'b0;`
213	8	acapola	`atrK<=4'b0;`
214	5	acapola	`end else if(isActivated) begin`
215			`if(~tsReceived) begin`
216	8	acapola	`{waitCardTx,waitTermTx}<=2'b10;`
217	5	acapola	`end else if(~atrCompleted) begin`
218	6	acapola	`//ATR analysis`
219			`case(fsmState)`
220			`ATR_TDI: begin`
221			`if(endOfRx) begin`
222	7	acapola	`if(tempBytesCnt==nIfBytes) begin //TDi bytes`
223			`tempBytesCnt <= 2'h0;`
224	6	acapola	`tdiStruct <= {tdiCnt+1,dataOut};`
225			`if(4'h0==tdiCnt) begin//this is T0`
226			`atrK <= dataOut[3:0];`
227			`fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :`
228			`(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;`
229			`end else begin//TDi, i from 1 to 15`
230			`fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :`
231			`(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;`
232			`end`
233	8	acapola	`if(12'h0=={dataOut,atrK}) begin`
234			`atrCompleted <= 1'b1;`
235			`{waitCardTx,waitTermTx}<=2'b01;`
236			`end`
237	6	acapola	`end else begin //TA, TB or TC bytes`
238			`//TODO: get relevant info`
239	7	acapola	`tempBytesCnt <= tempBytesCnt+1;`
240	6	acapola	`end`
241			`end`
242			`end`
243			`ATR_HISTORICAL: begin`
244			`if(endOfRx) begin`
245	7	acapola	`if(tempBytesCnt==atrK) begin`
246	8	acapola	`tempBytesCnt <= 8'h0;`
247			`if(atrHasTck) begin`
248			`fsmState <= ATR_TCK;`
249			`end else begin`
250			`atrCompleted <= ~atrHasTck;`
251			`{waitCardTx,waitTermTx}<=2'b10;`
252			`fsmState <= T0_HEADER;`
253			`end`
254	6	acapola	`end else begin`
255	7	acapola	`tempBytesCnt <= tempBytesCnt+1;`
256	6	acapola	`end`
257			`end`
258			`end`
259			`ATR_TCK: begin`
260			`if(endOfRx) begin`
261			`//TODO:check`
262			`atrCompleted <= 1'b1;`
263	8	acapola	`{waitCardTx,waitTermTx}<=2'b10;`
264	6	acapola	`fsmState <= T0_HEADER;`
265			`end`
266			`end`
267			`endcase`
268	5	acapola	`end else if(useT0) begin`
269			`//T=0 cmd/response monitoring state machine`
270	8	acapola	`case(fsmState)`
271			`T0_HEADER: begin`
272			`if(endOfRx) begin`
273			`tpduHeader[CLA_I+:8]<=dataOut;`
274			`tempBytesCnt <= 1;`
275			`if(8'hFF==dataOut)`
276			`fsmState <= T0_HEADER_PPS;//TODO`
277			`else`
278			`fsmState <= T0_HEADER_TPDU;`
279			`end`
280			`end`
281			`T0_HEADER_TPDU: begin`
282			`if(endOfRx) begin`
283			`tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;`
284			`if(4==tempBytesCnt) begin`
285			`tempBytesCnt <= 8'h0;`
286			`fsmState <= T0_PB;`
287			`{waitCardTx,waitTermTx}<=2'b10;`
288			`end else begin`
289			`tempBytesCnt <= tempBytesCnt+1;`
290			`end`
291			`end`
292			`end`
293			`T0_PB: begin`
294			`if(endOfRx) begin`
295			`case(dataOut[7:4])`
296			`4'h6: begin`
297			`fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;`
298			`end`
299			`4'h9: begin`
300			`fsmState <= T0_SW2;`
301			`end`
302			`default: begin`
303			`case(dataOut)`
304			`tpduHeader[INS_I+:8]: begin//ACK`
305			`fsmState <= T0_DATA;`
306			`{waitCardTx,waitTermTx}<=2'b11;`
307			`end`
308			`~tpduHeader[INS_I+:8]: begin//NACK`
309			`fsmState <= T0_NACK_DATA;`
310			`{waitCardTx,waitTermTx}<=2'b11;`
311			`end`
312			`default: begin //invalid`
313			`//TODO`
314			`end`
315			`endcase`
316			`end`
317			`endcase`
318			`end`
319			`end`
320			`T0_NACK_DATA: begin`
321			`if(endOfRx) begin`
322			`fsmState <= T0_PB;`
323			`{waitCardTx,waitTermTx}<=2'b10;`
324			`tempBytesCnt <= tempBytesCnt+1;`
325			`end`
326			`end`
327			`T0_SW1: begin`
328			`if(endOfRx) begin`
329			`//TODO:check != 60 but equal to 6x or 9x`
330			`fsmState <= T0_SW2;`
331			`{waitCardTx,waitTermTx}<=2'b10;`
332			`end`
333			`end`
334			`T0_SW2: begin`
335			`if(endOfRx) begin`
336			`fsmState <= T0_HEADER;`
337			`{waitCardTx,waitTermTx}<=2'b01;`
338			`end`
339			`end`
340			`T0_DATA: begin`
341			`if(endOfRx) begin`
342			`if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin`
343			`tempBytesCnt <= 0;`
344			`fsmState <= T0_SW1;`
345			`{waitCardTx,waitTermTx}<=2'b10;`
346			`end else begin`
347			`tempBytesCnt <= tempBytesCnt+1;`
348			`end`
349			`end`
350			`end`
351			`endcase`
352	5	acapola	`end`
353			`end`
354			`end`
355
356			`reg [1:0] txDir;`
357	10	acapola	`reg proto_cardTx;`
358			`reg proto_termTx;`
359			`always @(*) begin: protoComDirectionCombiBlock`
360	6	acapola	`if(guardTime & ~isoSio)`
361	10	acapola	`{proto_cardTx, proto_termTx}={txDir[0],txDir[1]};`
362	5	acapola	`else`
363	10	acapola	`{proto_cardTx, proto_termTx}={txDir[1],txDir[0]};`
364	5	acapola	`end`
365	10	acapola	`always @(posedge isoClk, negedge nReset) begin: protoComDirectionSeqBlock`
366	5	acapola	`if(~nReset \| ~run) begin`
367			`txDir<=2'b00;`
368			`end else begin`
369	6	acapola	`if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here`
370	5	acapola	`case({waitCardTx, waitTermTx})`
371	8	acapola	`2'b00: txDir<=2'b00;//no one should/is sending`
372			`2'b01: txDir<=2'b01;//terminal should/is sending`
373			`2'b10: txDir<=2'b10;//card should/is sending`
374			`2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)`
375	5	acapola	`endcase`
376			`end`
377			`end`
378			`end`
379	10	acapola
380			`reg phy_cardTx;`
381			`reg phy_termTx;`
382			`always @(negedge isoSio, negedge nReset) begin: phyComDirectionBlock`
383			`if(~nReset) begin`
384			`phy_cardTx<=1'b0;`
385			`phy_termTx<=1'b0;`
386			`end else begin`
387			`if(~isoSioTerm) begin`
388			`phy_cardTx<=1'b0;`
389			`phy_termTx<=1'b1;`
390			`end else begin`
391			`phy_cardTx<=1'b1;`
392			`phy_termTx<=1'b0;`
393			`end`
394			`end`
395			`end`
396
397			`assign cardTx = useDirectionProbe ? phy_cardTx : proto_cardTx;`
398			`assign termTx = useDirectionProbe ? phy_termTx : proto_termTx;`
399	5	acapola
400			`endmodule`
401	11	acapola	`default_nettype wire
402	5	acapola

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