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`timescale 1ns / 1ps
`default_nettype none
 
module Iso7816_3_t0_analyzer(
        input wire nReset,
        input wire clk,
        input wire [DIVIDER_WIDTH-1:0] clkPerCycle,
        input wire isoReset,
        input wire isoClk,
        input wire isoVdd,
        input wire isoSio,
        output reg [3:0] fiCode,
        output reg [3:0] diCode,
        output wire [12:0] fi,
        output wire [7:0] di,
        output wire [12:0] cyclesPerEtu,
        output wire [7:0] fMax,
        output wire isActivated,
        output wire tsReceived,
        output wire tsError,
        output wire useIndirectConvention,
        output wire atrIsEarly,//high if TS received before 400 cycles after reset release
        output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release
        output reg [3:0] atrK,//number of historical bytes
        output reg atrHasTck,
        output reg atrCompleted,
        output reg useT0,
        output reg useT1,
        output reg useT15,
        output reg waitCardTx,
        output reg waitTermTx,
        output reg cardTx,
        output reg termTx,
        output wire guardTime,
        output wire overrunError,
        output wire frameError,
        output reg [7:0] lastByte,
        output reg [31:0] bytesCnt
        );
parameter DIVIDER_WIDTH = 1;
 
reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release
 
reg [7:0] buffer[256+5:0];
localparam CLA_I= 8*4;
localparam INS_I= 8*3;
localparam P1_I = 8*2;
localparam P2_I = 8*1;
localparam P3_I = 0;
reg [CLA_I+7:0] tpduHeader;
 
//wire COM_clk=isoClk;
//integer COM_errorCnt;
//wire txPending=1'b0;
//wire txRun=1'b0;
 
wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
assign overrunErrorFlag = overrunError;
assign frameErrorFlag = frameError;
 
wire [7:0] rxData;
reg ackFlags;
 
wire msbFirst = useIndirectConvention;
wire sioHighValue = ~useIndirectConvention;
wire oddParity = 1'b0;
 
wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;
 
 
//`include "ComRxDriverTasks.v"
 
wire endOfRx;
 
wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte
 
RxCoreSelfContained #(
                .DIVIDER_WIDTH(DIVIDER_WIDTH),
                .CLOCK_PER_BIT_WIDTH(4'd13),
                .PRECISE_STOP_BIT(1'b1))
        rxCore (
    .dataOut(rxData),
    .overrunErrorFlag(overrunError),
    .dataOutReadyFlag(bufferFull),
    .frameErrorFlag(frameError),
    .endOfRx(endOfRx),
    .run(rxRun),
    .startBit(rxStartBit),
         .stopBit(guardTime),
    .clkPerCycle(clkPerCycle),
    .clocksPerBit(cyclesPerEtu-1),
    .stopBit2(stopBit2),
    .oddParity(oddParity),
    .msbFirst(msbFirst),
         .ackFlags(ackFlags),
    .serialIn(isoSio),
    .comClk(isoClk),
    .clk(clk),
    .nReset(nReset)
    );
 
TsAnalyzer tsAnalyzer(
        .nReset(nReset),
        .isoReset(isoReset),
        .isoClk(isoClk),
        .isoVdd(isoVdd),
        .isoSio(isoSio),
        .endOfRx(endOfRx),
        .rxData(rxData),
        .isActivated(isActivated),
        .tsReceived(tsReceived),
        .tsError(tsError),
        .atrIsEarly(atrIsEarly),
        .atrIsLate(atrIsLate),
        .useIndirectConvention(useIndirectConvention)
        );
 
FiDiAnalyzer fiDiAnalyzer(
        .fiCode(fiCode),
        .diCode(diCode),
        .fi(fi),
        .di(di),
        .cyclesPerEtu(cyclesPerEtu),
        .fMax(fMax)
        );
 
wire run = rxStartBit | rxRun;
localparam ATR_T0 = 0;
localparam ATR_TDI = 1;
localparam ATR_HISTORICAL = 2;
localparam ATR_TCK = 3;
localparam T0_HEADER = 0;
localparam T0_HEADER_TPDU = 1;
localparam T0_PB = 2;
localparam T0_DATA = 3;
localparam T0_NACK_DATA = 4;
localparam T0_SW1 = 5;
localparam T0_SW2 = 6;
localparam T0_HEADER_PPS = 100;
 
integer fsmState;
 
reg [11:0] tdiStruct;
wire [3:0] tdiCnt;//i+1
wire [7:0] tdiData;//value of TDi
assign {tdiCnt,tdiData}=tdiStruct;
 
wire [1:0] nIfBytes;
HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));
reg [7:0] tempBytesCnt;
always @(posedge isoClk, negedge nReset) begin
        if(~nReset) begin
                lastByte<=8'b0;
                ackFlags<=1'b0;
                bytesCnt<=32'b0;
        end else if(ackFlags) begin
                ackFlags<=1'b0;
        end else if(frameErrorFlag|bufferFull) begin
                lastByte<=dataOut;
                ackFlags<=1'b1;
                bytesCnt<=bytesCnt+1'b1;
        end
end
always @(posedge isoClk, negedge nReset) begin
        if(~nReset) begin
                fiCode<=4'b0001;
                diCode<=4'b0001;
                useT0<=1'b1;
                useT1<=1'b0;
                useT15<=1'b0;
                {waitCardTx,waitTermTx}<=2'b00;
                fsmState<=ATR_TDI;
                atrHasTck<=1'b0;
                tempBytesCnt<=8'h0;
                tdiStruct<=12'h0;
                atrCompleted<=1'b0;
                atrK<=4'b0;
        end else if(isActivated) begin
                if(~tsReceived) begin
                        {waitCardTx,waitTermTx}<=2'b10;
                end else if(~atrCompleted) begin
                        //ATR analysis
                        case(fsmState)
                                ATR_TDI: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==nIfBytes) begin //TDi bytes
                                                        tempBytesCnt <= 2'h0;
                                                        tdiStruct <= {tdiCnt+1,dataOut};
                                                        if(4'h0==tdiCnt) begin//this is T0
                                                                atrK <= dataOut[3:0];
                                                                fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
                                                                                                (4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
                                                        end else begin//TDi, i from 1 to 15
                                                                fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
                                                                                                (4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
                                                        end
                                                        if(12'h0=={dataOut,atrK}) begin
                                                                atrCompleted <= 1'b1;
                                                                {waitCardTx,waitTermTx}<=2'b01;
                                                        end
                                                end else begin //TA, TB or TC bytes
                                                        //TODO: get relevant info
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                ATR_HISTORICAL: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==atrK) begin
                                                        tempBytesCnt <= 8'h0;
                                                        if(atrHasTck) begin
                                                                fsmState <= ATR_TCK;
                                                        end else begin
                                                                atrCompleted <= ~atrHasTck;
                                                                {waitCardTx,waitTermTx}<=2'b10;
                                                                fsmState <= T0_HEADER;
                                                        end
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                ATR_TCK: begin
                                        if(endOfRx) begin
                                        //TODO:check
                                                atrCompleted <= 1'b1;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                                fsmState <= T0_HEADER;
                                        end
                                end
                        endcase
                end else if(useT0) begin
                        //T=0 cmd/response monitoring state machine
                        case(fsmState)
                                T0_HEADER: begin
                                        if(endOfRx) begin
                                                tpduHeader[CLA_I+:8]<=dataOut;
                                                tempBytesCnt <= 1;
                                                if(8'hFF==dataOut)
                                                        fsmState <= T0_HEADER_PPS;//TODO
                                                else
                                                        fsmState <= T0_HEADER_TPDU;
                                        end
                                end
                                T0_HEADER_TPDU: begin
                                        if(endOfRx) begin
                                                tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;
                                                if(4==tempBytesCnt) begin
                                                        tempBytesCnt <= 8'h0;
                                                        fsmState <= T0_PB;
                                                        {waitCardTx,waitTermTx}<=2'b10;
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                                T0_PB: begin
                                        if(endOfRx) begin
                                                case(dataOut[7:4])
                                                        4'h6: begin
                                                                fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;
                                                        end
                                                        4'h9: begin
                                                                fsmState <= T0_SW2;
                                                        end
                                                        default: begin
                                                                case(dataOut)
                                                                        tpduHeader[INS_I+:8]: begin//ACK
                                                                                fsmState <= T0_DATA;
                                                                                {waitCardTx,waitTermTx}<=2'b11;
                                                                        end
                                                                        ~tpduHeader[INS_I+:8]: begin//NACK
                                                                                fsmState <= T0_NACK_DATA;
                                                                                {waitCardTx,waitTermTx}<=2'b11;
                                                                        end
                                                                        default: begin //invalid
                                                                                //TODO
                                                                        end
                                                                endcase
                                                        end
                                                endcase
                                        end
                                end
                                T0_NACK_DATA: begin
                                        if(endOfRx) begin
                                                fsmState <= T0_PB;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                                tempBytesCnt <= tempBytesCnt+1;
                                        end
                                end
                                T0_SW1: begin
                                        if(endOfRx) begin
                                        //TODO:check != 60 but equal to 6x or 9x
                                                fsmState <= T0_SW2;
                                                {waitCardTx,waitTermTx}<=2'b10;
                                        end
                                end
                                T0_SW2: begin
                                        if(endOfRx) begin
                                                fsmState <= T0_HEADER;
                                                {waitCardTx,waitTermTx}<=2'b01;
                                        end
                                end
                                T0_DATA: begin
                                        if(endOfRx) begin
                                                if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
                                                        tempBytesCnt <= 0;
                                                        fsmState <= T0_SW1;
                                                        {waitCardTx,waitTermTx}<=2'b10;
                                                end else begin
                                                        tempBytesCnt <= tempBytesCnt+1;
                                                end
                                        end
                                end
                        endcase
                end
        end
end
 
reg [1:0] txDir;
always @(*) begin: errorSigDirectionBlock
        if(guardTime & ~isoSio)
                {cardTx, termTx}={txDir[0],txDir[1]};
        else
                {cardTx, termTx}={txDir[1],txDir[0]};
end
always @(posedge isoClk, negedge nReset) begin: comDirectionBlock
        if(~nReset | ~run) begin
                txDir<=2'b00;
        end else begin
                if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here
                        case({waitCardTx, waitTermTx})
                                2'b00: txDir<=2'b00;//no one should/is sending
                                2'b01: txDir<=2'b01;//terminal should/is sending
                                2'b10: txDir<=2'b10;//card should/is sending
                                2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)
                        endcase
                end
        end
end
 
endmodule
 

Line No.	Rev	Author	Line
1	5	acapola	`timescale 1ns / 1ps
2			`default_nettype none
3
4			`module Iso7816_3_t0_analyzer(`
5			`input wire nReset,`
6			`input wire clk,`
7	6	acapola	`input wire [DIVIDER_WIDTH-1:0] clkPerCycle,`
8	5	acapola	`input wire isoReset,`
9			`input wire isoClk,`
10			`input wire isoVdd,`
11			`input wire isoSio,`
12			`output reg [3:0] fiCode,`
13			`output reg [3:0] diCode,`
14	6	acapola	`output wire [12:0] fi,`
15			`output wire [7:0] di,`
16			`output wire [12:0] cyclesPerEtu,`
17			`output wire [7:0] fMax,`
18	5	acapola	`output wire isActivated,`
19			`output wire tsReceived,`
20			`output wire tsError,`
21			`output wire useIndirectConvention,`
22			`output wire atrIsEarly,//high if TS received before 400 cycles after reset release`
23			`output wire atrIsLate,//high if TS is still not received after 40000 cycles after reset release`
24	6	acapola	`output reg [3:0] atrK,//number of historical bytes`
25			`output reg atrHasTck,`
26			`output reg atrCompleted,`
27	5	acapola	`output reg useT0,`
28			`output reg useT1,`
29			`output reg useT15,`
30			`output reg waitCardTx,`
31			`output reg waitTermTx,`
32	6	acapola	`output reg cardTx,`
33			`output reg termTx,`
34	5	acapola	`output wire guardTime,`
35			`output wire overrunError,`
36			`output wire frameError,`
37	7	acapola	`output reg [7:0] lastByte,`
38			`output reg [31:0] bytesCnt`
39	5	acapola	`);`
40	6	acapola	`parameter DIVIDER_WIDTH = 1;`
41	5	acapola
42			`reg [8:0] tsCnt;//counter to start ATR 400 cycles after reset release`
43
44			`reg [7:0] buffer[256+5:0];`
45			`localparam CLA_I= 8*4;`
46			`localparam INS_I= 8*3;`
47			`localparam P1_I = 8*2;`
48			`localparam P2_I = 8*1;`
49			`localparam P3_I = 0;`
50			`reg [CLA_I+7:0] tpduHeader;`
51
52	7	acapola	`//wire COM_clk=isoClk;`
53			`//integer COM_errorCnt;`
54			`//wire txPending=1'b0;`
55			`//wire txRun=1'b0;`
56	5	acapola
57			`wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;`
58			`assign overrunErrorFlag = overrunError;`
59			`assign frameErrorFlag = frameError;`
60
61			`wire [7:0] rxData;`
62	7	acapola	`reg ackFlags;`
63	5	acapola
64	6	acapola	`wire msbFirst = useIndirectConvention;`
65			`wire sioHighValue = ~useIndirectConvention;`
66			`wire oddParity = 1'b0;`
67
68			`wire [7:0] dataOut = sioHighValue ? rxData : ~rxData;`
69
70
71	7	acapola	//`include "ComRxDriverTasks.v"
72	5	acapola
73			`wire endOfRx;`
74
75	6	acapola	`wire stopBit2 = useT0;//1 if com use 2 stop bits --> 12 ETU / byte`
76	5	acapola
77			`RxCoreSelfContained #(`
78	6	acapola	`.DIVIDER_WIDTH(DIVIDER_WIDTH),`
79	7	acapola	`.CLOCK_PER_BIT_WIDTH(4'd13),`
80			`.PRECISE_STOP_BIT(1'b1))`
81	5	acapola	`rxCore (`
82			`.dataOut(rxData),`
83			`.overrunErrorFlag(overrunError),`
84			`.dataOutReadyFlag(bufferFull),`
85			`.frameErrorFlag(frameError),`
86			`.endOfRx(endOfRx),`
87			`.run(rxRun),`
88			`.startBit(rxStartBit),`
89			`.stopBit(guardTime),`
90			`.clkPerCycle(clkPerCycle),`
91	7	acapola	`.clocksPerBit(cyclesPerEtu-1),`
92	5	acapola	`.stopBit2(stopBit2),`
93			`.oddParity(oddParity),`
94			`.msbFirst(msbFirst),`
95	7	acapola	`.ackFlags(ackFlags),`
96	5	acapola	`.serialIn(isoSio),`
97	6	acapola	`.comClk(isoClk),`
98	5	acapola	`.clk(clk),`
99			`.nReset(nReset)`
100			`);`
101
102			`TsAnalyzer tsAnalyzer(`
103			`.nReset(nReset),`
104			`.isoReset(isoReset),`
105			`.isoClk(isoClk),`
106			`.isoVdd(isoVdd),`
107			`.isoSio(isoSio),`
108			`.endOfRx(endOfRx),`
109			`.rxData(rxData),`
110			`.isActivated(isActivated),`
111			`.tsReceived(tsReceived),`
112			`.tsError(tsError),`
113			`.atrIsEarly(atrIsEarly),`
114			`.atrIsLate(atrIsLate),`
115			`.useIndirectConvention(useIndirectConvention)`
116			`);`
117
118			`FiDiAnalyzer fiDiAnalyzer(`
119			`.fiCode(fiCode),`
120			`.diCode(diCode),`
121			`.fi(fi),`
122			`.di(di),`
123			`.cyclesPerEtu(cyclesPerEtu),`
124			`.fMax(fMax)`
125			`);`
126
127			`wire run = rxStartBit \| rxRun;`
128	6	acapola	`localparam ATR_T0 = 0;`
129			`localparam ATR_TDI = 1;`
130			`localparam ATR_HISTORICAL = 2;`
131			`localparam ATR_TCK = 3;`
132			`localparam T0_HEADER = 0;`
133	8	acapola	`localparam T0_HEADER_TPDU = 1;`
134			`localparam T0_PB = 2;`
135			`localparam T0_DATA = 3;`
136			`localparam T0_NACK_DATA = 4;`
137			`localparam T0_SW1 = 5;`
138			`localparam T0_SW2 = 6;`
139			`localparam T0_HEADER_PPS = 100;`
140
141	6	acapola	`integer fsmState;`
142
143			`reg [11:0] tdiStruct;`
144			`wire [3:0] tdiCnt;//i+1`
145			`wire [7:0] tdiData;//value of TDi`
146			`assign {tdiCnt,tdiData}=tdiStruct;`
147
148			`wire [1:0] nIfBytes;`
149			`HammingWeight hammingWeight(.dataIn(tdiData[7:4]), .hammingWeight(nIfBytes));`
150	7	acapola	`reg [7:0] tempBytesCnt;`
151	6	acapola	`always @(posedge isoClk, negedge nReset) begin`
152	5	acapola	`if(~nReset) begin`
153	7	acapola	`lastByte<=8'b0;`
154			`ackFlags<=1'b0;`
155			`bytesCnt<=32'b0;`
156			`end else if(ackFlags) begin`
157			`ackFlags<=1'b0;`
158			`end else if(frameErrorFlag\|bufferFull) begin`
159			`lastByte<=dataOut;`
160			`ackFlags<=1'b1;`
161			`bytesCnt<=bytesCnt+1'b1;`
162			`end`
163			`end`
164			`always @(posedge isoClk, negedge nReset) begin`
165			`if(~nReset) begin`
166	5	acapola	`fiCode<=4'b0001;`
167			`diCode<=4'b0001;`
168	6	acapola	`useT0<=1'b1;`
169	5	acapola	`useT1<=1'b0;`
170			`useT15<=1'b0;`
171	8	acapola	`{waitCardTx,waitTermTx}<=2'b00;`
172	6	acapola	`fsmState<=ATR_TDI;`
173			`atrHasTck<=1'b0;`
174	7	acapola	`tempBytesCnt<=8'h0;`
175	6	acapola	`tdiStruct<=12'h0;`
176			`atrCompleted<=1'b0;`
177	8	acapola	`atrK<=4'b0;`
178	5	acapola	`end else if(isActivated) begin`
179			`if(~tsReceived) begin`
180	8	acapola	`{waitCardTx,waitTermTx}<=2'b10;`
181	5	acapola	`end else if(~atrCompleted) begin`
182	6	acapola	`//ATR analysis`
183			`case(fsmState)`
184			`ATR_TDI: begin`
185			`if(endOfRx) begin`
186	7	acapola	`if(tempBytesCnt==nIfBytes) begin //TDi bytes`
187			`tempBytesCnt <= 2'h0;`
188	6	acapola	`tdiStruct <= {tdiCnt+1,dataOut};`
189			`if(4'h0==tdiCnt) begin//this is T0`
190			`atrK <= dataOut[3:0];`
191			`fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :`
192			`(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;`
193			`end else begin//TDi, i from 1 to 15`
194			`fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :`
195			`(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;`
196			`end`
197	8	acapola	`if(12'h0=={dataOut,atrK}) begin`
198			`atrCompleted <= 1'b1;`
199			`{waitCardTx,waitTermTx}<=2'b01;`
200			`end`
201	6	acapola	`end else begin //TA, TB or TC bytes`
202			`//TODO: get relevant info`
203	7	acapola	`tempBytesCnt <= tempBytesCnt+1;`
204	6	acapola	`end`
205			`end`
206			`end`
207			`ATR_HISTORICAL: begin`
208			`if(endOfRx) begin`
209	7	acapola	`if(tempBytesCnt==atrK) begin`
210	8	acapola	`tempBytesCnt <= 8'h0;`
211			`if(atrHasTck) begin`
212			`fsmState <= ATR_TCK;`
213			`end else begin`
214			`atrCompleted <= ~atrHasTck;`
215			`{waitCardTx,waitTermTx}<=2'b10;`
216			`fsmState <= T0_HEADER;`
217			`end`
218	6	acapola	`end else begin`
219	7	acapola	`tempBytesCnt <= tempBytesCnt+1;`
220	6	acapola	`end`
221			`end`
222			`end`
223			`ATR_TCK: begin`
224			`if(endOfRx) begin`
225			`//TODO:check`
226			`atrCompleted <= 1'b1;`
227	8	acapola	`{waitCardTx,waitTermTx}<=2'b10;`
228	6	acapola	`fsmState <= T0_HEADER;`
229			`end`
230			`end`
231			`endcase`
232	5	acapola	`end else if(useT0) begin`
233			`//T=0 cmd/response monitoring state machine`
234	8	acapola	`case(fsmState)`
235			`T0_HEADER: begin`
236			`if(endOfRx) begin`
237			`tpduHeader[CLA_I+:8]<=dataOut;`
238			`tempBytesCnt <= 1;`
239			`if(8'hFF==dataOut)`
240			`fsmState <= T0_HEADER_PPS;//TODO`
241			`else`
242			`fsmState <= T0_HEADER_TPDU;`
243			`end`
244			`end`
245			`T0_HEADER_TPDU: begin`
246			`if(endOfRx) begin`
247			`tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]<=dataOut;`
248			`if(4==tempBytesCnt) begin`
249			`tempBytesCnt <= 8'h0;`
250			`fsmState <= T0_PB;`
251			`{waitCardTx,waitTermTx}<=2'b10;`
252			`end else begin`
253			`tempBytesCnt <= tempBytesCnt+1;`
254			`end`
255			`end`
256			`end`
257			`T0_PB: begin`
258			`if(endOfRx) begin`
259			`case(dataOut[7:4])`
260			`4'h6: begin`
261			`fsmState <= (4'h0==dataOut[3:0]) ? T0_PB : T0_SW2;`
262			`end`
263			`4'h9: begin`
264			`fsmState <= T0_SW2;`
265			`end`
266			`default: begin`
267			`case(dataOut)`
268			`tpduHeader[INS_I+:8]: begin//ACK`
269			`fsmState <= T0_DATA;`
270			`{waitCardTx,waitTermTx}<=2'b11;`
271			`end`
272			`~tpduHeader[INS_I+:8]: begin//NACK`
273			`fsmState <= T0_NACK_DATA;`
274			`{waitCardTx,waitTermTx}<=2'b11;`
275			`end`
276			`default: begin //invalid`
277			`//TODO`
278			`end`
279			`endcase`
280			`end`
281			`endcase`
282			`end`
283			`end`
284			`T0_NACK_DATA: begin`
285			`if(endOfRx) begin`
286			`fsmState <= T0_PB;`
287			`{waitCardTx,waitTermTx}<=2'b10;`
288			`tempBytesCnt <= tempBytesCnt+1;`
289			`end`
290			`end`
291			`T0_SW1: begin`
292			`if(endOfRx) begin`
293			`//TODO:check != 60 but equal to 6x or 9x`
294			`fsmState <= T0_SW2;`
295			`{waitCardTx,waitTermTx}<=2'b10;`
296			`end`
297			`end`
298			`T0_SW2: begin`
299			`if(endOfRx) begin`
300			`fsmState <= T0_HEADER;`
301			`{waitCardTx,waitTermTx}<=2'b01;`
302			`end`
303			`end`
304			`T0_DATA: begin`
305			`if(endOfRx) begin`
306			`if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin`
307			`tempBytesCnt <= 0;`
308			`fsmState <= T0_SW1;`
309			`{waitCardTx,waitTermTx}<=2'b10;`
310			`end else begin`
311			`tempBytesCnt <= tempBytesCnt+1;`
312			`end`
313			`end`
314			`end`
315			`endcase`
316	5	acapola	`end`
317			`end`
318			`end`
319
320			`reg [1:0] txDir;`
321			`always @(*) begin: errorSigDirectionBlock`
322	6	acapola	`if(guardTime & ~isoSio)`
323			`{cardTx, termTx}={txDir[0],txDir[1]};`
324	5	acapola	`else`
325	6	acapola	`{cardTx, termTx}={txDir[1],txDir[0]};`
326	5	acapola	`end`
327	6	acapola	`always @(posedge isoClk, negedge nReset) begin: comDirectionBlock`
328	5	acapola	`if(~nReset \| ~run) begin`
329			`txDir<=2'b00;`
330			`end else begin`
331	6	acapola	`if(~guardTime) begin //{waitCardTx, waitTermTx} is updated during stop bits so we hold current value here`
332	5	acapola	`case({waitCardTx, waitTermTx})`
333	8	acapola	`2'b00: txDir<=2'b00;//no one should/is sending`
334			`2'b01: txDir<=2'b01;//terminal should/is sending`
335			`2'b10: txDir<=2'b10;//card should/is sending`
336			`2'b11: txDir<=2'b11;//either card OR terminal should/is sending (we just don't know)`
337	5	acapola	`endcase`
338			`end`
339			`end`
340			`end`
341
342			`endmodule`
343

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