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1 16 jguarin200
-- Author : Julian Andres Guarin Reyes.
2
-- Project : JART, Just Another Ray Tracer.
3
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
4
 
5
-- This code was entirely written by Julian Andres Guarin Reyes.
6
-- The following code is licensed under GNU Public License
7
-- http://www.gnu.org/licenses/gpl-3.0.txt.
8
 
9
 -- This file is part of JART (Just Another Ray Tracer).
10
 
11
    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
12
    -- it under the terms of the GNU General Public License as published by
13
    -- the Free Software Foundation, either version 3 of the License, or
14
    -- (at your option) any later version.
15
 
16
    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
17
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
18
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
    -- GNU General Public License for more details.
20
 
21
    -- You should have received a copy of the GNU General Public License
22
    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.
23
 
24
-- 16X50M Intersection Tests    
25
 
26
library ieee;
27
use ieee.std_logic_1164.all;
28
 
29 64 jguarin200
 
30
 
31
 
32 16 jguarin200
package powerGrid is
33 64 jguarin200
 
34
        -- R2 for size and width
35
        type SIZE_WIDTH is array (0 to 1) of integer;
36
        type DUPLA is array (0 to 2) of SIZE_WIDTH;
37
 
38
        -- Tuple for widths
39
        type WARRAY is array (0 to 2) of integer;
40
 
41
        -- Index 
42
        constant SZINDEX: integer :=0;
43
        constant WDINDEX: integer :=1;
44
 
45
        -- Register file for spheres.
46
        -- OP1 : One sphere output per clock.
47
        -- OP2 : Two sphere output per clock.
48
        -- OP4 : Four sphere output per clock.
49
        constant OP4            : integer := 2;
50
        constant OP2            : integer := 1;
51
        constant OP1            : integer := 0;
52
 
53
        constant SZALFA         : integer := 1;
54
        constant SZBETA         : integer := 2;
55
 
56
        constant BUSW           : integer := 32;
57
        constant HBUSW          : integer := 18;
58
 
59
        -- Size and Width.
60
        constant REGSZADD       : WARRAY := (12,11,10);
61
        constant CIDSZADD       : DUPLA := ((1,0),(2,1),(4,2));
62
 
63
 
64
 
65
 
66
        -- Register blocks.....
67
 
68
        -- 8 x 512 x 32 
69
        component bt81
70
                port
71
                (
72
                address         : in std_logic_vector (11 downto 0);
73
                clken           : in std_logic ;
74
                clock           : in std_logic ;
75
                data            : in std_logic_vector (31 downto 0);
76
                wren            : in std_logic ;
77
                q                       : out std_logic_vector (31 downto 0)
78
                );
79
        end component;
80
 
81
        -- 4 x 512 x 32 
82
        component bt41
83
                port
84
                (
85
                address         : in std_logic_vector (10 downto 0);
86
                clken           : in std_logic ;
87
                clock           : in std_logic ;
88
                data            : in std_logic_vector (31 downto 0);
89
                wren            : in std_logic ;
90
                q                       : out std_logic_vector (31 downto 0)
91
                );
92
        end component;
93
 
94
        -- 2 x 512 x 32 
95
        component bt21
96
                port
97
                (
98
                address         : in std_logic_vector (9 downto 0);
99
                clken           : in std_logic ;
100
                clock           : in std_logic ;
101
                data            : in std_logic_vector (31 downto 0);
102
                wren            : in std_logic ;
103
                q                       : out std_logic_vector (31 downto 0)
104
                );
105
        end component;
106
 
107
        -- 1 x 512 x 32 
108
        component bt41
109
                port
110
                (
111
                address         : in std_logic_vector (8 downto 0);
112
                clken           : in std_logic ;
113
                clock           : in std_logic ;
114
                data            : in std_logic_vector (31 downto 0);
115
                wren            : in std_logic ;
116
                q                       : out std_logic_vector (31 downto 0)
117
                );
118
        end component;
119
 
120
        -- 8 x 512 x 32 
121
        component bt84
122
                port
123
                (
124
                address         : in std_logic_vector (11 downto 0);
125
                clken           : in std_logic ;
126
                clock           : in std_logic ;
127
                data            : in std_logic_vector (17 downto 0);
128
                wren            : in std_logic ;
129
                q                       : out std_logic_vector (17 downto 0)
130
                );
131
        end component;
132
 
133
        -- 4 x 512 x 32 
134
        component bt44
135
                port
136
                (
137
                address         : in std_logic_vector (10 downto 0);
138
                clken           : in std_logic ;
139
                clock           : in std_logic ;
140
                data            : in std_logic_vector (17 downto 0);
141
                wren            : in std_logic ;
142
                q                       : out std_logic_vector (17 downto 0)
143
                );
144
        end component;
145
 
146
        -- 2 x 512 x 32 
147
        component bt24
148
                port
149
                (
150
                address         : in std_logic_vector (9 downto 0);
151
                clken           : in std_logic ;
152
                clock           : in std_logic ;
153
                data            : in std_logic_vector (17 downto 0);
154
                wren            : in std_logic ;
155
                q                       : out std_logic_vector (17 downto 0)
156
                );
157
        end component;
158
 
159
        -- 1 x 512 x 18 
160
        component bt14
161
                port
162
                (
163
                address         : in std_logic_vector (8 downto 0);
164
                clken           : in std_logic ;
165
                clock           : in std_logic ;
166
                data            : in std_logic_vector (17 downto 0);
167
                wren            : in std_logic ;
168
                q                       : out std_logic_vector (17 downto 0)
169
                );
170
        end component;
171
 
172
        -- Register type 1 .
173
        component r1
174
                port (
175
 
176
 
177
                        clk, ena: in std_logic; -- The usual control signals.
178
 
179
                        wen             : in std_logic_vector   (3 downto 0);
180
                        add             : in std_logic_vector   (8 downto 0);
181
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
182
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
183
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
184
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
185
                        K               : out std_logic_vector  (BUSW-1 downto 0)
186
                );
187
        end component;
188
        -- Register type 2 .
189
        component r2
190
                port (
191
 
192
 
193
                        clk, ena: in std_logic; -- The usual control signals.
194
 
195
                        wen             : in std_logic_vector   (3 downto 0);
196
                        add             : in std_logic_vector   (9 downto 0);
197
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
198
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
199
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
200
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
201
                        K               : out std_logic_vector  (BUSW-1 downto 0)
202
                );
203
        end component;
204
        -- Register type 4
205
        component r4
206
                port (
207
 
208
 
209
                        clk, ena: in std_logic; -- The usual control signals.
210
 
211
                        wen             : in std_logic_vector   (3 downto 0);
212
                        add             : in std_logic_vector   (10 downto 0);
213
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
214
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
215
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
216
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
217
                        K               : out std_logic_vector  (BUSW-1 downto 0)
218
                );
219
        end component;-- Register type 8.
220
        component r8
221
                port (
222
 
223
 
224
                        clk, ena: in std_logic; -- The usual control signals.
225
 
226
                        wen             : in std_logic_vector   (3 downto 0);
227
                        add             : in std_logic_vector   (11 downto 0);
228
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
229
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
230
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
231
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
232
                        K               : out std_logic_vector  (BUSW-1 downto 0)
233
                );
234
        end component;
235
 
236
 
237
        -- Register Option mode 1
238
        component rop1
239
                generic (
240
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
241
                );
242
                port (
243
 
244
 
245
                        clk, ena: in std_logic; -- The usual control signals.
246
                        wen             : in std_logic_vector   (3 downto 0);
247
                        add             : in std_logic_vector   (REGSZADD(OP1)-SZMODE downto 0);
248
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
249
                        Vx              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
250
                        Vy              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
251
                        Vz              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
252
                        K               : out std_logic_vector  (2*BUSW-1 downto 0)
253
                );
254
 
255
        end component;
256
 
257
        -- Register Option mode 2
258
        component rop2
259
                generic (
260
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
261
                );
262
                port (
263
 
264
 
265
                        clk, ena: in std_logic; -- The usual control signals.
266
                        wen             : in std_logic_vector   (7 downto 0);
267
                        add             : in std_logic_vector   (REGSZADD(OP2)-SZMODE downto 0);
268
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
269
                        Vx              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
270
                        Vy              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
271
                        Vz              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
272
                        K               : out std_logic_vector  (2*BUSW-1 downto 0)
273
                );
274
 
275
        end component;
276
 
277
        -- Register Option mode 2
278
        component rop4
279
                generic (
280
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
281
                );
282
                port (
283
 
284
 
285
                        clk, ena: in std_logic; -- The usual control signals.
286
                        wen             : in std_logic_vector   (15 downto 0);
287
                        add             : in std_logic_vector   (REGSZADD(OP4)-SZMODE downto 0);
288
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
289
                        Vx              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
290
                        Vy              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
291
                        Vz              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
292
                        K               : out std_logic_vector  (4*BUSW-1 downto 0)
293
                );
294
 
295
        end component;
296
 
297
 
298
        -- Sphere Register Block
299
        component sphereRegisterBlock
300
                generic (
301
 
302
                        OPMODE  : integer := OP4;               -- By default push out 4 spheres at same time.
303
                        SZMODE  : integer := SZBETA;    -- By default the max sphere numbers is 2048, but could be 4096 with SZALFA.
304
 
305
                );
306
                port (
307
 
308
 
309
                        clk, ena: in std_logic; -- The usual control signals.
310
 
311
                        wen             : in std_logic_vector   (CIDSZADD(OPMODE(SZINDEX))*4-1 downto 0);        -- Write enable signals
312
                        add             : in std_logic_vector   (REGSZADD(OPMODE)-SZMODE  downto 0);             -- Address bus
313
 
314
                        datain  : in std_logic_vector   (BUSW-1 downto 0);       -- incoming data from 32 bits width bus.
315
 
316
                        Vx              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
317
                        Vy              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
318
                        Vz              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
319
                        K               : out std_logic_vector  (OPMODE*BUSW-1 downto 0)
320
 
321
                );
322
 
323
        end entity;
324
 
325 58 jguarin200
        -- A scan flip flop, aka selectable input ff.
326
        component scanFF
327
                generic (
328
                W       : integer := 8);
329
                port    (
330 61 jguarin200
                clk,rst,ena,sel         : in std_logic; -- The usual  control signals
331 58 jguarin200
 
332 61 jguarin200
                d0,d1   : in std_logic_vector (W-1 downto 0);    -- The two operands.
333
                q               : out std_logic_vector (W-1 downto 0)    -- The selected data.
334 58 jguarin200
 
335
                );
336
        end component;
337 33 jguarin200
        --A one stage pipe (1 Clk) a+b+c with w width bits in input as well as output.
338
        --As a fixed signed addtion we have:
339
        -- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
340
        -- A(15,20)*A(15,20) = A(15,20). (This component format)
341
 
342 22 jguarin200
        component p1ax
343 33 jguarin200
                generic (
344
                -- The width of the operands and result.
345
                W               : integer := 36 );
346
                port    (
347
                -- The usual control signals.
348
                clk             :        in std_logic;
349
                rst             :        in std_logic;
350 61 jguarin200
                enable  :        in std_logic;
351 33 jguarin200
 
352
                -- Operand A.
353
                dataa           :        in std_logic_vector(W-1 downto 0);
354
                -- Operand B.
355
                datab           :        in std_logic_vector(W-1 downto 0);
356
                -- Operand C
357
                datac           :        in std_logic_vector(W-1 downto 0);
358
                -- Result.
359
                result          :        out std_logic_vector(W-1 downto 0)
360 22 jguarin200
                );
361
        end component;
362
 
363
        -- A 1 stage pipe 18x18 multiplier. On Cycle III devices is a M-R (Multiplier, Register). (Should be generated using a synthesis tool....).
364 33 jguarin200
        -- As a fixed signed multiplication we have :
365
        -- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
366
        -- A(7,10)*A(7,10) = A(15,20). (This component format)
367
 
368 22 jguarin200
        component p1m18
369
                port    (
370 33 jguarin200
                -- Asynchronous clear signal.
371
                aclr            : in std_logic ;
372
                -- The usual control signals.
373
                clken           : in std_logic ;
374
                clock           : in std_logic ;
375
 
376
                -- Factor A.
377
                dataa           : in std_logic_vector (17 downto 0);
378
                -- Factor B.
379
                datab           : in std_logic_vector (17 downto 0);
380
                -- Product.
381
                result          : out std_logic_vector (35 downto 0)
382 22 jguarin200
                );
383
        end component;
384
 
385 33 jguarin200
        -- Signed "less than". dataa < datab
386 16 jguarin200
        component sl32
387
                port    (
388 33 jguarin200
 
389
                dataa   : in std_logic_vector (31 downto 0);
390
                datab   : in std_logic_vector (31 downto 0);
391
                AlB             : out std_logic
392
 
393 16 jguarin200
                );
394
                end component;
395
 
396 33 jguarin200
        -- Signed "greater than". dataa >= datab.
397 16 jguarin200
        component sge32
398
                port    (
399 33 jguarin200
 
400
                dataa   : in std_logic_vector (31 downto 0);
401
                datab   : in std_logic_vector (31 downto 0);
402
                AgeB    : out std_logic
403
 
404 16 jguarin200
                );
405
                end component;
406
 
407
 
408 22 jguarin200
        -- Dot Product Calculation Cell. 
409
        -- A 4 side cell along with an upper side. 
410
        -- V input flows through V output using a data flipflop, so turning V output in the next cell on the next row V Input. V input also flows upwards into the dotproduct 3 stage pipeline. 
411
        -- D input flows through D output using a data flipflop, so turning D output in the next column cell. D input also flows upwards into the dotproduct 3 stage. 
412 16 jguarin200
        component dotCell
413 40 jguarin200
                generic (
414
 
415
                -- Register V?, by default register the pass of V to the next grid. This should be NO when using a single grid cube or in the last grid of the grid array.
416
                RV      : string := "yes";
417 33 jguarin200
                -- Actual Level Width
418 40 jguarin200
                W0      : integer := 18;
419 33 jguarin200
                -- Next Level Width
420 40 jguarin200
                W1      : integer := 32);
421 33 jguarin200
 
422 16 jguarin200
                port    (
423 33 jguarin200
                --The usual control signals
424
                clk                     : in std_logic;
425
                rst                     : in std_logic;
426 16 jguarin200
 
427 33 jguarin200
                -- This bit controls when the sphere center goes to the next row.
428
                nxtSphere       : in std_logic;
429
                -- This bit controls when the ray goes to the next column.
430
                nxtRay          : in std_logic;
431 22 jguarin200
 
432 33 jguarin200
                -- First Side.
433 40 jguarin200
                vxInput         : in std_logic_vector(W0-1 downto 0);
434
                vyInput         : in std_logic_vector(W0-1 downto 0);
435
                vzInput         : in std_logic_vector(W0-1 downto 0);
436 16 jguarin200
 
437 33 jguarin200
                -- Second Side (Opposite to the first one)
438 40 jguarin200
                vxOutput        : out std_logic_vector(W0-1 downto 0);
439
                vyOutput        : out std_logic_vector(W0-1 downto 0);
440
                vzOutput        : out std_logic_vector(W0-1 downto 0);
441 16 jguarin200
 
442 33 jguarin200
                -- Third Side (Perpendicular to the first and second ones)
443 40 jguarin200
                dxInput         : in std_logic_vector(W0-1 downto 0);
444
                dyInput         : in std_logic_vector(W0-1 downto 0);
445
                dzInput         : in std_logic_vector(W0-1 downto 0);
446 16 jguarin200
 
447 33 jguarin200
                --Fourth Side (Opposite to the third one)
448 64 jguarin200
                dxOutput        : out std_logic_vector(W0-1 downto 0);
449
                dyOutput        : out std_logic_vector(W0-1 downto 0);
450
                dzOutput        : out std_logic_vector(W0-1 downto 0);
451 16 jguarin200
 
452 33 jguarin200
                --Fifth Side (Going to the floor right upstairs!)
453 40 jguarin200
                vdOutput        : out std_logic_vector(W1-1 downto 0) -- Dot product.
454 16 jguarin200
 
455 22 jguarin200
                );
456 16 jguarin200
        end component;
457
 
458
        -- K discriminant comparison.
459 33 jguarin200
        -- The vdinput value is the calculation of the ray and the column's sphere dot product. This value should be compared to a sphere constant in order to find out whether the ray intersects
460
        -- or not the sphere. If vdinput is grather or equal than kinput there's an intersection or else when vdinput is less than kinput. If there's an intersection the block sets vdinput at vdoutput,
461
        -- whenever there's no intersection the output is asserted with the maximum positive distance in 32 bits : 0x7fffffff.
462 16 jguarin200
        component kComparisonCell
463 40 jguarin200
                generic (
464
                RK      : string        := "yes";
465
                W1      : integer       := 32
466 16 jguarin200
                );
467 40 jguarin200
                port (
468
                clk,rst         : in std_logic;
469
                scanOut         : in std_logic; -- This signals overrides the 'signed greater or equal than' internal function and allows vdinput to flow upwards.
470
                nxtSphere       : in std_logic; -- Controls when the sphere goes to the next Row. 
471
                pipeOn          : in std_logic; -- Enables / Disable the upwarding flow.
472
                kinput          : in std_logic_vector (W1-1 downto 0);
473
                koutputhor      : out std_logic_vector (W1-1 downto 0);
474
                koutputver      : out std_logic_vector (W1-1 downto 0);  -- K input  flowing to the next floor upstairs (but waits one clock). 
475
                vdinput         : in std_logic_vector (W1-1 downto 0);   -- V.D input.
476
                vdoutput        : out std_logic_vector (W1-1 downto 0)   -- Selected dot product.
477
                );
478 22 jguarin200
        end component;
479 33 jguarin200
        -- Minimun distance Comparison.
480
        -- The reference value, refvd, is the ray minimal intersection distance calculated in the moment of the comparison. 
481
        -- The column value, colvd, is the column sphere and ray intersection distance (if any or else the maximum distance is asserted).
482
 
483
 
484
        component dComparisonCell
485
                generic (
486
                -- V.D, minDistance and selectD Width 
487 40 jguarin200
                W1              : integer := 32;
488 33 jguarin200
                -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
489 40 jguarin200
                IDW     : integer := 2;
490 33 jguarin200
                -- Column Id
491
                idCol   : integer := 0
492
                );
493
                port    (
494
                -- The usual control signals.           
495 40 jguarin200
                clk, rst, pipeOn : in std_logic;
496
 
497 61 jguarin200
 
498
                intd    : in    std_logic;
499
                intq    : out   std_logic;
500 33 jguarin200
                -- This is the reference column identification input.
501 40 jguarin200
                cIdd    : in    std_logic_vector (IDW - 1 downto 0);
502 33 jguarin200
                -- This is the result column identification output.
503 61 jguarin200
                cIdq    : out   std_logic_vector (IDW - 1 downto 0);
504
                refk    : in    std_logic_vector (W1 - 1 downto 0); -- This is the columns sphere constant
505
                colk    : in    std_logic_vector (W1 - 1 downto 0); -- This is the reference sphere constant
506
                selk    : out   std_logic_vector (W1 - 1 downto 0); -- This is the selected sphere constant              
507 33 jguarin200
                -- This is the reference projection incoming from the previous cell.
508 40 jguarin200
                refvd   : in    std_logic_vector (W1 - 1 downto 0);
509 33 jguarin200
                -- This is the sphere position over the ray traced vector projection.
510 40 jguarin200
                colvd   : in    std_logic_vector (W1 - 1 downto 0);
511 33 jguarin200
                -- This is the smallest value between refvd and colvd.
512 40 jguarin200
                selvd   : out   std_logic_vector (W1 - 1 downto 0)
513 33 jguarin200
                );
514
        end component;
515
 
516
        component floor0Row
517
                generic (
518
                -- Floor Level Width (V.D width)
519 40 jguarin200
                W1 : integer := 32;
520 33 jguarin200
                -- Vector input Width           
521 40 jguarin200
                W0 : integer := 18;
522 33 jguarin200
                -- Number of Colums
523 40 jguarin200
                C       : integer := 4
524 33 jguarin200
        );
525
        port (
526
                -- The usual control signals. nxtRay should be 0 whenever I want to stop the entire machine.
527
                clk, rst, nxtRay : in std_logic;
528 16 jguarin200
 
529 33 jguarin200
                -- Clk, Rst, the usual control signals.
530
                -- enabled, the machine is running when this input is set.
531
                -- enabled, all the counters begin again.
532 40 jguarin200
                nxtSphere : in std_logic_vector (C-1 downto 0);
533 33 jguarin200
 
534
 
535
                -- Input Values. 
536
                -- The ray input vector.
537 40 jguarin200
                iRayx: in std_logic_vector (W0 - 1 downto 0);
538
                iRayy: in std_logic_vector (W0 - 1 downto 0);
539
                iRayz: in std_logic_vector (W0 - 1 downto 0);
540 33 jguarin200
 
541
                -- The spheres x position (sphere centers) input vectors.
542 40 jguarin200
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
543 33 jguarin200
                -- The spheres y position (sphere centers) input vectors.
544 40 jguarin200
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
545 33 jguarin200
                -- The spheres z position (sphere centers) input vectors.
546 40 jguarin200
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
547 33 jguarin200
                -- The spheres x position (sphere centers) output vectors.
548 40 jguarin200
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
549 33 jguarin200
                -- The spheres y positions (sphere centes) output vectors.
550 40 jguarin200
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
551 33 jguarin200
                -- The spheres z positions (sphere centers) output vectors.             
552 40 jguarin200
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
553 33 jguarin200
 
554
                -- Output Values
555
                -- The ray output vector.
556 40 jguarin200
                oRayx: out std_logic_vector (W0 - 1 downto 0);
557
                oRayy: out std_logic_vector (W0 - 1 downto 0);
558
                oRayz: out std_logic_vector (W0 - 1 downto 0);
559 33 jguarin200
 
560
                -- The dot product result from each dot prod cell.
561 40 jguarin200
                vdOutput : out std_logic_vector (W1*C - 1 downto 0)
562 33 jguarin200
                );
563
        end component;
564
 
565
        -- In this level the V.D results from floor 0 are compared whether they are greater or equal than column's sphere K constants, in order to find if there's an intersection per column or not.
566
        -- When any comparison is true, meaning VD value greater or equal than K, the outgoing value to floor2 level is the same VD, if not the outgoing value is 0x7fffffff (the maximum)
567
        -- distance value.
568
 
569
        component floor1Row
570
        generic (
571
 
572
                -- Vector input Width   
573 40 jguarin200
                W1 : integer := 32;
574 33 jguarin200
                -- Number of Colums
575 40 jguarin200
                C       : integer := 4
576 33 jguarin200
        );
577
        port (
578
 
579
                -- Input Control Signals, pipe on is one when raysr going on. 
580
                clk, rst        : in std_logic;
581
                pipeOn          : in std_logic;
582
 
583
                -- Clk, Rst, the usual control signals.
584 40 jguarin200
                nxtSphere       : in std_logic_vector (C-1 downto 0);
585 33 jguarin200
 
586
                -- VD Input / Output.
587 40 jguarin200
                vdInput : in std_logic_vector (W1*C-1 downto 0);
588
                vdOutput: out std_logic_vector (W1*C-1 downto 0);
589 33 jguarin200
 
590
                -- K Input / Output.
591 40 jguarin200
                kInput  : in std_logic_vector (W1*C - 1 downto 0);
592
                kOutput : out std_logic_vector (W1*C - 1 downto 0)
593 33 jguarin200
        );
594
        end component;
595
 
596
        -- This level takes the -on the moment smalles distance-- value per ray in the extreme left, and starts making comparisons from left to right, one comparison each clock and so on, searching for the smallest V.D value in the row incomung from the floor1 level. When the ray has finished crossing throguh all the spheres in the scene, the row extreme right value will be the smallest V.D found along with an ID of the sphere intersected. This is the goal of the intersection architecture : to find out which is the closest sphere intersected by a particular ray. 
597
 
598
        component floor2Row
599
        generic (
600
                -- Vector input Width
601 40 jguarin200
                W1 : integer := 32;
602 33 jguarin200
                -- ID Column width
603 40 jguarin200
                IDW : integer := 2;
604 33 jguarin200
                -- Number of Colums
605 40 jguarin200
                C       : integer := 4
606 33 jguarin200
        );
607
        port (
608
                -- Input Control Signal
609
                -- Clk, Rst, the usual control signals.
610
                clk, rst, pipeOn: in std_logic;
611
 
612
                -- Input Values
613
                -- Reference VD, the "at the moment" smallest VD sphere ray projection value.
614 40 jguarin200
                refvd   : in std_logic_vector (W1-1 downto 0);
615 33 jguarin200
 
616
                -- The smallest VD, value found.
617 40 jguarin200
                selvd   : out std_logic_vector (W1-1 downto 0);
618 33 jguarin200
 
619
                -- The column's sphere ray projection value.
620 40 jguarin200
                colvd   : in std_logic_vector (W1*C-1 downto 0);
621 33 jguarin200
                -- The smallest VD projection value column id.
622 40 jguarin200
                colid   : out std_logic_vector (IDW-1 downto 0);
623 33 jguarin200
                -- The intersection signal (1 on intersection else 0).
624
                inter   : out std_logic
625
        );
626
        end component;
627
 
628
        component rayxsphereGrid
629
        generic (
630
                -- Width of Column identificator.
631
                IDW     : integer := 2;
632
                -- Number of Columns.
633
                C       : integer := 4;
634
                -- Input rays width.
635
                W0      : integer := 18;
636
                -- Dot products and spheres constant width
637 40 jguarin200
                W1      : integer := 32
638 33 jguarin200
 
639
                );
640
        port (
641
                -- The usual control signals.
642
                clk,rst         : in std_logic;
643
 
644
                -- Grid, rays and sphere flow through control signals.
645
                pipeOn          : in std_logic;
646
                nxtSphere       : in std_logic_vector (C-1 downto 0);
647
 
648
                -- R-F0
649
                -- Input Values. 
650
                -- The ray input vector.
651
                iRayx: in std_logic_vector (W0 - 1 downto 0);
652
                iRayy: in std_logic_vector (W0 - 1 downto 0);
653
                iRayz: in std_logic_vector (W0 - 1 downto 0);
654
                -- The spheres x position (sphere centers) input vectors.
655
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
656
                -- The spheres y position (sphere centers) input vectors.
657
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
658
                -- The spheres z position (sphere centers) input vectors.
659
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
660
                -- The spheres x position (sphere centers) output vectors.
661
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
662
                -- The spheres y positions (sphere centes) output vectors.
663
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
664
                -- The spheres z positions (sphere centers) output vectors.             
665
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
666
                -- Output Values
667
                -- The ray output vector.
668
                oRayx: out std_logic_vector (W0 - 1 downto 0);
669
                oRayy: out std_logic_vector (W0 - 1 downto 0);
670
                oRayz: out std_logic_vector (W0 - 1 downto 0);
671
 
672
                -- R-F1
673
                -- K Input / Output.
674
                kInput  : in std_logic_vector (C*W1 - 1 downto 0);
675 40 jguarin200
                kOutput : out std_logic_vector (C*W1 - 1 downto 0);
676 33 jguarin200
 
677
                --R-F2
678
                -- Input Values
679
                refvd   : in std_logic_vector (W1-1 downto 0);
680
                selvd   : out std_logic_vector (W1-1 downto 0);
681
                colid   : out std_logic_vector (IDW-1 downto 0);
682
                inter   : out std_logic
683
                );
684
        end component;
685
        component gridCube
686
        generic (
687
                -- Depth
688
                D       : integer := 4;
689
                -- ID width.
690
                IDW     : integer := 2;
691
                -- Number of Columns.
692
                C       : integer := 4;
693
                -- Input rays width.
694
                W0      : integer := 18;
695
                -- Dot products and spheres constant width
696 40 jguarin200
                W1      : integer := 32
697 33 jguarin200
 
698
                );
699
        port (
700
                        -- The usual control signals.
701
                clk,rst : in std_logic;
702
 
703
                -- Grid, rays and sphere flow through control signals.
704
                pipeOn                  : in std_logic;
705
                -- The same column nxtSphere signal control..... regardless the Cube Depth.
706
                nxtSphere               : in std_logic_vector (C-1 downto 0);
707
 
708
                -- R-F0
709
                -- Input Values. 
710
                -- The ray input vector. 
711
                iRayx: in std_logic_vector (D*W0 - 1 downto 0);
712
                iRayy: in std_logic_vector (D*W0 - 1 downto 0);
713
                iRayz: in std_logic_vector (D*W0 - 1 downto 0);
714
                -- The spheres x position (sphere centers) input vectors.
715
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
716
                -- The spheres y position (sphere centers) input vectors.
717
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
718
                -- The spheres z position (sphere centers) input vectors.
719
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
720
                -- The spheres x position (sphere centers) output vectors.
721
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
722
                -- The spheres y positions (sphere centes) output vectors.
723
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
724
                -- The spheres z positions (sphere centers) output vectors.             
725
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
726
                -- Output Values
727
                -- The ray output vector.
728
                oRayx: out std_logic_vector (D*W0 - 1 downto 0);
729
                oRayy: out std_logic_vector (D*W0 - 1 downto 0);
730
                oRayz: out std_logic_vector (D*W0 - 1 downto 0);
731
 
732
                -- R-F1
733
                -- K Input / Output.
734
                kInput  : in std_logic_vector (C*W1 - 1 downto 0);
735 40 jguarin200
                kOutput : out std_logic_vector (C*W1 - 1 downto 0);
736 33 jguarin200
 
737
                --R-F2
738
                -- Input Values
739
                refvd   : in std_logic_vector (D*W1-1 downto 0);
740
                selvd   : out std_logic_vector (D*W1-1 downto 0);
741
                colid   : out std_logic_vector (D*IDW-1 downto 0);
742
                inter   : out std_logic_vector (D-1 downto 0)
743
                );
744
        end component;
745 22 jguarin200
end powerGrid;

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