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1 16 jguarin200
-- Author : Julian Andres Guarin Reyes.
2
-- Project : JART, Just Another Ray Tracer.
3
-- email : jguarin2002 at gmail.com, j.guarin at javeriana.edu.co
4
 
5
-- This code was entirely written by Julian Andres Guarin Reyes.
6
-- The following code is licensed under GNU Public License
7
-- http://www.gnu.org/licenses/gpl-3.0.txt.
8
 
9
 -- This file is part of JART (Just Another Ray Tracer).
10
 
11
    -- JART (Just Another Ray Tracer) is free software: you can redistribute it and/or modify
12
    -- it under the terms of the GNU General Public License as published by
13
    -- the Free Software Foundation, either version 3 of the License, or
14
    -- (at your option) any later version.
15
 
16
    -- JART (Just Another Ray Tracer) is distributed in the hope that it will be useful,
17
    -- but WITHOUT ANY WARRANTY; without even the implied warranty of
18
    -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19
    -- GNU General Public License for more details.
20
 
21
    -- You should have received a copy of the GNU General Public License
22
    -- along with JART (Just Another Ray Tracer).  If not, see <http://www.gnu.org/licenses/>.
23
 
24
-- 16X50M Intersection Tests    
25
 
26
library ieee;
27
use ieee.std_logic_1164.all;
28
 
29 64 jguarin200
 
30
 
31
 
32 16 jguarin200
package powerGrid is
33 64 jguarin200
 
34
        -- R2 for size and width
35 69 jguarin200
        type SIZE_WIDTH is array (integer,integer) of integer;
36
        type DUPLA is array (0 to 2,1 downto 0) of integer;
37 64 jguarin200
 
38
        -- Tuple for widths
39
        type WARRAY is array (0 to 2) of integer;
40
 
41
        -- Index 
42 69 jguarin200
        constant SZINDEX: integer :=0;   -- Size Description Index.
43
        constant WDINDEX: integer :=1;  -- Width description Index.
44 64 jguarin200
 
45
        -- Register file for spheres.
46
        -- OP1 : One sphere output per clock.
47
        -- OP2 : Two sphere output per clock.
48
        -- OP4 : Four sphere output per clock.
49
        constant OP4            : integer := 2;
50
        constant OP2            : integer := 1;
51
        constant OP1            : integer := 0;
52
 
53
        constant SZALFA         : integer := 1;
54
        constant SZBETA         : integer := 2;
55
 
56 69 jguarin200
        constant DBUSW          : integer := 64;
57 64 jguarin200
        constant BUSW           : integer := 32;
58
        constant HBUSW          : integer := 18;
59
 
60 69 jguarin200
        -- Size and Width depending upon the number of spheres to push out in one clock (OP1= One sphere, OP2 = Two spheres, OP4= Four spheres).
61 64 jguarin200
        constant REGSZADD       : WARRAY := (12,11,10);
62
        constant CIDSZADD       : DUPLA := ((1,0),(2,1),(4,2));
63
 
64
 
65
 
66
 
67
        -- Register blocks.....
68
 
69
        -- 8 x 512 x 32 
70
        component bt81
71
                port
72
                (
73
                address         : in std_logic_vector (11 downto 0);
74
                clken           : in std_logic ;
75
                clock           : in std_logic ;
76
                data            : in std_logic_vector (31 downto 0);
77
                wren            : in std_logic ;
78
                q                       : out std_logic_vector (31 downto 0)
79
                );
80
        end component;
81
 
82
        -- 4 x 512 x 32 
83
        component bt41
84
                port
85
                (
86
                address         : in std_logic_vector (10 downto 0);
87
                clken           : in std_logic ;
88
                clock           : in std_logic ;
89
                data            : in std_logic_vector (31 downto 0);
90
                wren            : in std_logic ;
91
                q                       : out std_logic_vector (31 downto 0)
92
                );
93
        end component;
94
 
95
        -- 2 x 512 x 32 
96
        component bt21
97
                port
98
                (
99
                address         : in std_logic_vector (9 downto 0);
100
                clken           : in std_logic ;
101
                clock           : in std_logic ;
102
                data            : in std_logic_vector (31 downto 0);
103
                wren            : in std_logic ;
104
                q                       : out std_logic_vector (31 downto 0)
105
                );
106
        end component;
107
 
108
        -- 1 x 512 x 32 
109 66 jguarin200
        component bt11
110 64 jguarin200
                port
111
                (
112
                address         : in std_logic_vector (8 downto 0);
113
                clken           : in std_logic ;
114
                clock           : in std_logic ;
115
                data            : in std_logic_vector (31 downto 0);
116
                wren            : in std_logic ;
117
                q                       : out std_logic_vector (31 downto 0)
118
                );
119
        end component;
120
 
121 67 jguarin200
        -- 8 x 512 x 18 
122 64 jguarin200
        component bt84
123
                port
124
                (
125
                address         : in std_logic_vector (11 downto 0);
126
                clken           : in std_logic ;
127
                clock           : in std_logic ;
128
                data            : in std_logic_vector (17 downto 0);
129
                wren            : in std_logic ;
130
                q                       : out std_logic_vector (17 downto 0)
131
                );
132
        end component;
133
 
134 66 jguarin200
        -- 4 x 512 x 18 
135 64 jguarin200
        component bt44
136
                port
137
                (
138
                address         : in std_logic_vector (10 downto 0);
139
                clken           : in std_logic ;
140
                clock           : in std_logic ;
141
                data            : in std_logic_vector (17 downto 0);
142
                wren            : in std_logic ;
143
                q                       : out std_logic_vector (17 downto 0)
144
                );
145
        end component;
146
 
147 66 jguarin200
        -- 2 x 512 x 18 
148 64 jguarin200
        component bt24
149
                port
150
                (
151
                address         : in std_logic_vector (9 downto 0);
152
                clken           : in std_logic ;
153
                clock           : in std_logic ;
154
                data            : in std_logic_vector (17 downto 0);
155
                wren            : in std_logic ;
156
                q                       : out std_logic_vector (17 downto 0)
157
                );
158
        end component;
159
 
160
        -- 1 x 512 x 18 
161
        component bt14
162
                port
163
                (
164
                address         : in std_logic_vector (8 downto 0);
165
                clken           : in std_logic ;
166
                clock           : in std_logic ;
167
                data            : in std_logic_vector (17 downto 0);
168
                wren            : in std_logic ;
169
                q                       : out std_logic_vector (17 downto 0)
170
                );
171
        end component;
172
 
173
        -- Register type 1 .
174
        component r1
175
                port (
176
 
177
 
178
                        clk, ena: in std_logic; -- The usual control signals.
179
 
180
                        wen             : in std_logic_vector   (3 downto 0);
181
                        add             : in std_logic_vector   (8 downto 0);
182
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
183
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
184
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
185
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
186
                        K               : out std_logic_vector  (BUSW-1 downto 0)
187
                );
188
        end component;
189
        -- Register type 2 .
190
        component r2
191
                port (
192
 
193
 
194
                        clk, ena: in std_logic; -- The usual control signals.
195
 
196
                        wen             : in std_logic_vector   (3 downto 0);
197
                        add             : in std_logic_vector   (9 downto 0);
198
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
199
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
200
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
201
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
202
                        K               : out std_logic_vector  (BUSW-1 downto 0)
203
                );
204
        end component;
205
        -- Register type 4
206
        component r4
207
                port (
208
 
209
 
210
                        clk, ena: in std_logic; -- The usual control signals.
211
 
212
                        wen             : in std_logic_vector   (3 downto 0);
213
                        add             : in std_logic_vector   (10 downto 0);
214
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
215
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
216
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
217
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
218
                        K               : out std_logic_vector  (BUSW-1 downto 0)
219
                );
220
        end component;-- Register type 8.
221
        component r8
222
                port (
223
 
224
 
225
                        clk, ena: in std_logic; -- The usual control signals.
226
 
227
                        wen             : in std_logic_vector   (3 downto 0);
228
                        add             : in std_logic_vector   (11 downto 0);
229
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
230
                        Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
231
                        Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
232
                        Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
233
                        K               : out std_logic_vector  (BUSW-1 downto 0)
234
                );
235
        end component;
236
 
237
 
238
        -- Register Option mode 1
239
        component rop1
240
                generic (
241
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
242
                );
243
                port (
244
 
245
 
246
                        clk, ena: in std_logic; -- The usual control signals.
247
                        wen             : in std_logic_vector   (3 downto 0);
248
                        add             : in std_logic_vector   (REGSZADD(OP1)-SZMODE downto 0);
249
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
250
                        Vx              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
251
                        Vy              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
252
                        Vz              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
253
                        K               : out std_logic_vector  (2*BUSW-1 downto 0)
254
                );
255
 
256
        end component;
257
 
258
        -- Register Option mode 2
259
        component rop2
260
                generic (
261
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
262
                );
263
                port (
264
 
265
 
266
                        clk, ena: in std_logic; -- The usual control signals.
267
                        wen             : in std_logic_vector   (7 downto 0);
268
                        add             : in std_logic_vector   (REGSZADD(OP2)-SZMODE downto 0);
269
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
270
                        Vx              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
271
                        Vy              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
272
                        Vz              : out std_logic_vector  (2*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
273
                        K               : out std_logic_vector  (2*BUSW-1 downto 0)
274
                );
275
 
276
        end component;
277
 
278
        -- Register Option mode 2
279
        component rop4
280
                generic (
281
                        SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
282
                );
283
                port (
284
 
285
 
286
                        clk, ena: in std_logic; -- The usual control signals.
287
                        wen             : in std_logic_vector   (15 downto 0);
288
                        add             : in std_logic_vector   (REGSZADD(OP4)-SZMODE downto 0);
289
                        datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
290
                        Vx              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
291
                        Vy              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
292
                        Vz              : out std_logic_vector  (4*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
293
                        K               : out std_logic_vector  (4*BUSW-1 downto 0)
294
                );
295
 
296
        end component;
297
 
298
 
299
        -- Sphere Register Block
300
        component sphereRegisterBlock
301
                generic (
302
 
303
                        OPMODE  : integer := OP4;               -- By default push out 4 spheres at same time.
304 69 jguarin200
                        SZMODE  : integer := SZBETA             -- By default the max sphere numbers is 2048, but could be 4096 with SZALFA.
305
 
306
 
307 64 jguarin200
                );
308
                port (
309
 
310
 
311
                        clk, ena: in std_logic; -- The usual control signals.
312
 
313 69 jguarin200
                        wen             : in std_logic_vector   (CIDSZADD(OP4,SZINDEX)-1 downto 0);      -- Write enable signals
314 64 jguarin200
                        add             : in std_logic_vector   (REGSZADD(OPMODE)-SZMODE  downto 0);             -- Address bus
315
 
316
                        datain  : in std_logic_vector   (BUSW-1 downto 0);       -- incoming data from 32 bits width bus.
317
 
318
                        Vx              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
319
                        Vy              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
320
                        Vz              : out std_logic_vector  (OPMODE*HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
321
                        K               : out std_logic_vector  (OPMODE*BUSW-1 downto 0)
322
 
323
                );
324
 
325 69 jguarin200
        end component;
326 64 jguarin200
 
327 58 jguarin200
        -- A scan flip flop, aka selectable input ff.
328
        component scanFF
329
                generic (
330
                W       : integer := 8);
331
                port    (
332 61 jguarin200
                clk,rst,ena,sel         : in std_logic; -- The usual  control signals
333 58 jguarin200
 
334 61 jguarin200
                d0,d1   : in std_logic_vector (W-1 downto 0);    -- The two operands.
335
                q               : out std_logic_vector (W-1 downto 0)    -- The selected data.
336 58 jguarin200
 
337
                );
338
        end component;
339 33 jguarin200
        --A one stage pipe (1 Clk) a+b+c with w width bits in input as well as output.
340
        --As a fixed signed addtion we have:
341
        -- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
342
        -- A(15,20)*A(15,20) = A(15,20). (This component format)
343
 
344 22 jguarin200
        component p1ax
345 33 jguarin200
                generic (
346
                -- The width of the operands and result.
347
                W               : integer := 36 );
348
                port    (
349
                -- The usual control signals.
350
                clk             :        in std_logic;
351
                rst             :        in std_logic;
352 61 jguarin200
                enable  :        in std_logic;
353 33 jguarin200
 
354
                -- Operand A.
355
                dataa           :        in std_logic_vector(W-1 downto 0);
356
                -- Operand B.
357
                datab           :        in std_logic_vector(W-1 downto 0);
358
                -- Operand C
359
                datac           :        in std_logic_vector(W-1 downto 0);
360
                -- Result.
361
                result          :        out std_logic_vector(W-1 downto 0)
362 22 jguarin200
                );
363
        end component;
364
 
365
        -- A 1 stage pipe 18x18 multiplier. On Cycle III devices is a M-R (Multiplier, Register). (Should be generated using a synthesis tool....).
366 33 jguarin200
        -- As a fixed signed multiplication we have :
367
        -- A(B,C) ====> B+C SIGNED BITS FORMAT : 1 bit for sign, B bits for integer part, C bits for decimal part. (FORMAT)
368
        -- A(7,10)*A(7,10) = A(15,20). (This component format)
369
 
370 22 jguarin200
        component p1m18
371
                port    (
372 33 jguarin200
                -- Asynchronous clear signal.
373
                aclr            : in std_logic ;
374
                -- The usual control signals.
375
                clken           : in std_logic ;
376
                clock           : in std_logic ;
377
 
378
                -- Factor A.
379
                dataa           : in std_logic_vector (17 downto 0);
380
                -- Factor B.
381
                datab           : in std_logic_vector (17 downto 0);
382
                -- Product.
383
                result          : out std_logic_vector (35 downto 0)
384 22 jguarin200
                );
385
        end component;
386
 
387 33 jguarin200
        -- Signed "less than". dataa < datab
388 16 jguarin200
        component sl32
389
                port    (
390 33 jguarin200
 
391
                dataa   : in std_logic_vector (31 downto 0);
392
                datab   : in std_logic_vector (31 downto 0);
393
                AlB             : out std_logic
394
 
395 16 jguarin200
                );
396
                end component;
397
 
398 33 jguarin200
        -- Signed "greater than". dataa >= datab.
399 16 jguarin200
        component sge32
400
                port    (
401 33 jguarin200
 
402
                dataa   : in std_logic_vector (31 downto 0);
403
                datab   : in std_logic_vector (31 downto 0);
404
                AgeB    : out std_logic
405
 
406 16 jguarin200
                );
407
                end component;
408
 
409
 
410 22 jguarin200
        -- Dot Product Calculation Cell. 
411
        -- A 4 side cell along with an upper side. 
412
        -- V input flows through V output using a data flipflop, so turning V output in the next cell on the next row V Input. V input also flows upwards into the dotproduct 3 stage pipeline. 
413
        -- D input flows through D output using a data flipflop, so turning D output in the next column cell. D input also flows upwards into the dotproduct 3 stage. 
414 16 jguarin200
        component dotCell
415 40 jguarin200
                generic (
416
 
417
                -- Register V?, by default register the pass of V to the next grid. This should be NO when using a single grid cube or in the last grid of the grid array.
418
                RV      : string := "yes";
419 33 jguarin200
                -- Actual Level Width
420 40 jguarin200
                W0      : integer := 18;
421 33 jguarin200
                -- Next Level Width
422 40 jguarin200
                W1      : integer := 32);
423 33 jguarin200
 
424 16 jguarin200
                port    (
425 33 jguarin200
                --The usual control signals
426
                clk                     : in std_logic;
427
                rst                     : in std_logic;
428 16 jguarin200
 
429 33 jguarin200
                -- This bit controls when the sphere center goes to the next row.
430
                nxtSphere       : in std_logic;
431
                -- This bit controls when the ray goes to the next column.
432
                nxtRay          : in std_logic;
433 22 jguarin200
 
434 33 jguarin200
                -- First Side.
435 40 jguarin200
                vxInput         : in std_logic_vector(W0-1 downto 0);
436
                vyInput         : in std_logic_vector(W0-1 downto 0);
437
                vzInput         : in std_logic_vector(W0-1 downto 0);
438 16 jguarin200
 
439 33 jguarin200
                -- Second Side (Opposite to the first one)
440 40 jguarin200
                vxOutput        : out std_logic_vector(W0-1 downto 0);
441
                vyOutput        : out std_logic_vector(W0-1 downto 0);
442
                vzOutput        : out std_logic_vector(W0-1 downto 0);
443 16 jguarin200
 
444 33 jguarin200
                -- Third Side (Perpendicular to the first and second ones)
445 40 jguarin200
                dxInput         : in std_logic_vector(W0-1 downto 0);
446
                dyInput         : in std_logic_vector(W0-1 downto 0);
447
                dzInput         : in std_logic_vector(W0-1 downto 0);
448 16 jguarin200
 
449 33 jguarin200
                --Fourth Side (Opposite to the third one)
450 64 jguarin200
                dxOutput        : out std_logic_vector(W0-1 downto 0);
451
                dyOutput        : out std_logic_vector(W0-1 downto 0);
452
                dzOutput        : out std_logic_vector(W0-1 downto 0);
453 16 jguarin200
 
454 33 jguarin200
                --Fifth Side (Going to the floor right upstairs!)
455 40 jguarin200
                vdOutput        : out std_logic_vector(W1-1 downto 0) -- Dot product.
456 16 jguarin200
 
457 22 jguarin200
                );
458 16 jguarin200
        end component;
459
 
460
        -- K discriminant comparison.
461 33 jguarin200
        -- The vdinput value is the calculation of the ray and the column's sphere dot product. This value should be compared to a sphere constant in order to find out whether the ray intersects
462
        -- or not the sphere. If vdinput is grather or equal than kinput there's an intersection or else when vdinput is less than kinput. If there's an intersection the block sets vdinput at vdoutput,
463
        -- whenever there's no intersection the output is asserted with the maximum positive distance in 32 bits : 0x7fffffff.
464 16 jguarin200
        component kComparisonCell
465 40 jguarin200
                generic (
466
                RK      : string        := "yes";
467
                W1      : integer       := 32
468 16 jguarin200
                );
469 40 jguarin200
                port (
470
                clk,rst         : in std_logic;
471
                scanOut         : in std_logic; -- This signals overrides the 'signed greater or equal than' internal function and allows vdinput to flow upwards.
472
                nxtSphere       : in std_logic; -- Controls when the sphere goes to the next Row. 
473
                pipeOn          : in std_logic; -- Enables / Disable the upwarding flow.
474
                kinput          : in std_logic_vector (W1-1 downto 0);
475
                koutputhor      : out std_logic_vector (W1-1 downto 0);
476
                koutputver      : out std_logic_vector (W1-1 downto 0);  -- K input  flowing to the next floor upstairs (but waits one clock). 
477
                vdinput         : in std_logic_vector (W1-1 downto 0);   -- V.D input.
478
                vdoutput        : out std_logic_vector (W1-1 downto 0)   -- Selected dot product.
479
                );
480 22 jguarin200
        end component;
481 33 jguarin200
        -- Minimun distance Comparison.
482
        -- The reference value, refvd, is the ray minimal intersection distance calculated in the moment of the comparison. 
483
        -- The column value, colvd, is the column sphere and ray intersection distance (if any or else the maximum distance is asserted).
484
 
485
 
486
        component dComparisonCell
487
                generic (
488
                -- V.D, minDistance and selectD Width 
489 40 jguarin200
                W1              : integer := 32;
490 33 jguarin200
                -- Column Sphere ID width. 1 = 2 columns max, 2= 4 colums max... and so on.
491 40 jguarin200
                IDW     : integer := 2;
492 33 jguarin200
                -- Column Id
493
                idCol   : integer := 0
494
                );
495
                port    (
496
                -- The usual control signals.           
497 40 jguarin200
                clk, rst, pipeOn : in std_logic;
498
 
499 61 jguarin200
 
500
                intd    : in    std_logic;
501
                intq    : out   std_logic;
502 33 jguarin200
                -- This is the reference column identification input.
503 40 jguarin200
                cIdd    : in    std_logic_vector (IDW - 1 downto 0);
504 33 jguarin200
                -- This is the result column identification output.
505 61 jguarin200
                cIdq    : out   std_logic_vector (IDW - 1 downto 0);
506
                refk    : in    std_logic_vector (W1 - 1 downto 0); -- This is the columns sphere constant
507
                colk    : in    std_logic_vector (W1 - 1 downto 0); -- This is the reference sphere constant
508
                selk    : out   std_logic_vector (W1 - 1 downto 0); -- This is the selected sphere constant              
509 33 jguarin200
                -- This is the reference projection incoming from the previous cell.
510 40 jguarin200
                refvd   : in    std_logic_vector (W1 - 1 downto 0);
511 33 jguarin200
                -- This is the sphere position over the ray traced vector projection.
512 40 jguarin200
                colvd   : in    std_logic_vector (W1 - 1 downto 0);
513 33 jguarin200
                -- This is the smallest value between refvd and colvd.
514 40 jguarin200
                selvd   : out   std_logic_vector (W1 - 1 downto 0)
515 33 jguarin200
                );
516
        end component;
517
 
518
        component floor0Row
519
                generic (
520
                -- Floor Level Width (V.D width)
521 40 jguarin200
                W1 : integer := 32;
522 33 jguarin200
                -- Vector input Width           
523 40 jguarin200
                W0 : integer := 18;
524 33 jguarin200
                -- Number of Colums
525 40 jguarin200
                C       : integer := 4
526 33 jguarin200
        );
527
        port (
528
                -- The usual control signals. nxtRay should be 0 whenever I want to stop the entire machine.
529
                clk, rst, nxtRay : in std_logic;
530 16 jguarin200
 
531 33 jguarin200
                -- Clk, Rst, the usual control signals.
532
                -- enabled, the machine is running when this input is set.
533
                -- enabled, all the counters begin again.
534 40 jguarin200
                nxtSphere : in std_logic_vector (C-1 downto 0);
535 33 jguarin200
 
536
 
537
                -- Input Values. 
538
                -- The ray input vector.
539 40 jguarin200
                iRayx: in std_logic_vector (W0 - 1 downto 0);
540
                iRayy: in std_logic_vector (W0 - 1 downto 0);
541
                iRayz: in std_logic_vector (W0 - 1 downto 0);
542 33 jguarin200
 
543
                -- The spheres x position (sphere centers) input vectors.
544 40 jguarin200
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
545 33 jguarin200
                -- The spheres y position (sphere centers) input vectors.
546 40 jguarin200
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
547 33 jguarin200
                -- The spheres z position (sphere centers) input vectors.
548 40 jguarin200
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
549 33 jguarin200
                -- The spheres x position (sphere centers) output vectors.
550 40 jguarin200
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
551 33 jguarin200
                -- The spheres y positions (sphere centes) output vectors.
552 40 jguarin200
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
553 33 jguarin200
                -- The spheres z positions (sphere centers) output vectors.             
554 40 jguarin200
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
555 33 jguarin200
 
556
                -- Output Values
557
                -- The ray output vector.
558 40 jguarin200
                oRayx: out std_logic_vector (W0 - 1 downto 0);
559
                oRayy: out std_logic_vector (W0 - 1 downto 0);
560
                oRayz: out std_logic_vector (W0 - 1 downto 0);
561 33 jguarin200
 
562
                -- The dot product result from each dot prod cell.
563 40 jguarin200
                vdOutput : out std_logic_vector (W1*C - 1 downto 0)
564 33 jguarin200
                );
565
        end component;
566
 
567
        -- In this level the V.D results from floor 0 are compared whether they are greater or equal than column's sphere K constants, in order to find if there's an intersection per column or not.
568
        -- When any comparison is true, meaning VD value greater or equal than K, the outgoing value to floor2 level is the same VD, if not the outgoing value is 0x7fffffff (the maximum)
569
        -- distance value.
570
 
571
        component floor1Row
572
        generic (
573
 
574
                -- Vector input Width   
575 40 jguarin200
                W1 : integer := 32;
576 33 jguarin200
                -- Number of Colums
577 40 jguarin200
                C       : integer := 4
578 33 jguarin200
        );
579
        port (
580
 
581
                -- Input Control Signals, pipe on is one when raysr going on. 
582
                clk, rst        : in std_logic;
583
                pipeOn          : in std_logic;
584
 
585
                -- Clk, Rst, the usual control signals.
586 40 jguarin200
                nxtSphere       : in std_logic_vector (C-1 downto 0);
587 33 jguarin200
 
588
                -- VD Input / Output.
589 40 jguarin200
                vdInput : in std_logic_vector (W1*C-1 downto 0);
590
                vdOutput: out std_logic_vector (W1*C-1 downto 0);
591 33 jguarin200
 
592
                -- K Input / Output.
593 40 jguarin200
                kInput  : in std_logic_vector (W1*C - 1 downto 0);
594
                kOutput : out std_logic_vector (W1*C - 1 downto 0)
595 33 jguarin200
        );
596
        end component;
597
 
598
        -- This level takes the -on the moment smalles distance-- value per ray in the extreme left, and starts making comparisons from left to right, one comparison each clock and so on, searching for the smallest V.D value in the row incomung from the floor1 level. When the ray has finished crossing throguh all the spheres in the scene, the row extreme right value will be the smallest V.D found along with an ID of the sphere intersected. This is the goal of the intersection architecture : to find out which is the closest sphere intersected by a particular ray. 
599
 
600
        component floor2Row
601
        generic (
602
                -- Vector input Width
603 40 jguarin200
                W1 : integer := 32;
604 33 jguarin200
                -- ID Column width
605 40 jguarin200
                IDW : integer := 2;
606 33 jguarin200
                -- Number of Colums
607 40 jguarin200
                C       : integer := 4
608 33 jguarin200
        );
609
        port (
610
                -- Input Control Signal
611
                -- Clk, Rst, the usual control signals.
612
                clk, rst, pipeOn: in std_logic;
613
 
614
                -- Input Values
615
                -- Reference VD, the "at the moment" smallest VD sphere ray projection value.
616 40 jguarin200
                refvd   : in std_logic_vector (W1-1 downto 0);
617 33 jguarin200
 
618
                -- The smallest VD, value found.
619 40 jguarin200
                selvd   : out std_logic_vector (W1-1 downto 0);
620 33 jguarin200
 
621
                -- The column's sphere ray projection value.
622 40 jguarin200
                colvd   : in std_logic_vector (W1*C-1 downto 0);
623 33 jguarin200
                -- The smallest VD projection value column id.
624 40 jguarin200
                colid   : out std_logic_vector (IDW-1 downto 0);
625 33 jguarin200
                -- The intersection signal (1 on intersection else 0).
626
                inter   : out std_logic
627
        );
628
        end component;
629
 
630
        component rayxsphereGrid
631
        generic (
632
                -- Width of Column identificator.
633
                IDW     : integer := 2;
634
                -- Number of Columns.
635
                C       : integer := 4;
636
                -- Input rays width.
637
                W0      : integer := 18;
638
                -- Dot products and spheres constant width
639 40 jguarin200
                W1      : integer := 32
640 33 jguarin200
 
641
                );
642
        port (
643
                -- The usual control signals.
644
                clk,rst         : in std_logic;
645
 
646
                -- Grid, rays and sphere flow through control signals.
647
                pipeOn          : in std_logic;
648
                nxtSphere       : in std_logic_vector (C-1 downto 0);
649
 
650
                -- R-F0
651
                -- Input Values. 
652
                -- The ray input vector.
653
                iRayx: in std_logic_vector (W0 - 1 downto 0);
654
                iRayy: in std_logic_vector (W0 - 1 downto 0);
655
                iRayz: in std_logic_vector (W0 - 1 downto 0);
656
                -- The spheres x position (sphere centers) input vectors.
657
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
658
                -- The spheres y position (sphere centers) input vectors.
659
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
660
                -- The spheres z position (sphere centers) input vectors.
661
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
662
                -- The spheres x position (sphere centers) output vectors.
663
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
664
                -- The spheres y positions (sphere centes) output vectors.
665
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
666
                -- The spheres z positions (sphere centers) output vectors.             
667
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
668
                -- Output Values
669
                -- The ray output vector.
670
                oRayx: out std_logic_vector (W0 - 1 downto 0);
671
                oRayy: out std_logic_vector (W0 - 1 downto 0);
672
                oRayz: out std_logic_vector (W0 - 1 downto 0);
673
 
674
                -- R-F1
675
                -- K Input / Output.
676
                kInput  : in std_logic_vector (C*W1 - 1 downto 0);
677 40 jguarin200
                kOutput : out std_logic_vector (C*W1 - 1 downto 0);
678 33 jguarin200
 
679
                --R-F2
680
                -- Input Values
681
                refvd   : in std_logic_vector (W1-1 downto 0);
682
                selvd   : out std_logic_vector (W1-1 downto 0);
683
                colid   : out std_logic_vector (IDW-1 downto 0);
684
                inter   : out std_logic
685
                );
686
        end component;
687
        component gridCube
688
        generic (
689
                -- Depth
690
                D       : integer := 4;
691
                -- ID width.
692
                IDW     : integer := 2;
693
                -- Number of Columns.
694
                C       : integer := 4;
695
                -- Input rays width.
696
                W0      : integer := 18;
697
                -- Dot products and spheres constant width
698 40 jguarin200
                W1      : integer := 32
699 33 jguarin200
 
700
                );
701
        port (
702
                        -- The usual control signals.
703
                clk,rst : in std_logic;
704
 
705
                -- Grid, rays and sphere flow through control signals.
706
                pipeOn                  : in std_logic;
707
                -- The same column nxtSphere signal control..... regardless the Cube Depth.
708
                nxtSphere               : in std_logic_vector (C-1 downto 0);
709
 
710
                -- R-F0
711
                -- Input Values. 
712
                -- The ray input vector. 
713
                iRayx: in std_logic_vector (D*W0 - 1 downto 0);
714
                iRayy: in std_logic_vector (D*W0 - 1 downto 0);
715
                iRayz: in std_logic_vector (D*W0 - 1 downto 0);
716
                -- The spheres x position (sphere centers) input vectors.
717
                iSphrCenterx: in std_logic_vector (C*W0 - 1 downto 0);
718
                -- The spheres y position (sphere centers) input vectors.
719
                iSphrCentery: in std_logic_vector (C*W0 - 1 downto 0);
720
                -- The spheres z position (sphere centers) input vectors.
721
                iSphrCenterz: in std_logic_vector (C*W0 - 1 downto 0);
722
                -- The spheres x position (sphere centers) output vectors.
723
                oSphrCenterx: out std_logic_vector (C*W0 - 1 downto 0);
724
                -- The spheres y positions (sphere centes) output vectors.
725
                oSphrCentery: out std_logic_vector (C*W0 - 1 downto 0);
726
                -- The spheres z positions (sphere centers) output vectors.             
727
                oSphrCenterz: out std_logic_vector (C*W0 - 1 downto 0);
728
                -- Output Values
729
                -- The ray output vector.
730
                oRayx: out std_logic_vector (D*W0 - 1 downto 0);
731
                oRayy: out std_logic_vector (D*W0 - 1 downto 0);
732
                oRayz: out std_logic_vector (D*W0 - 1 downto 0);
733
 
734
                -- R-F1
735
                -- K Input / Output.
736
                kInput  : in std_logic_vector (C*W1 - 1 downto 0);
737 40 jguarin200
                kOutput : out std_logic_vector (C*W1 - 1 downto 0);
738 33 jguarin200
 
739
                --R-F2
740
                -- Input Values
741
                refvd   : in std_logic_vector (D*W1-1 downto 0);
742
                selvd   : out std_logic_vector (D*W1-1 downto 0);
743
                colid   : out std_logic_vector (D*IDW-1 downto 0);
744
                inter   : out std_logic_vector (D-1 downto 0)
745
                );
746
        end component;
747 22 jguarin200
end powerGrid;

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