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1 65 jguarin200
library ieee;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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entity r2 is
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        port (
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                clk, ena: in std_logic; -- The usual control signals.
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                wen             : in std_logic_vector   (3 downto 0);
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                add             : in std_logic_vector   (9 downto 0);
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                datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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                Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                K               : out std_logic_vector  (BUSW-1 downto 0)
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        );
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end entity;
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architecture rtl of r8 is
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begin
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        -- K Register
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        bt21_inst : bt21
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                port map (
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                        address => add,
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                        clken   => ena,
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                        clock   => clk,
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                        data    => datain,
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                        wren    => wen(0),
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                        q               => K
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                );
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        --      Vx, Vy, VZ registers
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        bt24x : bt24
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                port map (
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                        address => add,
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                        clken   => ena,
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                        clock   => clk,
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                        data    => datain,
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                        wren    => wen(3),
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                        q               => Vx
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                );
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        bt24y : bt24
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                port map (
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                        address => add,
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                        clken   => ena,
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                        clock   => clk,
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                        data    => datain,
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                        wren    => wen(2),
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                        q               => Vy
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                );
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        bt24z : bt24
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                port map (
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                        address => add,
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                        clken   => ena,
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                        clock   => clk,
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                        data    => datain,
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                        wren    => wen(1),
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                        q               => Vz
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                );
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end;

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