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1 65 jguarin200
library ieee;
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use ieee.std_logic_1164.all;
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use work.powerGrid.all;
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entity rop1 is
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        generic (
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                SZMODE  : integer       := SZBETA       -- By default use the 50% of the max memory for sphere register block.
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        );
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        port (
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                clk, ena: in std_logic; -- The usual control signals.
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                wen             : in std_logic_vector   (3 downto 0);
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                add             : in std_logic_vector   (REGSZADD(OP1)-SZMODE downto 0);
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                datain  : in std_logic_vector   (BUSW-1 downto 0);-- incoming data from 32 bits width bus.
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                Vx              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                Vy              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                Vz              : out std_logic_vector  (HBUSW-1 downto 0); -- outcoming data to 54 bit width bus multiplexer selector and intersection test cube.
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                K               : out std_logic_vector  (BUSW-1 downto 0)
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        );
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end entity;
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architecture rtl of rop1 is
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begin
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        if SZMODE = SZALFA generate
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                r8_inst : r8
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                port map (
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                        clk             => clk,
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                        ena             => ena,
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                        wen             => wen,
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                        add             => add,
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                        datain  => datain,
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                        Vx              => Vx,
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                        Vy              => Vy,
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                        Vz              => Vz,
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                        K               => K
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                );
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        end generate
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        if SZMODE = SZBETA generate
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                r4_inst : r4
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                port map (
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                        clk             => clk,
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                        ena             => ena,
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                        wen             => wen,
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                        add             => add,
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                        datain  => datain,
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                        Vx              => Vx,
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                        Vy              => Vy,
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                        Vz              => Vz,
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                        K               => K
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                );
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        end generate
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end rtl;

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